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seeq8005.c revision 1.53
      1 /* $NetBSD: seeq8005.c,v 1.52 2014/08/10 16:44:35 tls Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2000, 2001 Ben Harris
      5  * Copyright (c) 1995-1998 Mark Brinicombe
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by Mark Brinicombe
     19  *	for the NetBSD Project.
     20  * 4. The name of the company nor the name of the author may be used to
     21  *    endorse or promote products derived from this software without specific
     22  *    prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     25  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     27  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     34  * SUCH DAMAGE.
     35  */
     36 /*
     37  * seeq8005.c - SEEQ 8005 device driver
     38  */
     39 /*
     40  * This driver currently supports the following chips:
     41  * SEEQ 8005 Advanced Ethernet Data Link Controller
     42  * SEEQ 80C04 Ethernet Data Link Controller
     43  * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller
     44  */
     45 /*
     46  * More information on the 8004 and 8005 AEDLC controllers can be found in
     47  * the SEEQ Technology Inc 1992 Data Comm Devices data book.
     48  *
     49  * This data book may no longer be available as these are rather old chips
     50  * (1991 - 1993)
     51  */
     52 /*
     53  * This driver is based on the arm32 ea(4) driver, hence the names of many
     54  * of the functions.
     55  */
     56 /*
     57  * Bugs/possible improvements:
     58  *	- Does not currently support DMA
     59  *	- Does not transmit multiple packets in one go
     60  *	- Does not support 8-bit busses
     61  */
     62 
     63 #include <sys/cdefs.h>
     64 __KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.52 2014/08/10 16:44:35 tls Exp $");
     65 
     66 #include <sys/param.h>
     67 #include <sys/systm.h>
     68 #include <sys/endian.h>
     69 #include <sys/errno.h>
     70 #include <sys/ioctl.h>
     71 #include <sys/mbuf.h>
     72 #include <sys/socket.h>
     73 #include <sys/syslog.h>
     74 #include <sys/device.h>
     75 
     76 #include <net/if.h>
     77 #include <net/if_dl.h>
     78 #include <net/if_types.h>
     79 #include <net/if_ether.h>
     80 #include <net/if_media.h>
     81 
     82 #include <net/bpf.h>
     83 #include <net/bpfdesc.h>
     84 
     85 #include <sys/rndsource.h>
     86 
     87 #include <sys/bus.h>
     88 #include <sys/intr.h>
     89 
     90 #include <dev/ic/seeq8005reg.h>
     91 #include <dev/ic/seeq8005var.h>
     92 
     93 /*#define SEEQ_DEBUG*/
     94 
     95 /* for debugging convenience */
     96 #ifdef SEEQ8005_DEBUG
     97 #define SEEQ_DEBUG_MISC		1
     98 #define SEEQ_DEBUG_TX		2
     99 #define SEEQ_DEBUG_RX		4
    100 #define SEEQ_DEBUG_PKT		8
    101 #define SEEQ_DEBUG_TXINT	16
    102 #define SEEQ_DEBUG_RXINT	32
    103 int seeq8005_debug = 0;
    104 #define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; }
    105 #else
    106 #define DPRINTF(f, x)
    107 #endif
    108 
    109 #ifndef EA_TX_BUFFER_SIZE
    110 #define EA_TX_BUFFER_SIZE		0x800		/* (> ETHER_MAX_LEN) */
    111 #endif
    112 #ifndef EA_TX_BUFFER_COUNT
    113 #define EA_TX_BUFFER_COUNT		1		/* (> 0) */
    114 #endif
    115 
    116 #define SEEQ_READ16(sc, iot, ioh, reg)					\
    117 	((sc)->sc_flags & SF_8BIT ?					\
    118 	    (bus_space_read_1((iot), (ioh), (reg)) |			\
    119 	     (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) :	\
    120 	    (bus_space_read_2((iot), (ioh), (reg))))
    121 
    122 #define SEEQ_WRITE16(sc, iot, ioh, reg, val) do {			\
    123 	if ((sc)->sc_flags & SF_8BIT) {					\
    124 		bus_space_write_1((iot), (ioh), (reg), (val) & 0xff);	\
    125 		bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8);	\
    126 	} else								\
    127 		bus_space_write_2((iot), (ioh), (reg), (val));		\
    128 } while (/*CONSTCOND*/0)
    129 
    130 /*
    131  * prototypes
    132  */
    133 
    134 static int ea_init(struct ifnet *);
    135 static int ea_ioctl(struct ifnet *, u_long, void *);
    136 static void ea_start(struct ifnet *);
    137 static void ea_watchdog(struct ifnet *);
    138 static void ea_chipreset(struct seeq8005_softc *);
    139 static void ea_ramtest(struct seeq8005_softc *);
    140 static int ea_stoptx(struct seeq8005_softc *);
    141 static int ea_stoprx(struct seeq8005_softc *);
    142 static void ea_stop(struct ifnet *, int);
    143 static void ea_await_fifo_empty(struct seeq8005_softc *);
    144 static void ea_await_fifo_full(struct seeq8005_softc *);
    145 static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t);
    146 static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t);
    147 static void ea_select_buffer(struct seeq8005_softc *, int);
    148 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *);
    149 static void ea_read(struct seeq8005_softc *, int, int);
    150 static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *);
    151 static void ea_txint(struct seeq8005_softc *);
    152 static void ea_rxint(struct seeq8005_softc *);
    153 static void ea_txpacket(struct seeq8005_softc *);
    154 static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int);
    155 static void ea_mc_reset(struct seeq8005_softc *);
    156 static void ea_mc_reset_8004(struct seeq8005_softc *);
    157 static void ea_mc_reset_8005(struct seeq8005_softc *);
    158 static int ea_mediachange(struct ifnet *);
    159 static void ea_mediastatus(struct ifnet *, struct ifmediareq *);
    160 
    161 static u_char* padbuf = NULL;
    162 
    163 
    164 /*
    165  * Attach chip.
    166  */
    167 
    168 void
    169 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media,
    170     int nmedia, int defmedia)
    171 {
    172 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    173 	bus_space_tag_t iot = sc->sc_iot;
    174 	bus_space_handle_t ioh = sc->sc_ioh;
    175 	u_int id;
    176 
    177 	KASSERT(myaddr != NULL);
    178 	printf(" address %s", ether_sprintf(myaddr));
    179 
    180 	/* Stop the board. */
    181 
    182 	ea_chipreset(sc);
    183 
    184 	/* Work out data bus width. */
    185 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234);
    186 	if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) {
    187 		/* Try 8-bit mode */
    188 		sc->sc_flags |= SF_8BIT;
    189 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234);
    190 		if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) {
    191 			aprint_normal("\n");
    192 			aprint_error_dev(sc->sc_dev, "Cannot determine data bus width\n");
    193 			return;
    194 		}
    195 	}
    196 
    197 	printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16);
    198 
    199 	/* Get the product ID */
    200 
    201 	ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID);
    202 	id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN);
    203 
    204 	switch (id & SEEQ_PRODUCTID_MASK) {
    205 	case SEEQ_PRODUCTID_8004:
    206 		sc->sc_variant = SEEQ_8004;
    207 		switch (id & SEEQ_PRODUCTID_REV_MASK) {
    208 		case SEEQ_PRODUCTID_REV_80C04:
    209 			printf(", SEEQ 80C04\n");
    210 			break;
    211 		case SEEQ_PRODUCTID_REV_80C04A:
    212 			printf(", SEEQ 80C04A\n");
    213 			break;
    214 		default:
    215 			/* Unknown SEEQ 8004 variants */
    216 			printf(", SEEQ 8004 rev %x\n",
    217 			    id & SEEQ_PRODUCTID_REV_MASK);
    218 			break;
    219 		}
    220 		break;
    221 	default:	/* XXX */
    222 		sc->sc_variant = SEEQ_8005;
    223 		printf(", SEEQ 8005\n");
    224 		break;
    225 	}
    226 
    227 	/* Both the 8004 and 8005 are designed for 64K Buffer memory */
    228 	sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE;
    229 
    230 	/*
    231 	 * Set up tx and rx buffers.
    232 	 *
    233 	 * We set aside EA_TX_BUFFER_SIZE * EA_TX_BUFFER_COUNT for TX
    234 	 * buffers and the rest for RX buffers
    235 	 */
    236 	sc->sc_tx_bufs = EA_TX_BUFFER_COUNT;
    237 	sc->sc_tx_bufsize = sc->sc_tx_bufs * EA_TX_BUFFER_SIZE;
    238 	sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize;
    239 	sc->sc_enabled = 0;
    240 
    241 	/* Test the RAM */
    242 	ea_ramtest(sc);
    243 
    244 	printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB",
    245 	    device_xname(sc->sc_dev), sc->sc_buffersize >> 10,
    246 	    sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10);
    247 
    248 	if (padbuf == NULL) {
    249 		padbuf = malloc(ETHER_MIN_LEN - ETHER_CRC_LEN, M_DEVBUF,
    250 		    M_ZERO | M_NOWAIT);
    251 		if (padbuf == NULL) {
    252 			aprint_error_dev(sc->sc_dev, "can't allocate pad buffer\n");
    253 			return;
    254 		}
    255 	}
    256 
    257 	/* Initialise ifnet structure. */
    258 
    259 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
    260 	ifp->if_softc = sc;
    261 	ifp->if_start = ea_start;
    262 	ifp->if_ioctl = ea_ioctl;
    263 	ifp->if_init = ea_init;
    264 	ifp->if_stop = ea_stop;
    265 	ifp->if_watchdog = ea_watchdog;
    266 	ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS;
    267 	if (sc->sc_variant == SEEQ_8004)
    268 		ifp->if_flags |= IFF_SIMPLEX;
    269 	IFQ_SET_READY(&ifp->if_snd);
    270 
    271 	/* Initialize media goo. */
    272 	ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus);
    273 	if (media != NULL) {
    274 		int i;
    275 
    276 		for (i = 0; i < nmedia; i++)
    277 			ifmedia_add(&sc->sc_media, media[i], 0, NULL);
    278 		ifmedia_set(&sc->sc_media, defmedia);
    279 	} else {
    280 		ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
    281 		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
    282 	}
    283 
    284 	/* We can support 802.1Q VLAN-sized frames. */
    285 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
    286 
    287 	/* Now we can attach the interface. */
    288 
    289 	if_attach(ifp);
    290 	ether_ifattach(ifp, myaddr);
    291 
    292 	printf("\n");
    293 
    294 	/* After \n because it can print a line of its own. */
    295 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
    296 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
    297 }
    298 
    299 /*
    300  * Media change callback.
    301  */
    302 static int
    303 ea_mediachange(struct ifnet *ifp)
    304 {
    305 	struct seeq8005_softc *sc = ifp->if_softc;
    306 
    307 	if (sc->sc_mediachange)
    308 		return ((*sc->sc_mediachange)(sc));
    309 	return (EINVAL);
    310 }
    311 
    312 /*
    313  * Media status callback.
    314  */
    315 static void
    316 ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
    317 {
    318 	struct seeq8005_softc *sc = ifp->if_softc;
    319 
    320 	if (sc->sc_enabled == 0) {
    321 		ifmr->ifm_active = IFM_ETHER | IFM_NONE;
    322 		ifmr->ifm_status = 0;
    323 		return;
    324 	}
    325 
    326 	if (sc->sc_mediastatus)
    327 		(*sc->sc_mediastatus)(sc, ifmr);
    328 }
    329 
    330 /*
    331  * Test the RAM on the ethernet card.
    332  */
    333 
    334 void
    335 ea_ramtest(struct seeq8005_softc *sc)
    336 {
    337 	bus_space_tag_t iot = sc->sc_iot;
    338 	bus_space_handle_t ioh = sc->sc_ioh;
    339 	int loop;
    340 	u_int sum = 0;
    341 
    342 	/*
    343 	 * Test the buffer memory on the board.
    344 	 * Write simple pattens to it and read them back.
    345 	 */
    346 
    347 	/* Set up the whole buffer RAM for writing */
    348 
    349 	ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP);
    350 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1);
    351 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000);
    352 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2);
    353 
    354 #define SEEQ_RAMTEST_LOOP(value)						\
    355 do {									\
    356 	/* Set the write start address and write a pattern */		\
    357 	ea_writebuf(sc, NULL, 0x0000, 0);				\
    358 	for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2)		\
    359 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value));	\
    360 									\
    361 	/* Set the read start address and verify the pattern */		\
    362 	ea_readbuf(sc, NULL, 0x0000, 0);				\
    363 	for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2)		\
    364 		if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \
    365 			++sum;						\
    366 } while (/*CONSTCOND*/0)
    367 
    368 	SEEQ_RAMTEST_LOOP(loop);
    369 	SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1));
    370 	SEEQ_RAMTEST_LOOP(0xaa55);
    371 	SEEQ_RAMTEST_LOOP(0x55aa);
    372 
    373 	/* Report */
    374 
    375 	if (sum > 0)
    376 		aprint_error_dev(sc->sc_dev, "buffer RAM failed self test, %d faults\n", sum);
    377 }
    378 
    379 
    380 /*
    381  * Stop the tx interface.
    382  *
    383  * Returns 0 if the tx was already stopped or 1 if it was active
    384  */
    385 
    386 static int
    387 ea_stoptx(struct seeq8005_softc *sc)
    388 {
    389 	bus_space_tag_t iot = sc->sc_iot;
    390 	bus_space_handle_t ioh = sc->sc_ioh;
    391 	int timeout;
    392 	int status;
    393 
    394 	DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n"));
    395 
    396 	sc->sc_enabled = 0;
    397 
    398 	status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS);
    399 	if (!(status & SEEQ_STATUS_TX_ON))
    400 		return 0;
    401 
    402 	/* Stop any tx and wait for confirmation */
    403 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    404 			  sc->sc_command | SEEQ_CMD_TX_OFF);
    405 
    406 	timeout = 20000;
    407 	do {
    408 		status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS);
    409 		delay(1);
    410 	} while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0);
    411  	if (timeout == 0)
    412 		log(LOG_ERR, "%s: timeout waiting for tx termination\n",
    413 		    device_xname(sc->sc_dev));
    414 
    415 	/* Clear any pending tx interrupt */
    416 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    417 		   sc->sc_command | SEEQ_CMD_TX_INTACK);
    418 	return 1;
    419 }
    420 
    421 
    422 /*
    423  * Stop the rx interface.
    424  *
    425  * Returns 0 if the tx was already stopped or 1 if it was active
    426  */
    427 
    428 static int
    429 ea_stoprx(struct seeq8005_softc *sc)
    430 {
    431 	bus_space_tag_t iot = sc->sc_iot;
    432 	bus_space_handle_t ioh = sc->sc_ioh;
    433 	int timeout;
    434 	int status;
    435 
    436 	DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n"));
    437 
    438 	status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS);
    439 	if (!(status & SEEQ_STATUS_RX_ON))
    440 		return 0;
    441 
    442 	/* Stop any rx and wait for confirmation */
    443 
    444 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    445 			  sc->sc_command | SEEQ_CMD_RX_OFF);
    446 
    447 	timeout = 20000;
    448 	do {
    449 		status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS);
    450 		delay(1);
    451 	} while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0);
    452 	if (timeout == 0)
    453 		log(LOG_ERR, "%s: timeout waiting for rx termination\n",
    454 		    device_xname(sc->sc_dev));
    455 
    456 	/* Clear any pending rx interrupt */
    457 
    458 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    459 		   sc->sc_command | SEEQ_CMD_RX_INTACK);
    460 	return 1;
    461 }
    462 
    463 
    464 /*
    465  * Stop interface.
    466  * Stop all IO and shut the interface down
    467  */
    468 
    469 /* ARGSUSED */
    470 static void
    471 ea_stop(struct ifnet *ifp, int disable)
    472 {
    473 	struct seeq8005_softc *sc = ifp->if_softc;
    474 	bus_space_tag_t iot = sc->sc_iot;
    475 	bus_space_handle_t ioh = sc->sc_ioh;
    476 
    477 	DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n"));
    478 
    479 	/* Stop all IO */
    480 	ea_stoptx(sc);
    481 	ea_stoprx(sc);
    482 
    483 	/* Disable rx and tx interrupts */
    484 	sc->sc_command &= ~(SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN);
    485 
    486 	/* Clear any pending interrupts */
    487 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    488 			  sc->sc_command | SEEQ_CMD_RX_INTACK |
    489 			  SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK |
    490 			  SEEQ_CMD_BW_INTACK);
    491 
    492 	if (sc->sc_variant == SEEQ_8004) {
    493 		/* Put the chip to sleep */
    494 		ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3);
    495 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN,
    496 		    sc->sc_config3 | SEEQ_CFG3_SLEEP);
    497 	}
    498 
    499 	/* Cancel any watchdog timer */
    500 	sc->sc_ethercom.ec_if.if_timer = 0;
    501 }
    502 
    503 
    504 /*
    505  * Reset the chip
    506  * Following this the software registers are reset
    507  */
    508 
    509 static void
    510 ea_chipreset(struct seeq8005_softc *sc)
    511 {
    512 	bus_space_tag_t iot = sc->sc_iot;
    513 	bus_space_handle_t ioh = sc->sc_ioh;
    514 
    515 	DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n"));
    516 
    517 	/* Reset the controller. Min of 4us delay here */
    518 
    519 	/*
    520 	 * This can be called before we know whether the chip is in 8- or
    521 	 * 16-bit mode, so we do a reset in both modes.  The 16-bit reset is
    522 	 * harmless in 8-bit mode, so we do that second.
    523 	 */
    524 
    525 	/* In 16-bit mode, this will munge the PreamSelect bit. */
    526 	bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8);
    527 	delay(4);
    528 	/* In 8-bit mode, this will zero the bottom half of config reg 2. */
    529 	bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET);
    530 	delay(4);
    531 
    532 	sc->sc_command = 0;
    533 	sc->sc_config1 = 0;
    534 	sc->sc_config2 = 0;
    535 	sc->sc_config3 = 0;
    536 }
    537 
    538 
    539 /*
    540  * If the DMA FIFO's in write mode, wait for it to empty.  Needed when
    541  * switching the FIFO from write to read.  We also use it when changing
    542  * the address for writes.
    543  */
    544 static void
    545 ea_await_fifo_empty(struct seeq8005_softc *sc)
    546 {
    547 	bus_space_tag_t iot = sc->sc_iot;
    548 	bus_space_handle_t ioh = sc->sc_ioh;
    549 	int timeout;
    550 
    551 	timeout = 20000;
    552 	if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) &
    553 	     SEEQ_STATUS_FIFO_DIR) != 0)
    554 		return; /* FIFO is reading anyway. */
    555 	while (--timeout > 0)
    556 		if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) &
    557 		    SEEQ_STATUS_FIFO_EMPTY)
    558 			return;
    559 	log(LOG_ERR, "%s: DMA FIFO failed to empty\n", device_xname(sc->sc_dev));
    560 }
    561 
    562 /*
    563  * Wait for the DMA FIFO to fill before reading from it.
    564  */
    565 static void
    566 ea_await_fifo_full(struct seeq8005_softc *sc)
    567 {
    568 	bus_space_tag_t iot = sc->sc_iot;
    569 	bus_space_handle_t ioh = sc->sc_ioh;
    570 	int timeout;
    571 
    572 	timeout = 20000;
    573 	while (--timeout > 0)
    574 		if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) &
    575 		    SEEQ_STATUS_FIFO_FULL)
    576 			return;
    577 	log(LOG_ERR, "%s: DMA FIFO failed to fill\n", device_xname(sc->sc_dev));
    578 }
    579 
    580 /*
    581  * write to the buffer memory on the interface
    582  *
    583  * The buffer address is set to ADDR.
    584  * If len != 0 then data is copied from the address starting at buf
    585  * to the interface buffer.
    586  * BUF must be usable as a u_int16_t *.
    587  * If LEN is odd, it must be safe to overwrite one extra byte.
    588  */
    589 
    590 static void
    591 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len)
    592 {
    593 	bus_space_tag_t iot = sc->sc_iot;
    594 	bus_space_handle_t ioh = sc->sc_ioh;
    595 
    596 	DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n",
    597 	    SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS)));
    598 
    599 #ifdef DIAGNOSTIC
    600 	if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t)))
    601 		panic("%s: unaligned writebuf", device_xname(sc->sc_dev));
    602 	if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE))
    603 		panic("%s: writebuf out of range", device_xname(sc->sc_dev));
    604 #endif
    605 
    606 	if (addr != -1) {
    607 		ea_await_fifo_empty(sc);
    608 
    609 		ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM);
    610 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    611 		    sc->sc_command | SEEQ_CMD_FIFO_WRITE);
    612 
    613 		ea_await_fifo_empty(sc);
    614 
    615 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr);
    616 	}
    617 
    618 	if (len > 0) {
    619 		if (sc->sc_flags & SF_8BIT)
    620 			bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN,
    621 			    (u_int8_t *)buf, len);
    622 		else
    623 			bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN,
    624 			    /* LINTED: alignment checked above */
    625 			    (u_int16_t *)buf, len / 2);
    626 	}
    627 	if (!(sc->sc_flags & SF_8BIT) && len % 2) {
    628 		/* Write the last byte */
    629 		bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]);
    630 	}
    631 	/* Leave FIFO to empty in the background */
    632 }
    633 
    634 
    635 /*
    636  * read from the buffer memory on the interface
    637  *
    638  * The buffer address is set to ADDR.
    639  * If len != 0 then data is copied from the interface buffer to the
    640  * address starting at buf.
    641  * BUF must be usable as a u_int16_t *.
    642  * If LEN is odd, it must be safe to overwrite one extra byte.
    643  */
    644 
    645 static void
    646 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len)
    647 {
    648 	bus_space_tag_t iot = sc->sc_iot;
    649 	bus_space_handle_t ioh = sc->sc_ioh;
    650 	int runup;
    651 
    652 	DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n",
    653 	    SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len));
    654 
    655 #ifdef DIAGNOSTIC
    656 	if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t)))
    657 		panic("%s: unaligned readbuf", device_xname(sc->sc_dev));
    658 	if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE))
    659 		panic("%s: readbuf out of range", device_xname(sc->sc_dev));
    660 #endif
    661 
    662 	if (addr != -1) {
    663 		/*
    664 		 * SEEQ 80C04 bug:
    665 		 * Starting reading from certain addresses seems to cause
    666 		 * us to get bogus results, so we avoid them.
    667 		 */
    668 		runup = 0;
    669 		if (sc->sc_variant == SEEQ_8004 &&
    670 		    ((addr & 0x00ff) == 0x00ea ||
    671 		     (addr & 0x00ff) == 0x00ee ||
    672 		     (addr & 0x00ff) == 0x00f0))
    673 			runup = (addr & 0x00ff) - 0x00e8;
    674 
    675 		ea_await_fifo_empty(sc);
    676 
    677 		ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM);
    678 
    679 		/*
    680 		 * 80C04 bug workaround.  I found this in the old arm32 "eb"
    681 		 * driver.  I've no idea what it does, but it seems to stop
    682 		 * the chip mangling data so often.
    683 		 */
    684 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    685 		    sc->sc_command | SEEQ_CMD_FIFO_WRITE);
    686 		ea_await_fifo_empty(sc);
    687 
    688 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup);
    689 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    690 		    sc->sc_command | SEEQ_CMD_FIFO_READ);
    691 
    692 		ea_await_fifo_full(sc);
    693 		while (runup > 0) {
    694 			/* LINTED: Reading a volatile _does_ have an effect */
    695 			(void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN);
    696 			runup -= 2;
    697 		}
    698 	}
    699 
    700 	if (len > 0) {
    701 		if (sc->sc_flags & SF_8BIT)
    702 			bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN,
    703 			    (u_int8_t *)buf, len);
    704 		else
    705 			bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN,
    706 			    /* LINTED: pointer alignment checked above */
    707 			    (u_int16_t *)buf, len / 2);
    708 	}
    709 	if (!(sc->sc_flags & SF_8BIT) && len % 2) {
    710 		/* Read the last byte */
    711 		buf[len - 1] = bus_space_read_2(iot, ioh, SEEQ_BUFWIN);
    712 	}
    713 }
    714 
    715 static void
    716 ea_select_buffer(struct seeq8005_softc *sc, int bufcode)
    717 {
    718 
    719 	SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1,
    720 			  sc->sc_config1 | bufcode);
    721 }
    722 
    723 /* Must be called at splnet */
    724 static void
    725 ea_set_address(struct seeq8005_softc *sc, int which, const u_int8_t *ea)
    726 {
    727 	int i;
    728 
    729 	ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which);
    730 	for (i = 0; i < ETHER_ADDR_LEN; ++i)
    731 		SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN,
    732 				  ea[i]);
    733 }
    734 
    735 /*
    736  * Initialize interface.
    737  *
    738  * This should leave the interface in a state for packet reception and
    739  * transmission.
    740  */
    741 
    742 static int
    743 ea_init(struct ifnet *ifp)
    744 {
    745 	struct seeq8005_softc *sc = ifp->if_softc;
    746 	bus_space_tag_t iot = sc->sc_iot;
    747 	bus_space_handle_t ioh = sc->sc_ioh;
    748 	int s;
    749 
    750 	DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n"));
    751 
    752 	s = splnet();
    753 
    754 	/* First, reset the board. */
    755 
    756 	ea_chipreset(sc);
    757 
    758 	/* Set up defaults for the registers */
    759 
    760 	sc->sc_command = 0;
    761 	sc->sc_config1 = 0;
    762 #if BYTE_ORDER == BIG_ENDIAN
    763 	sc->sc_config2 = SEEQ_CFG2_BYTESWAP;
    764 #else
    765 	sc->sc_config2 = 0;
    766 #endif
    767 	sc->sc_config3 = 0;
    768 
    769 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command);
    770 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1);
    771 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
    772 	if (sc->sc_variant == SEEQ_8004) {
    773 		ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3);
    774 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3);
    775 	}
    776 
    777 	/* Write the station address - the receiver must be off */
    778 	ea_set_address(sc, 0, (const u_int8_t *)CLLADDR(ifp->if_sadl));
    779 
    780 	/* Split board memory into Rx and Tx. */
    781 	ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP);
    782 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1);
    783 
    784 	if (sc->sc_variant == SEEQ_8004) {
    785 		/* Make the interface IFF_SIMPLEX. */
    786 		sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE;
    787 		/* Enable reception of long packets (for vlan(4)). */
    788 		sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT;
    789 	}
    790 
    791 	/* Configure rx. */
    792 	ea_mc_reset(sc);
    793 	if (ifp->if_flags & IFF_PROMISC)
    794 		sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS;
    795 	else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004)
    796 		sc->sc_config1 = SEEQ_CFG1_MULTICAST;
    797 	else
    798 		sc->sc_config1 = SEEQ_CFG1_BROADCAST;
    799 	sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0;
    800 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1);
    801 
    802 	/* Setup the Rx pointers */
    803 	sc->sc_rx_ptr = sc->sc_tx_bufsize;
    804 
    805 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr);
    806 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8);
    807 
    808 
    809 	/* Place a NULL header at the beginning of the receive area */
    810 	ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0);
    811 
    812 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000);
    813 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000);
    814 
    815 
    816 	/* Configure TX. */
    817 	DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n"));
    818 
    819 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000);
    820 
    821 	sc->sc_config2 |= SEEQ_CFG2_OUTPUT;
    822 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
    823 
    824 	/* Reset tx buffer pointers */
    825 	sc->sc_tx_cur = 0;
    826 	sc->sc_tx_used = 0;
    827 	sc->sc_tx_next = 0;
    828 
    829 	/* Place a NULL header at the beginning of the transmit area */
    830 	ea_writebuf(sc, NULL, 0x0000, 0);
    831 
    832 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000);
    833 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000);
    834 
    835 	sc->sc_command |= SEEQ_CMD_TX_INTEN;
    836 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command);
    837 
    838 	/* Turn on Rx */
    839 	sc->sc_command |= SEEQ_CMD_RX_INTEN;
    840 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    841 			  sc->sc_command | SEEQ_CMD_RX_ON);
    842 
    843 	/* TX_ON gets set by ea_txpacket when there's something to transmit. */
    844 
    845 
    846 	/* Set flags appropriately. */
    847 	ifp->if_flags |= IFF_RUNNING;
    848 	ifp->if_flags &= ~IFF_OACTIVE;
    849 	sc->sc_enabled = 1;
    850 
    851 	/* And start output. */
    852 	ea_start(ifp);
    853 
    854 	splx(s);
    855 	return 0;
    856 }
    857 
    858 /*
    859  * Start output on interface. Get datagrams from the queue and output them,
    860  * giving the receiver a chance between datagrams. Call only from splnet or
    861  * interrupt level!
    862  */
    863 
    864 static void
    865 ea_start(struct ifnet *ifp)
    866 {
    867 	struct seeq8005_softc *sc = ifp->if_softc;
    868 	int s;
    869 
    870 	s = splnet();
    871 	DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n"));
    872 
    873 	/*
    874 	 * Don't do anything if output is active.  seeq8005intr() will call
    875 	 * us (actually ea_txpacket()) back when the card's ready for more
    876 	 * frames.
    877 	 */
    878 	if (ifp->if_flags & IFF_OACTIVE)
    879 		return;
    880 
    881 	/* Mark interface as output active */
    882 
    883 	ifp->if_flags |= IFF_OACTIVE;
    884 
    885 	/* tx packets */
    886 
    887 	ea_txpacket(sc);
    888 	splx(s);
    889 }
    890 
    891 
    892 /*
    893  * Transfer a packet to the interface buffer and start transmission
    894  *
    895  * Called at splnet()
    896  */
    897 
    898 static void
    899 ea_txpacket(struct seeq8005_softc *sc)
    900 {
    901 	bus_space_tag_t iot = sc->sc_iot;
    902 	bus_space_handle_t ioh = sc->sc_ioh;
    903 	struct mbuf *m0;
    904 	struct ifnet *ifp;
    905 
    906 	ifp = &sc->sc_ethercom.ec_if;
    907 
    908 	/* Dequeue the next packet. */
    909 	IFQ_DEQUEUE(&ifp->if_snd, m0);
    910 
    911 	/* If there's nothing to send, return. */
    912 	if (m0 == NULL) {
    913 		ifp->if_flags &= ~IFF_OACTIVE;
    914 		sc->sc_config2 |= SEEQ_CFG2_OUTPUT;
    915 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
    916 		DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n"));
    917 		return;
    918 	}
    919 
    920 	/* Give the packet to the bpf, if any. */
    921 	bpf_mtap(ifp, m0);
    922 
    923 	DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n"));
    924 
    925 	sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT;
    926 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
    927 
    928 	ea_writembuf(sc, m0, 0x0000);
    929 	m_freem(m0);
    930 
    931 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000);
    932 
    933 	/* Now transmit the datagram. */
    934 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
    935 			  sc->sc_command | SEEQ_CMD_TX_ON);
    936 
    937 	/* Make sure we notice if the chip goes silent on us. */
    938 	ifp->if_timer = 5;
    939 
    940 	DPRINTF(SEEQ_DEBUG_TX,
    941 	    ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS)));
    942 	DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n"));
    943 }
    944 
    945 /*
    946  * Copy a packet from an mbuf to the transmit buffer on the card.
    947  *
    948  * Puts a valid Tx header at the start of the packet, and a null header at
    949  * the end.
    950  */
    951 static int
    952 ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart)
    953 {
    954 	struct mbuf *m;
    955 	int len, nextpacket;
    956 	u_int8_t hdr[4];
    957 
    958 	/*
    959 	 * Copy the datagram to the packet buffer.
    960 	 */
    961 	len = 0;
    962 	for (m = m0; m; m = m->m_next) {
    963 		if (m->m_len == 0)
    964 			continue;
    965 		ea_writebuf(sc, mtod(m, u_char *), bufstart + 4 + len,
    966 		    m->m_len);
    967 		len += m->m_len;
    968 	}
    969 
    970 	if (len < ETHER_MIN_LEN) {
    971 		ea_writebuf(sc, padbuf, bufstart + 4 + len,
    972 		    ETHER_MIN_LEN - len);
    973 		len = ETHER_MIN_LEN;
    974 	}
    975 
    976 	/* Follow it with a NULL packet header */
    977 	memset(hdr, 0, 4);
    978 	ea_writebuf(sc, hdr, bufstart + 4 + len, 4);
    979 
    980 	/* Ok we now have a packet len bytes long in our packet buffer */
    981 	DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len));
    982 
    983 	/* Write the packet header */
    984 	nextpacket = bufstart + len + 4;
    985 	hdr[0] = (nextpacket >> 8) & 0xff;
    986 	hdr[1] = nextpacket & 0xff;
    987 	hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS |
    988 		SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT;
    989 	hdr[3] = 0; /* Status byte -- will be updated by hardware. */
    990 	ea_writebuf(sc, hdr, bufstart, 4);
    991 
    992 	return len;
    993 }
    994 
    995 /*
    996  * Ethernet controller interrupt.
    997  */
    998 
    999 int
   1000 seeq8005intr(void *arg)
   1001 {
   1002 	struct seeq8005_softc *sc = arg;
   1003 	bus_space_tag_t iot = sc->sc_iot;
   1004 	bus_space_handle_t ioh = sc->sc_ioh;
   1005 	int status, handled;
   1006 
   1007 	handled = 0;
   1008 
   1009 	/* Get the controller status */
   1010 	status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS);
   1011 
   1012 	/* Tx interrupt ? */
   1013 	if (status & SEEQ_STATUS_TX_INT) {
   1014 		handled = 1;
   1015 
   1016 		/* Acknowledge the interrupt */
   1017 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
   1018 				  sc->sc_command | SEEQ_CMD_TX_INTACK);
   1019 
   1020 		ea_txint(sc);
   1021 	}
   1022 
   1023 
   1024 	/* Rx interrupt ? */
   1025 	if (status & SEEQ_STATUS_RX_INT) {
   1026 		handled = 1;
   1027 
   1028 		/* Acknowledge the interrupt */
   1029 		SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
   1030 				  sc->sc_command | SEEQ_CMD_RX_INTACK);
   1031 
   1032 		/* Processes the received packets */
   1033 		ea_rxint(sc);
   1034 	}
   1035 
   1036 	if (handled)
   1037 		rnd_add_uint32(&sc->rnd_source, status);
   1038 
   1039 	return handled;
   1040 }
   1041 
   1042 static void
   1043 ea_txint(struct seeq8005_softc *sc)
   1044 {
   1045 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1046 	bus_space_tag_t iot = sc->sc_iot;
   1047 	bus_space_handle_t ioh = sc->sc_ioh;
   1048 	u_int8_t txhdr[4];
   1049 	u_int txstatus;
   1050 
   1051 	ea_readbuf(sc, txhdr, 0x0000, 4);
   1052 
   1053 	DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n",
   1054 	    txhdr[0], txhdr[1], txhdr[2], txhdr[3]));
   1055 	txstatus = txhdr[3];
   1056 
   1057 	/*
   1058 	 * If SEEQ_TXSTAT_COLLISION is set then we received at least
   1059 	 * one collision. On the 8004 we can find out exactly how many
   1060 	 * collisions occurred.
   1061 	 *
   1062 	 * The SEEQ_PKTSTAT_DONE will be set if the transmission has
   1063 	 * completed.
   1064 	 *
   1065 	 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions
   1066 	 * occurred and the packet transmission was aborted.
   1067 	 * This situation is untested as present.
   1068 	 *
   1069 	 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set
   1070 	 * when we deliberately transmit oversized packets (e.g. for
   1071 	 * 802.1Q).
   1072 	 */
   1073 	if (txstatus & SEEQ_TXSTAT_COLLISION) {
   1074 		switch (sc->sc_variant) {
   1075 		case SEEQ_8004: {
   1076 			int colls;
   1077 
   1078 			/*
   1079 			 * The 8004 contains a 4 bit collision count
   1080 			 * in the status register.
   1081 			 */
   1082 
   1083 			/* This appears to be broken on 80C04.AE */
   1084 /*			ifp->if_collisions +=
   1085 			    (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT)
   1086 			    & SEEQ_TXSTAT_COLLISION_MASK;*/
   1087 
   1088 			/* Use the TX Collision register */
   1089 			ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS);
   1090 			colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN);
   1091 			ifp->if_collisions += colls;
   1092 			break;
   1093 		}
   1094 		case SEEQ_8005:
   1095 			/* We known there was at least 1 collision */
   1096 			ifp->if_collisions++;
   1097 			break;
   1098 		}
   1099 	} else if (txstatus & SEEQ_TXSTAT_COLLISION16) {
   1100 		printf("seeq_intr: col16 %x\n", txstatus);
   1101 		ifp->if_collisions += 16;
   1102 		ifp->if_oerrors++;
   1103 	}
   1104 
   1105 	/* Have we completed transmission on the packet ? */
   1106 	if (txstatus & SEEQ_PKTSTAT_DONE) {
   1107 		/* Clear watchdog timer. */
   1108 		ifp->if_timer = 0;
   1109 		ifp->if_flags &= ~IFF_OACTIVE;
   1110 
   1111 		/* Update stats */
   1112 		ifp->if_opackets++;
   1113 
   1114 		/* Tx next packet */
   1115 
   1116 		ea_txpacket(sc);
   1117 	}
   1118 }
   1119 
   1120 static void
   1121 ea_rxint(struct seeq8005_softc *sc)
   1122 {
   1123 	bus_space_tag_t iot = sc->sc_iot;
   1124 	bus_space_handle_t ioh = sc->sc_ioh;
   1125 	u_int addr;
   1126 	int len;
   1127 	int ctrl;
   1128 	int ptr;
   1129 	int status;
   1130 	u_int8_t rxhdr[4];
   1131 	struct ifnet *ifp;
   1132 
   1133 	ifp = &sc->sc_ethercom.ec_if;
   1134 
   1135 
   1136 	/* We start from the last rx pointer position */
   1137 	addr = sc->sc_rx_ptr;
   1138 	sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT;
   1139 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
   1140 
   1141 	do {
   1142 		/* Read rx header */
   1143 		ea_readbuf(sc, rxhdr, addr, 4);
   1144 
   1145 		/* Split the packet header */
   1146 		ptr = (rxhdr[0] << 8) | rxhdr[1];
   1147 		ctrl = rxhdr[2];
   1148 		status = rxhdr[3];
   1149 
   1150 		DPRINTF(SEEQ_DEBUG_RX,
   1151 		    ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n",
   1152 			addr, ptr, ctrl, status));
   1153 
   1154 		/* Zero packet ptr ? then must be null header so exit */
   1155 		if (ptr == 0) break;
   1156 
   1157 		/* Sanity-check the next-packet pointer and flags. */
   1158 		if (__predict_false(ptr < sc->sc_tx_bufsize ||
   1159 		    (ctrl & SEEQ_PKTCMD_TX))) {
   1160 			++ifp->if_ierrors;
   1161 			log(LOG_ERR,
   1162 			    "%s: Rx chain corrupt at %04x (ptr = %04x)\n",
   1163 			    device_xname(sc->sc_dev), addr, ptr);
   1164 			ea_init(ifp);
   1165 			return;
   1166 		}
   1167 
   1168 		/* Get packet length */
   1169 		len = (ptr - addr) - 4;
   1170 
   1171 		if (len < 0)
   1172 			len += sc->sc_rx_bufsize;
   1173 		DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len));
   1174 
   1175 		/* Has the packet rx completed ? if not then exit */
   1176 		if ((status & SEEQ_PKTSTAT_DONE) == 0)
   1177 			break;
   1178 
   1179 		/*
   1180 		 * Did we have any errors? then note error and go to
   1181 		 * next packet
   1182 		 */
   1183 		if (__predict_false(status &
   1184 			(SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR |
   1185 			 SEEQ_RXSTAT_SHORT_FRAME))) {
   1186 			++ifp->if_ierrors;
   1187 			log(LOG_WARNING,
   1188 			    "%s: rx packet error at %04x (err=%02x)\n",
   1189 			    device_xname(sc->sc_dev), addr, status & 0x0f);
   1190 			/* XXX shouldn't need to reset if it's genuine. */
   1191 			ea_init(ifp);
   1192 			return;
   1193 		}
   1194 		/*
   1195 		 * Is the packet too big?  We allow slightly oversize packets
   1196 		 * for vlan(4) and tcpdump purposes, but the rest of the world
   1197 		 * wants incoming packets in a single mbuf cluster.
   1198 		 */
   1199 		if (__predict_false(len > MCLBYTES)) {
   1200 			++ifp->if_ierrors;
   1201 			log(LOG_ERR,
   1202 			    "%s: rx packet size error at %04x (len=%d)\n",
   1203 			    device_xname(sc->sc_dev), addr, len);
   1204 			ea_init(ifp);
   1205 			return;
   1206 		}
   1207 
   1208 		ifp->if_ipackets++;
   1209 		/* Pass data up to upper levels. */
   1210 		ea_read(sc, addr + 4, len);
   1211 
   1212 		addr = ptr;
   1213 	} while (len != 0);
   1214 
   1215 	sc->sc_config2 |= SEEQ_CFG2_OUTPUT;
   1216 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
   1217 
   1218 	DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr));
   1219 
   1220 	/* Store new rx pointer */
   1221 	sc->sc_rx_ptr = addr;
   1222 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8);
   1223 
   1224 	/* Make sure the receiver is on */
   1225 	SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND,
   1226 			  sc->sc_command | SEEQ_CMD_RX_ON);
   1227 }
   1228 
   1229 
   1230 /*
   1231  * Pass a packet up to the higher levels.
   1232  */
   1233 
   1234 static void
   1235 ea_read(struct seeq8005_softc *sc, int addr, int len)
   1236 {
   1237 	struct mbuf *m;
   1238 	struct ifnet *ifp;
   1239 
   1240 	ifp = &sc->sc_ethercom.ec_if;
   1241 
   1242 	/* Pull packet off interface. */
   1243 	m = ea_get(sc, addr, len, ifp);
   1244 	if (m == NULL)
   1245 		return;
   1246 
   1247 	/*
   1248 	 * Check if there's a BPF listener on this interface.
   1249 	 * If so, hand off the raw packet to bpf.
   1250 	 */
   1251 	bpf_mtap(ifp, m);
   1252 
   1253 	(*ifp->if_input)(ifp, m);
   1254 }
   1255 
   1256 /*
   1257  * Pull read data off a interface.  Len is length of data, with local net
   1258  * header stripped.  We copy the data into mbufs.  When full cluster sized
   1259  * units are present we copy into clusters.
   1260  */
   1261 
   1262 struct mbuf *
   1263 ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp)
   1264 {
   1265         struct mbuf *top, **mp, *m;
   1266         int len;
   1267         u_int cp, epkt;
   1268 
   1269         cp = addr;
   1270         epkt = cp + totlen;
   1271 
   1272         MGETHDR(m, M_DONTWAIT, MT_DATA);
   1273         if (m == NULL)
   1274                 return NULL;
   1275         m->m_pkthdr.rcvif = ifp;
   1276         m->m_pkthdr.len = totlen;
   1277         m->m_len = MHLEN;
   1278         top = NULL;
   1279         mp = &top;
   1280 
   1281         while (totlen > 0) {
   1282                 if (top) {
   1283                         MGET(m, M_DONTWAIT, MT_DATA);
   1284                         if (m == NULL) {
   1285                                 m_freem(top);
   1286                                 return NULL;
   1287                         }
   1288                         m->m_len = MLEN;
   1289                 }
   1290                 len = min(totlen, epkt - cp);
   1291                 if (len >= MINCLSIZE) {
   1292                         MCLGET(m, M_DONTWAIT);
   1293                         if (m->m_flags & M_EXT)
   1294                                 m->m_len = len = min(len, MCLBYTES);
   1295                         else
   1296                                 len = m->m_len;
   1297                 } else {
   1298                         /*
   1299                          * Place initial small packet/header at end of mbuf.
   1300                          */
   1301                         if (len < m->m_len) {
   1302                                 if (top == NULL && len + max_linkhdr <= m->m_len)
   1303                                         m->m_data += max_linkhdr;
   1304                                 m->m_len = len;
   1305                         } else
   1306                                 len = m->m_len;
   1307                 }
   1308 		if (top == NULL) {
   1309 			/* Make sure the payload is aligned */
   1310 			char *newdata = (char *)
   1311 			    ALIGN((char*)m->m_data +
   1312 				sizeof(struct ether_header)) -
   1313 			    sizeof(struct ether_header);
   1314 			len -= newdata - m->m_data;
   1315 			m->m_len = len;
   1316 			m->m_data = newdata;
   1317 		}
   1318                 ea_readbuf(sc, mtod(m, u_char *),
   1319 		    cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize,
   1320 		    len);
   1321                 cp += len;
   1322                 *mp = m;
   1323                 mp = &m->m_next;
   1324                 totlen -= len;
   1325                 if (cp == epkt)
   1326                         cp = addr;
   1327         }
   1328 
   1329         return top;
   1330 }
   1331 
   1332 /*
   1333  * Process an ioctl request.  Mostly boilerplate.
   1334  */
   1335 static int
   1336 ea_ioctl(struct ifnet *ifp, u_long cmd, void *data)
   1337 {
   1338 	struct seeq8005_softc *sc = ifp->if_softc;
   1339 	int s, error = 0;
   1340 
   1341 	s = splnet();
   1342 	switch (cmd) {
   1343 
   1344 	default:
   1345 		error = ether_ioctl(ifp, cmd, data);
   1346 		if (error == ENETRESET) {
   1347 			/*
   1348 			 * Multicast list has changed; set the hardware filter
   1349 			 * accordingly.
   1350 			 */
   1351 			if (ifp->if_flags & IFF_RUNNING)
   1352 				ea_mc_reset(sc);
   1353 			error = 0;
   1354 		}
   1355 		break;
   1356 	}
   1357 
   1358 	splx(s);
   1359 	return error;
   1360 }
   1361 
   1362 /* Must be called at splnet() */
   1363 
   1364 static void
   1365 ea_mc_reset(struct seeq8005_softc *sc)
   1366 {
   1367 
   1368 	switch (sc->sc_variant) {
   1369 	case SEEQ_8004:
   1370 		ea_mc_reset_8004(sc);
   1371 		return;
   1372 	case SEEQ_8005:
   1373 		ea_mc_reset_8005(sc);
   1374 		return;
   1375 	}
   1376 }
   1377 
   1378 static void
   1379 ea_mc_reset_8004(struct seeq8005_softc *sc)
   1380 {
   1381 	struct ethercom *ec = &sc->sc_ethercom;
   1382 	struct ifnet *ifp = &ec->ec_if;
   1383 	struct ether_multi *enm;
   1384         u_int32_t crc;
   1385         int i;
   1386         struct ether_multistep step;
   1387         u_int8_t af[8];
   1388 
   1389 	/*
   1390 	 * Set up multicast address filter by passing all multicast addresses
   1391 	 * through a crc generator, and then using bits 2 - 7 as an index
   1392 	 * into the 64 bit logical address filter.  The high order bits
   1393 	 * selects the word, while the rest of the bits select the bit within
   1394 	 * the word.
   1395 	 */
   1396 
   1397 	if (ifp->if_flags & IFF_PROMISC) {
   1398 		ifp->if_flags |= IFF_ALLMULTI;
   1399 		for (i = 0; i < 8; i++)
   1400 			af[i] = 0xff;
   1401 		return;
   1402 	}
   1403 	for (i = 0; i < 8; i++)
   1404 		af[i] = 0;
   1405 	ETHER_FIRST_MULTI(step, ec, enm);
   1406 	while (enm != NULL) {
   1407 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
   1408 		    sizeof(enm->enm_addrlo)) != 0) {
   1409 			/*
   1410 			 * We must listen to a range of multicast addresses.
   1411 			 * For now, just accept all multicasts, rather than
   1412 			 * trying to set only those filter bits needed to match
   1413 			 * the range.  (At this time, the only use of address
   1414 			 * ranges is for IP multicast routing, for which the
   1415 			 * range is big enough to require all bits set.)
   1416 			 */
   1417 			ifp->if_flags |= IFF_ALLMULTI;
   1418 			for (i = 0; i < 8; i++)
   1419 				af[i] = 0xff;
   1420 			break;
   1421 		}
   1422 
   1423 		crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo));
   1424 
   1425 		/* Just want the 6 most significant bits. */
   1426 		crc = (crc >> 2) & 0x3f;
   1427 
   1428 		/* Turn on the corresponding bit in the filter. */
   1429 		af[crc >> 3] |= 1 << (crc & 0x7);
   1430 
   1431 		ETHER_NEXT_MULTI(step, enm);
   1432 	}
   1433 	ifp->if_flags &= ~IFF_ALLMULTI;
   1434 
   1435 	ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST);
   1436 		for (i = 0; i < 8; ++i)
   1437 			bus_space_write_1(sc->sc_iot, sc->sc_ioh,
   1438 			    SEEQ_BUFWIN, af[i]);
   1439 }
   1440 
   1441 static void
   1442 ea_mc_reset_8005(struct seeq8005_softc *sc)
   1443 {
   1444 	struct ether_multi *enm;
   1445 	struct ether_multistep step;
   1446 	int naddr, maxaddrs;
   1447 
   1448 	naddr = 0;
   1449 	maxaddrs = 5;
   1450 	ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm);
   1451 	while (enm != NULL) {
   1452 		/* Have we got space? */
   1453 		if (naddr >= maxaddrs ||
   1454 		    memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) {
   1455 			sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI;
   1456 			ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL);
   1457 			return;
   1458 		}
   1459 		ea_set_address(sc, 1 + naddr, enm->enm_addrlo);
   1460 		sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr;
   1461 		naddr++;
   1462 		ETHER_NEXT_MULTI(step, enm);
   1463 	}
   1464 	for (; naddr < maxaddrs; naddr++)
   1465 		sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr);
   1466 	SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1,
   1467 			  sc->sc_config1);
   1468 }
   1469 
   1470 /*
   1471  * Device timeout routine.
   1472  */
   1473 
   1474 static void
   1475 ea_watchdog(struct ifnet *ifp)
   1476 {
   1477 	struct seeq8005_softc *sc = ifp->if_softc;
   1478 
   1479 	log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n",
   1480 	    device_xname(sc->sc_dev),
   1481 	    SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS));
   1482 	ifp->if_oerrors++;
   1483 
   1484 	/* Kick the interface */
   1485 
   1486 	ea_init(ifp);
   1487 
   1488 	ifp->if_timer = 0;
   1489 }
   1490 
   1491 /* End of seeq8005.c */
   1492