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smc91cxx.c revision 1.89
      1 /*	$NetBSD: smc91cxx.c,v 1.88 2014/08/10 16:44:35 tls Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9  * NASA Ames Research Center.
     10  *
     11  * Redistribution and use in source and binary forms, with or without
     12  * modification, are permitted provided that the following conditions
     13  * are met:
     14  * 1. Redistributions of source code must retain the above copyright
     15  *    notice, this list of conditions and the following disclaimer.
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30  * POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 /*
     34  * Copyright (c) 1996 Gardner Buchanan <gbuchanan (at) shl.com>
     35  * All rights reserved.
     36  *
     37  * Redistribution and use in source and binary forms, with or without
     38  * modification, are permitted provided that the following conditions
     39  * are met:
     40  * 1. Redistributions of source code must retain the above copyright
     41  *    notice, this list of conditions and the following disclaimer.
     42  * 2. Redistributions in binary form must reproduce the above copyright
     43  *    notice, this list of conditions and the following disclaimer in the
     44  *    documentation and/or other materials provided with the distribution.
     45  * 3. All advertising materials mentioning features or use of this software
     46  *    must display the following acknowledgement:
     47  *	This product includes software developed by Gardner Buchanan.
     48  * 4. The name of Gardner Buchanan may not be used to endorse or promote
     49  *    products derived from this software without specific prior written
     50  *    permission.
     51  *
     52  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     53  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     54  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     55  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     56  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     57  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     58  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     59  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     60  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     61  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     62  *
     63  *   from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp
     64  */
     65 
     66 /*
     67  * Core driver for the SMC 91Cxx family of Ethernet chips.
     68  *
     69  * Memory allocation interrupt logic is drived from an SMC 91C90 driver
     70  * written for NetBSD/amiga by Michael Hitch.
     71  */
     72 
     73 #include <sys/cdefs.h>
     74 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.88 2014/08/10 16:44:35 tls Exp $");
     75 
     76 #include "opt_inet.h"
     77 
     78 #include <sys/param.h>
     79 #include <sys/systm.h>
     80 #include <sys/mbuf.h>
     81 #include <sys/syslog.h>
     82 #include <sys/socket.h>
     83 #include <sys/device.h>
     84 #include <sys/kernel.h>
     85 #include <sys/malloc.h>
     86 #include <sys/ioctl.h>
     87 #include <sys/errno.h>
     88 #include <sys/rndsource.h>
     89 
     90 #include <sys/bus.h>
     91 #include <sys/intr.h>
     92 
     93 #include <net/if.h>
     94 #include <net/if_dl.h>
     95 #include <net/if_ether.h>
     96 #include <net/if_media.h>
     97 
     98 #ifdef INET
     99 #include <netinet/in.h>
    100 #include <netinet/if_inarp.h>
    101 #include <netinet/in_systm.h>
    102 #include <netinet/in_var.h>
    103 #include <netinet/ip.h>
    104 #endif
    105 
    106 #include <net/bpf.h>
    107 #include <net/bpfdesc.h>
    108 
    109 #include <dev/mii/mii.h>
    110 #include <dev/mii/miivar.h>
    111 #include <dev/mii/mii_bitbang.h>
    112 
    113 #include <dev/ic/smc91cxxreg.h>
    114 #include <dev/ic/smc91cxxvar.h>
    115 
    116 #ifndef __BUS_SPACE_HAS_STREAM_METHODS
    117 #define bus_space_write_multi_stream_2 bus_space_write_multi_2
    118 #define bus_space_write_multi_stream_4 bus_space_write_multi_4
    119 #define bus_space_read_multi_stream_2  bus_space_read_multi_2
    120 #define bus_space_read_multi_stream_4  bus_space_read_multi_4
    121 
    122 #define bus_space_write_stream_4 bus_space_write_4
    123 #define bus_space_read_stream_4  bus_space_read_4
    124 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
    125 
    126 /* XXX Hardware padding doesn't work yet(?) */
    127 #define	SMC91CXX_SW_PAD
    128 
    129 const char *smc91cxx_idstrs[] = {
    130 	NULL,				/* 0 */
    131 	NULL,				/* 1 */
    132 	NULL,				/* 2 */
    133 	"SMC91C90/91C92",		/* 3 */
    134 	"SMC91C94/91C96",		/* 4 */
    135 	"SMC91C95",			/* 5 */
    136 	NULL,				/* 6 */
    137 	"SMC91C100",			/* 7 */
    138 	"SMC91C100FD",			/* 8 */
    139 	"SMC91C111",			/* 9 */
    140 	NULL,				/* 10 */
    141 	NULL,				/* 11 */
    142 	NULL,				/* 12 */
    143 	NULL,				/* 13 */
    144 	NULL,				/* 14 */
    145 	NULL,				/* 15 */
    146 };
    147 
    148 /* Supported media types. */
    149 static const int smc91cxx_media[] = {
    150 	IFM_ETHER|IFM_10_T,
    151 	IFM_ETHER|IFM_10_5,
    152 };
    153 #define	NSMC91CxxMEDIA	(sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0]))
    154 
    155 /*
    156  * MII bit-bang glue.
    157  */
    158 u_int32_t smc91cxx_mii_bitbang_read(device_t);
    159 void smc91cxx_mii_bitbang_write(device_t, u_int32_t);
    160 
    161 static const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = {
    162 	smc91cxx_mii_bitbang_read,
    163 	smc91cxx_mii_bitbang_write,
    164 	{
    165 		MR_MDO,		/* MII_BIT_MDO */
    166 		MR_MDI,		/* MII_BIT_MDI */
    167 		MR_MCLK,	/* MII_BIT_MDC */
    168 		MR_MDOE,	/* MII_BIT_DIR_HOST_PHY */
    169 		0,		/* MII_BIT_DIR_PHY_HOST */
    170 	}
    171 };
    172 
    173 /* MII callbacks */
    174 int	smc91cxx_mii_readreg(device_t, int, int);
    175 void	smc91cxx_mii_writereg(device_t, int, int, int);
    176 void	smc91cxx_statchg(struct ifnet *);
    177 void	smc91cxx_tick(void *);
    178 
    179 int	smc91cxx_mediachange(struct ifnet *);
    180 void	smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *);
    181 
    182 int	smc91cxx_set_media(struct smc91cxx_softc *, int);
    183 
    184 void	smc91cxx_init(struct smc91cxx_softc *);
    185 void	smc91cxx_read(struct smc91cxx_softc *);
    186 void	smc91cxx_reset(struct smc91cxx_softc *);
    187 void	smc91cxx_start(struct ifnet *);
    188 uint8_t	smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *);
    189 void	smc91cxx_resume(struct smc91cxx_softc *);
    190 void	smc91cxx_stop(struct smc91cxx_softc *);
    191 void	smc91cxx_watchdog(struct ifnet *);
    192 int	smc91cxx_ioctl(struct ifnet *, u_long, void *);
    193 
    194 static inline int ether_cmp(const void *, const void *);
    195 static inline int
    196 ether_cmp(const void *va, const void *vb)
    197 {
    198 	const u_int8_t *a = va;
    199 	const u_int8_t *b = vb;
    200 
    201 	return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) ||
    202 		(a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0]));
    203 }
    204 
    205 static inline void
    206 smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh,
    207 	uint8_t mask)
    208 {
    209 	KDASSERT((mask & IM_ERCV_INT) == 0);
    210 #ifdef SMC91CXX_NO_BYTE_WRITE
    211 	bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8);
    212 #else
    213 	bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask);
    214 #endif
    215 	KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT));
    216 }
    217 
    218 static inline void
    219 smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh,
    220 	uint8_t ack, uint8_t mask)
    221 {
    222 #ifdef SMC91CXX_NO_BYTE_WRITE
    223 	bus_space_write_2(bst, bsh, INTR_ACK_REG_B, ack | (mask << 8));
    224 #else
    225 	bus_space_write_1(bst, bsh, INTR_ACK_REG_B, ack);
    226 #endif
    227 	KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT));
    228 }
    229 
    230 void
    231 smc91cxx_attach(struct smc91cxx_softc *sc, u_int8_t *myea)
    232 {
    233 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    234 	bus_space_tag_t bst = sc->sc_bst;
    235 	bus_space_handle_t bsh = sc->sc_bsh;
    236 	struct ifmedia *ifm = &sc->sc_mii.mii_media;
    237 	const char *idstr;
    238 	u_int32_t miicapabilities;
    239 	u_int16_t tmp;
    240 	u_int8_t enaddr[ETHER_ADDR_LEN];
    241 	int i, aui, mult, scale, memsize;
    242 	char pbuf[9];
    243 
    244 	tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W);
    245 	/* check magic number */
    246 	if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
    247 		aprint_error_dev(sc->sc_dev,
    248 		     "failed to detect chip, bsr=%04x\n", tmp);
    249 		return;
    250 	}
    251 
    252 	/* Make sure the chip is stopped. */
    253 	smc91cxx_stop(sc);
    254 
    255 	SMC_SELECT_BANK(sc, 3);
    256 	tmp = bus_space_read_2(bst, bsh, REVISION_REG_W);
    257 	sc->sc_chipid = RR_ID(tmp);
    258 	idstr = smc91cxx_idstrs[sc->sc_chipid];
    259 
    260 	aprint_normal_dev(sc->sc_dev, "");
    261 	if (idstr != NULL)
    262 		aprint_normal("%s, ", idstr);
    263 	else
    264 		aprint_normal("unknown chip id %d, ", sc->sc_chipid);
    265 	aprint_normal("revision %d, ", RR_REV(tmp));
    266 
    267 	SMC_SELECT_BANK(sc, 0);
    268 	switch (sc->sc_chipid) {
    269 	default:
    270 		mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W));
    271 		scale = MIR_SCALE_91C9x;
    272 		break;
    273 
    274 	case CHIP_91C111:
    275 		mult = MIR_MULT_91C111;
    276 		scale = MIR_SCALE_91C111;
    277 	}
    278 	memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK;
    279 	if (memsize == 255)
    280 		memsize++;
    281 	memsize *= scale * mult;
    282 
    283 	format_bytes(pbuf, sizeof(pbuf), memsize);
    284 	aprint_normal("buffer size: %s\n", pbuf);
    285 
    286 	/* Read the station address from the chip. */
    287 	SMC_SELECT_BANK(sc, 1);
    288 	if (myea == NULL) {
    289 		myea = enaddr;
    290 		for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
    291 			tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i);
    292 			myea[i + 1] = (tmp >> 8) & 0xff;
    293 			myea[i] = tmp & 0xff;
    294 		}
    295 	}
    296 	aprint_normal_dev(sc->sc_dev, "MAC address %s, ",
    297 	    ether_sprintf(myea));
    298 
    299 	/* Initialize the ifnet structure. */
    300 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
    301 	ifp->if_softc = sc;
    302 	ifp->if_start = smc91cxx_start;
    303 	ifp->if_ioctl = smc91cxx_ioctl;
    304 	ifp->if_watchdog = smc91cxx_watchdog;
    305 	ifp->if_flags =
    306 	    IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
    307 	IFQ_SET_READY(&ifp->if_snd);
    308 
    309 	/* Attach the interface. */
    310 	if_attach(ifp);
    311 	ether_ifattach(ifp, myea);
    312 
    313 	/*
    314 	 * Initialize our media structures and MII info.  We will
    315 	 * probe the MII if we are on the SMC91Cxx
    316 	 */
    317 	sc->sc_mii.mii_ifp = ifp;
    318 	sc->sc_mii.mii_readreg = smc91cxx_mii_readreg;
    319 	sc->sc_mii.mii_writereg = smc91cxx_mii_writereg;
    320 	sc->sc_mii.mii_statchg = smc91cxx_statchg;
    321 	ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus);
    322 
    323 	SMC_SELECT_BANK(sc, 1);
    324 	tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
    325 
    326 	miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG;
    327 	switch (sc->sc_chipid) {
    328 	case CHIP_91100:
    329 		/*
    330 		 * The 91100 does not have full-duplex capabilities,
    331 		 * even if the PHY does.
    332 		 */
    333 		miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX);
    334 		/*FALLTHROUGH*/
    335 	case CHIP_91100FD:
    336 	case CHIP_91C111:
    337 		if (tmp & CR_MII_SELECT) {
    338 			aprint_normal("default media MII");
    339 			if (sc->sc_chipid == CHIP_91C111) {
    340 				aprint_normal(" (%s PHY)\n",
    341 				    (tmp & CR_AUI_SELECT) ?
    342 				    "external" : "internal");
    343 				sc->sc_internal_phy = !(tmp & CR_AUI_SELECT);
    344 			} else
    345 				aprint_normal("\n");
    346 			mii_attach(sc->sc_dev, &sc->sc_mii, miicapabilities,
    347 			    MII_PHY_ANY, MII_OFFSET_ANY, 0);
    348 			if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
    349 				ifmedia_add(&sc->sc_mii.mii_media,
    350 				    IFM_ETHER|IFM_NONE, 0, NULL);
    351 				ifmedia_set(&sc->sc_mii.mii_media,
    352 				    IFM_ETHER|IFM_NONE);
    353 			} else {
    354 				ifmedia_set(&sc->sc_mii.mii_media,
    355 				    IFM_ETHER|IFM_AUTO);
    356 			}
    357 			sc->sc_flags |= SMC_FLAGS_HAS_MII;
    358 			break;
    359 		} else
    360 		if (sc->sc_chipid == CHIP_91C111) {
    361 			/*
    362 			 * XXX: Should bring it out of low-power mode
    363 			 */
    364 			aprint_normal("EPH interface in low power mode\n");
    365 			sc->sc_internal_phy = 0;
    366 			return;
    367 		}
    368 		/*FALLTHROUGH*/
    369 	default:
    370 		aprint_normal("default media %s\n",
    371 		    (aui = (tmp & CR_AUI_SELECT)) ?
    372 		    "AUI" : "UTP");
    373 		for (i = 0; i < NSMC91CxxMEDIA; i++)
    374 			ifmedia_add(ifm, smc91cxx_media[i], 0, NULL);
    375 		ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T));
    376 		break;
    377 	}
    378 
    379 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
    380 			  RND_TYPE_NET, RND_FLAG_DEFAULT);
    381 
    382 	callout_init(&sc->sc_mii_callout, 0);
    383 
    384 	/* The attach is successful. */
    385 	sc->sc_flags |= SMC_FLAGS_ATTACHED;
    386 }
    387 
    388 /*
    389  * Change media according to request.
    390  */
    391 int
    392 smc91cxx_mediachange(struct ifnet *ifp)
    393 {
    394 	struct smc91cxx_softc *sc = ifp->if_softc;
    395 
    396 	return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media));
    397 }
    398 
    399 int
    400 smc91cxx_set_media(struct smc91cxx_softc *sc, int media)
    401 {
    402 	bus_space_tag_t bst = sc->sc_bst;
    403 	bus_space_handle_t bsh = sc->sc_bsh;
    404 	u_int16_t tmp;
    405 	int rc;
    406 
    407 	/*
    408 	 * If the interface is not currently powered on, just return.
    409 	 * When it is enabled later, smc91cxx_init() will properly set
    410 	 * up the media for us.
    411 	 */
    412 	if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0)
    413 		return (0);
    414 
    415 	if (IFM_TYPE(media) != IFM_ETHER)
    416 		return (EINVAL);
    417 
    418 	if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 ||
    419 	    (rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
    420 		rc = 0;
    421 
    422 	switch (IFM_SUBTYPE(media)) {
    423 	case IFM_10_T:
    424 	case IFM_10_5:
    425 		SMC_SELECT_BANK(sc, 1);
    426 		tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
    427 		if (IFM_SUBTYPE(media) == IFM_10_5)
    428 			tmp |= CR_AUI_SELECT;
    429 		else
    430 			tmp &= ~CR_AUI_SELECT;
    431 		bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp);
    432 		delay(20000);	/* XXX is this needed? */
    433 		break;
    434 
    435 	default:
    436 		return (EINVAL);
    437 	}
    438 
    439 	return rc;
    440 }
    441 
    442 /*
    443  * Notify the world which media we're using.
    444  */
    445 void
    446 smc91cxx_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
    447 {
    448 	struct smc91cxx_softc *sc = ifp->if_softc;
    449 	bus_space_tag_t bst = sc->sc_bst;
    450 	bus_space_handle_t bsh = sc->sc_bsh;
    451 	u_int16_t tmp;
    452 
    453 	if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) {
    454 		ifmr->ifm_active = IFM_ETHER | IFM_NONE;
    455 		ifmr->ifm_status = 0;
    456 		return;
    457 	}
    458 
    459 	/*
    460 	 * If we have MII, go ask the PHY what's going on.
    461 	 */
    462 	if (sc->sc_flags & SMC_FLAGS_HAS_MII) {
    463 		mii_pollstat(&sc->sc_mii);
    464 		ifmr->ifm_active = sc->sc_mii.mii_media_active;
    465 		ifmr->ifm_status = sc->sc_mii.mii_media_status;
    466 		return;
    467 	}
    468 
    469 	SMC_SELECT_BANK(sc, 1);
    470 	tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
    471 	ifmr->ifm_active =
    472 	    IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T);
    473 }
    474 
    475 /*
    476  * Reset and initialize the chip.
    477  */
    478 void
    479 smc91cxx_init(struct smc91cxx_softc *sc)
    480 {
    481 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    482 	bus_space_tag_t bst = sc->sc_bst;
    483 	bus_space_handle_t bsh = sc->sc_bsh;
    484 	u_int16_t tmp;
    485 	const u_int8_t *enaddr;
    486 	int s, i;
    487 
    488 	s = splnet();
    489 
    490 	/*
    491 	 * This resets the registers mostly to defaults, but doesn't
    492 	 * affect the EEPROM.  The longest reset recovery time of those devices
    493 	 * supported is the 91C111. Section 7.8 of its datasheet asks for 50ms.
    494 	 */
    495 	SMC_SELECT_BANK(sc, 0);
    496 	bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET);
    497 	delay(5);
    498 	bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0);
    499 	delay(50000);
    500 
    501 	bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0);
    502 
    503 	/* Set the Ethernet address. */
    504 	SMC_SELECT_BANK(sc, 1);
    505 	enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl);
    506 	for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
    507 		tmp = enaddr[i + 1] << 8 | enaddr[i];
    508 		bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp);
    509 	}
    510 
    511 	/*
    512 	 * Set the control register to automatically release successfully
    513 	 * transmitted packets (making the best use of our limited memory)
    514 	 * and enable the EPH interrupt on certain TX errors.
    515 	 */
    516 	bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE |
    517 	    CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE));
    518 
    519 	/*
    520 	 * Reset the MMU and wait for it to be un-busy.
    521 	 */
    522 	SMC_SELECT_BANK(sc, 2);
    523 	bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET);
    524 	sc->sc_txpacketno = ARR_FAILED;
    525 	for (;;) {
    526 		tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W);
    527 		if (tmp == 0xffff)	/* card went away! */
    528 			return;
    529 		if ((tmp & MMUCR_BUSY) == 0)
    530 			break;
    531 	}
    532 
    533 	/*
    534 	 * Disable all interrupts.
    535 	 */
    536 	smc91cxx_intr_mask_write(bst, bsh, 0);
    537 
    538 	/*
    539 	 * On the 91c111, enable auto-negotiation, and set the LED
    540 	 * status pins to something sane.
    541 	 * XXX: Should be some way for MD code to decide the latter.
    542 	 */
    543 	SMC_SELECT_BANK(sc, 0);
    544 	if (sc->sc_chipid == CHIP_91C111) {
    545 		bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W,
    546 		    RPC_ANEG |
    547 		    (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) |
    548 		    (RPC_LS_TXRX << RPC_LSB_SHIFT));
    549 	}
    550 
    551 	/*
    552 	 * Set current media.
    553 	 */
    554 	smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media);
    555 
    556 	/*
    557 	 * Set the receive filter.  We want receive enable and auto
    558 	 * strip of CRC from received packet.  If we are in promisc. mode,
    559 	 * then set that bit as well.
    560 	 *
    561 	 * XXX Initialize multicast filter.  For now, we just accept
    562 	 * XXX all multicast.
    563 	 */
    564 	SMC_SELECT_BANK(sc, 0);
    565 
    566 	tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL;
    567 	if (ifp->if_flags & IFF_PROMISC)
    568 		tmp |= RCR_PROMISC;
    569 
    570 	bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp);
    571 
    572 	/*
    573 	 * Set transmitter control to "enabled".
    574 	 */
    575 	tmp = TCR_ENABLE;
    576 
    577 #ifndef SMC91CXX_SW_PAD
    578 	/*
    579 	 * Enable hardware padding of transmitted packets.
    580 	 * XXX doesn't work?
    581 	 */
    582 	tmp |= TCR_PAD_ENABLE;
    583 #endif
    584 
    585 	bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp);
    586 
    587 	/*
    588 	 * Now, enable interrupts.
    589 	 */
    590 	SMC_SELECT_BANK(sc, 2);
    591 
    592 	sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT;
    593 	if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) {
    594 		sc->sc_intmask |= IM_MD_INT;
    595 	}
    596 	smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask);
    597 
    598 	/* Interface is now running, with no output active. */
    599 	ifp->if_flags |= IFF_RUNNING;
    600 	ifp->if_flags &= ~IFF_OACTIVE;
    601 
    602 	if (sc->sc_flags & SMC_FLAGS_HAS_MII) {
    603 		/* Start the one second clock. */
    604 		callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc);
    605 	}
    606 
    607 	/*
    608 	 * Attempt to start any pending transmission.
    609 	 */
    610 	smc91cxx_start(ifp);
    611 
    612 	splx(s);
    613 }
    614 
    615 /*
    616  * Start output on an interface.
    617  * Must be called at splnet or interrupt level.
    618  */
    619 void
    620 smc91cxx_start(struct ifnet *ifp)
    621 {
    622 	struct smc91cxx_softc *sc = ifp->if_softc;
    623 	bus_space_tag_t bst = sc->sc_bst;
    624 	bus_space_handle_t bsh = sc->sc_bsh;
    625 	u_int len;
    626 	struct mbuf *m;
    627 	u_int16_t length, npages;
    628 	u_int16_t oddbyte;
    629 	u_int8_t packetno;
    630 	int timo, pad;
    631 
    632 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
    633 		return;
    634 
    635  again:
    636 	/*
    637 	 * Peek at the next packet.
    638 	 */
    639 	IFQ_POLL(&ifp->if_snd, m);
    640 	if (m == NULL)
    641 		return;
    642 
    643 	/*
    644 	 * Compute the frame length and set pad to give an overall even
    645 	 * number of bytes.  Below, we assume that the packet length
    646 	 * is even.
    647 	 */
    648 	for (len = 0; m != NULL; m = m->m_next)
    649 		len += m->m_len;
    650 
    651 	/*
    652 	 * We drop packets that are too large.  Perhaps we should
    653 	 * truncate them instead?
    654 	 */
    655 	if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN)) {
    656 		printf("%s: large packet discarded\n",
    657 		    device_xname(sc->sc_dev));
    658 		ifp->if_oerrors++;
    659 		IFQ_DEQUEUE(&ifp->if_snd, m);
    660 		m_freem(m);
    661 		goto readcheck;
    662 	}
    663 
    664 	pad = 0;
    665 #ifdef SMC91CXX_SW_PAD
    666 	/*
    667 	 * Not using hardware padding; pad to ETHER_MIN_LEN.
    668 	 */
    669 	if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN))
    670 		pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
    671 #endif
    672 
    673 	length = pad + len;
    674 
    675 	/*
    676 	 * The MMU has a 256 byte page size.  The MMU expects us to
    677 	 * ask for "npages - 1".  We include space for the status word,
    678 	 * byte count, and control bytes in the allocation request.
    679 	 */
    680 	npages = ((length & ~1) + 6) >> 8;
    681 
    682 	/*
    683 	 * Now allocate the memory.
    684 	 */
    685 	SMC_SELECT_BANK(sc, 2);
    686 	bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages);
    687 
    688 	timo = MEMORY_WAIT_TIME;
    689 	if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) {
    690 		packetno = sc->sc_txpacketno;
    691 		sc->sc_txpacketno = ARR_FAILED;
    692 	} else {
    693 		do {
    694 			if (bus_space_read_1(bst, bsh,
    695 			    		     INTR_STAT_REG_B) & IM_ALLOC_INT)
    696 				break;
    697 			delay(1);
    698 		} while (--timo);
    699 	}
    700 
    701 	packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B);
    702 
    703 	if (packetno & ARR_FAILED || timo == 0) {
    704 		/*
    705 		 * No transmit memory is available.  Record the number
    706 		 * of requested pages and enable the allocation completion
    707 		 * interrupt.  Set up the watchdog timer in case we miss
    708 		 * the interrupt.  Mark the interface as active so that
    709 		 * no one else attempts to transmit while we're allocating
    710 		 * memory.
    711 		 */
    712 		sc->sc_intmask |= IM_ALLOC_INT;
    713 		smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask);
    714 		ifp->if_timer = 5;
    715 		ifp->if_flags |= IFF_OACTIVE;
    716 
    717 		return;
    718 	}
    719 
    720 	/*
    721 	 * We have a packet number - set the data window.
    722 	 */
    723 	bus_space_write_2(bst, bsh, PACKET_NUM_REG_B, packetno);
    724 
    725 	/*
    726 	 * Point to the beginning of the packet.
    727 	 */
    728 	bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */);
    729 
    730 	/*
    731 	 * Send the packet length (+6 for stats, length, and control bytes)
    732 	 * and the status word (set to zeros).
    733 	 */
    734 	bus_space_write_2(bst, bsh, DATA_REG_W, 0);
    735 	bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff);
    736 
    737 	/*
    738 	 * Get the packet from the kernel.  This will include the Ethernet
    739 	 * frame header, MAC address, etc.
    740 	 */
    741 	IFQ_DEQUEUE(&ifp->if_snd, m);
    742 
    743 	/*
    744 	 * Push the packet out to the card.  The copying function only does
    745 	 * whole words and returns the straggling byte (if any).
    746 	 */
    747 	oddbyte = smc91cxx_copy_tx_frame(sc, m);
    748 
    749 #ifdef SMC91CXX_SW_PAD
    750 	if (pad > 1 && (pad & 1)) {
    751 		bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte);
    752 		oddbyte = 0;
    753 		pad -= 1;
    754 	}
    755 
    756 	/*
    757 	 * Push out padding.
    758 	 */
    759 	while (pad > 1) {
    760 		bus_space_write_2(bst, bsh, DATA_REG_W, 0);
    761 		pad -= 2;
    762 	}
    763 #endif
    764 
    765 	/*
    766 	 * Push out control byte and unused packet byte.  The control byte
    767 	 * denotes whether this is an odd or even length packet, and that
    768 	 * no special CRC handling is necessary.
    769 	 */
    770 	bus_space_write_2(bst, bsh, DATA_REG_W,
    771 	    oddbyte | ((length & 1) ? (CTLB_ODD << 8) : 0));
    772 
    773 	/*
    774 	 * Enable transmit interrupts and let the chip go.  Set a watchdog
    775 	 * in case we miss the interrupt.
    776 	 */
    777 	sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT;
    778 	smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask);
    779 
    780 	bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE);
    781 
    782 	ifp->if_timer = 5;
    783 
    784 	/* Hand off a copy to the bpf. */
    785 	bpf_mtap(ifp, m);
    786 
    787 	ifp->if_opackets++;
    788 	m_freem(m);
    789 
    790  readcheck:
    791 	/*
    792 	 * Check for incoming packets.  We don't want to overflow the small
    793 	 * RX FIFO.  If nothing has arrived, attempt to queue another
    794 	 * transmit packet.
    795 	 */
    796 	if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY)
    797 		goto again;
    798 }
    799 
    800 /*
    801  * Squirt a (possibly misaligned) mbuf to the device
    802  */
    803 uint8_t
    804 smc91cxx_copy_tx_frame(struct smc91cxx_softc *sc, struct mbuf *m0)
    805 {
    806 	bus_space_tag_t bst = sc->sc_bst;
    807 	bus_space_handle_t bsh = sc->sc_bsh;
    808 	struct mbuf *m;
    809 	int len, leftover;
    810 	u_int16_t dbuf;
    811 	u_int8_t *p;
    812 #ifdef DIAGNOSTIC
    813 	u_int8_t *lim;
    814 #endif
    815 
    816 	/* start out with no leftover data */
    817 	leftover = 0;
    818 	dbuf = 0;
    819 
    820 	/* Process the chain of mbufs */
    821 	for (m = m0; m != NULL; m = m->m_next) {
    822 		/*
    823 		 * Process all of the data in a single mbuf.
    824 		 */
    825 		p = mtod(m, u_int8_t *);
    826 		len = m->m_len;
    827 #ifdef DIAGNOSTIC
    828 		lim = p + len;
    829 #endif
    830 
    831 		while (len > 0) {
    832 			if (leftover) {
    833 				/*
    834 				 * Data left over (from mbuf or realignment).
    835 				 * Buffer the next byte, and write it and
    836 				 * the leftover data out.
    837 				 */
    838 				dbuf |= *p++ << 8;
    839 				len--;
    840 				bus_space_write_2(bst, bsh, DATA_REG_W, dbuf);
    841 				leftover = 0;
    842 			} else if ((long) p & 1) {
    843 				/*
    844 				 * Misaligned data.  Buffer the next byte.
    845 				 */
    846 				dbuf = *p++;
    847 				len--;
    848 				leftover = 1;
    849 			} else {
    850 				/*
    851 				 * Aligned data.  This is the case we like.
    852 				 *
    853 				 * Write-region out as much as we can, then
    854 				 * buffer the remaining byte (if any).
    855 				 */
    856 				leftover = len & 1;
    857 				len &= ~1;
    858 				bus_space_write_multi_stream_2(bst, bsh,
    859 				    DATA_REG_W, (u_int16_t *)p, len >> 1);
    860 				p += len;
    861 
    862 				if (leftover)
    863 					dbuf = *p++;
    864 				len = 0;
    865 			}
    866 		}
    867 		if (len < 0)
    868 			panic("smc91cxx_copy_tx_frame: negative len");
    869 #ifdef DIAGNOSTIC
    870 		if (p != lim)
    871 			panic("smc91cxx_copy_tx_frame: p != lim");
    872 #endif
    873 	}
    874 
    875 	return dbuf;
    876 }
    877 
    878 /*
    879  * Interrupt service routine.
    880  */
    881 int
    882 smc91cxx_intr(void *arg)
    883 {
    884 	struct smc91cxx_softc *sc = arg;
    885 	struct ifnet *ifp = &sc->sc_ec.ec_if;
    886 	bus_space_tag_t bst = sc->sc_bst;
    887 	bus_space_handle_t bsh = sc->sc_bsh;
    888 	u_int8_t mask, interrupts, status;
    889 	u_int16_t packetno, tx_status, card_stats;
    890 	u_int16_t v;
    891 
    892 	if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 ||
    893 	    !device_is_active(sc->sc_dev))
    894 		return (0);
    895 
    896 	SMC_SELECT_BANK(sc, 2);
    897 
    898 	/*
    899 	 * Obtain the current interrupt status and mask.
    900 	 */
    901 	v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B);
    902 
    903 	/*
    904 	 * Get the set of interrupt which occurred and eliminate any
    905 	 * which are not enabled.
    906 	 */
    907 	mask = v >> 8;
    908 	interrupts = v & 0xff;
    909 	KDASSERT(mask == sc->sc_intmask);
    910 	status = interrupts & mask;
    911 
    912 	/* Ours? */
    913 	if (status == 0)
    914 		return (0);
    915 
    916 	/*
    917 	 * It's ours; disable all interrupts while we process them.
    918 	 */
    919 	smc91cxx_intr_mask_write(bst, bsh, 0);
    920 
    921 	/*
    922 	 * Receive overrun interrupts.
    923 	 */
    924 	if (status & IM_RX_OVRN_INT) {
    925 		smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT, 0);
    926 		ifp->if_ierrors++;
    927 	}
    928 
    929 	/*
    930 	 * Receive interrupts.
    931 	 */
    932 	if (status & IM_RCV_INT) {
    933 		smc91cxx_read(sc);
    934 	}
    935 
    936 	/*
    937 	 * Memory allocation interrupts.
    938 	 */
    939 	if (status & IM_ALLOC_INT) {
    940 		/* Disable this interrupt. */
    941 		mask &= ~IM_ALLOC_INT;
    942 		sc->sc_intmask &= ~IM_ALLOC_INT;
    943 
    944 		/*
    945 		 * Save allocated packet number for use in start
    946 		 */
    947 		packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B);
    948 		KASSERT(sc->sc_txpacketno & ARR_FAILED);
    949 		sc->sc_txpacketno = packetno;
    950 
    951 		/*
    952 		 * We can transmit again!
    953 		 */
    954 		ifp->if_flags &= ~IFF_OACTIVE;
    955 		ifp->if_timer = 0;
    956 	}
    957 
    958 	/*
    959 	 * Transmit complete interrupt.  Handle transmission error messages.
    960 	 * This will only be called on error condition because of AUTO RELEASE
    961 	 * mode.
    962 	 */
    963 	if (status & IM_TX_INT) {
    964 		smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT, 0);
    965 
    966 		packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) &
    967 		    FIFO_TX_MASK;
    968 
    969 		/*
    970 		 * Select this as the packet to read from.
    971 		 */
    972 		bus_space_write_2(bst, bsh, PACKET_NUM_REG_B, packetno);
    973 
    974 		/*
    975 		 * Position the pointer to the beginning of the packet, wait
    976 		 * for preload.
    977 		 */
    978 		bus_space_write_2(bst, bsh, POINTER_REG_W,
    979 		    PTR_AUTOINC | PTR_READ /* | 0x0000 */);
    980 		delay(1);
    981 
    982 		/*
    983 		 * Fetch the TX status word.  This will be a copy of
    984 		 * the EPH_STATUS_REG_W at the time of the transmission
    985 		 * failure.
    986 		 */
    987 		tx_status = bus_space_read_2(bst, bsh, DATA_REG_W);
    988 
    989 		if (tx_status & EPHSR_TX_SUC) {
    990 			static struct timeval txsuc_last;
    991 			static int txsuc_count;
    992 			if (ppsratecheck(&txsuc_last, &txsuc_count, 1))
    993 				printf("%s: successful packet caused TX"
    994 				    " interrupt?!\n", device_xname(sc->sc_dev));
    995 		} else
    996 			ifp->if_oerrors++;
    997 
    998 		if (tx_status & EPHSR_LATCOL)
    999 			ifp->if_collisions++;
   1000 
   1001 		/* Disable this interrupt (start will reenable if needed). */
   1002 		mask &= ~IM_TX_INT;
   1003 		sc->sc_intmask &= ~IM_TX_INT;
   1004 
   1005 		/*
   1006 		 * Some of these errors disable the transmitter; reenable it.
   1007 		 */
   1008 		SMC_SELECT_BANK(sc, 0);
   1009 #ifdef SMC91CXX_SW_PAD
   1010 		bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE);
   1011 #else
   1012 		bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W,
   1013 		    TCR_ENABLE | TCR_PAD_ENABLE);
   1014 #endif
   1015 
   1016 		/*
   1017 		 * Kill the failed packet and wait for the MMU to unbusy.
   1018 		 */
   1019 		SMC_SELECT_BANK(sc, 2);
   1020 		while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
   1021 			/* XXX bound this loop! */ ;
   1022 		bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT);
   1023 
   1024 		ifp->if_timer = 0;
   1025 	}
   1026 
   1027 	/*
   1028 	 * Transmit underrun interrupts.  We use this opportunity to
   1029 	 * update transmit statistics from the card.
   1030 	 */
   1031 	if (status & IM_TX_EMPTY_INT) {
   1032 		smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT, 0);
   1033 
   1034 		/* Disable this interrupt. */
   1035 		mask &= ~IM_TX_EMPTY_INT;
   1036 		sc->sc_intmask &= ~IM_TX_EMPTY_INT;
   1037 
   1038 		SMC_SELECT_BANK(sc, 0);
   1039 		card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W);
   1040 
   1041 		/* Single collisions. */
   1042 		ifp->if_collisions += card_stats & ECR_COLN_MASK;
   1043 
   1044 		/* Multiple collisions. */
   1045 		ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
   1046 
   1047 		SMC_SELECT_BANK(sc, 2);
   1048 
   1049 		ifp->if_timer = 0;
   1050 	}
   1051 
   1052 	/*
   1053 	 * Internal PHY status change
   1054 	 */
   1055 	if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy &&
   1056 	    (status & IM_MD_INT)) {
   1057 
   1058 		/*
   1059 		 * Internal PHY status change
   1060 		 */
   1061 		smc91cxx_intr_ack_write(bst, bsh, IM_MD_INT, 0);
   1062 		mii_pollstat(&sc->sc_mii);
   1063 	}
   1064 
   1065 	/*
   1066 	 * Other errors.  Reset the interface.
   1067 	 */
   1068 	if (status & IM_EPH_INT) {
   1069 		smc91cxx_stop(sc);
   1070 		smc91cxx_init(sc);
   1071 	}
   1072 
   1073 	/*
   1074 	 * Attempt to queue more packets for transmission.
   1075 	 */
   1076 	smc91cxx_start(ifp);
   1077 
   1078 	/*
   1079 	 * Reenable the interrupts we wish to receive now that processing
   1080 	 * is complete.
   1081 	 */
   1082 	mask |= sc->sc_intmask;
   1083 	smc91cxx_intr_mask_write(bst, bsh, mask);
   1084 
   1085 	if (status)
   1086 		rnd_add_uint32(&sc->rnd_source, status);
   1087 
   1088 	return (1);
   1089 }
   1090 
   1091 /*
   1092  * Read a packet from the card and pass it up to the kernel.
   1093  * NOTE!  WE EXPECT TO BE IN REGISTER WINDOW 2!
   1094  */
   1095 void
   1096 smc91cxx_read(struct smc91cxx_softc *sc)
   1097 {
   1098 	struct ifnet *ifp = &sc->sc_ec.ec_if;
   1099 	bus_space_tag_t bst = sc->sc_bst;
   1100 	bus_space_handle_t bsh = sc->sc_bsh;
   1101 	struct ether_header *eh;
   1102 	struct mbuf *m;
   1103 	u_int16_t status, packetno, packetlen;
   1104 	u_int8_t *data;
   1105 	u_int32_t dr;
   1106 	bool first = true;
   1107 
   1108  again:
   1109 	/*
   1110 	 * Set data pointer to the beginning of the packet.  Since
   1111 	 * PTR_RCV is set, the packet number will be found automatically
   1112 	 * in FIFO_PORTS_REG_W, FIFO_RX_MASK.
   1113 	 */
   1114 	packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
   1115 	if (packetno & FIFO_REMPTY) {
   1116 		if (first) {
   1117 			aprint_error_dev(sc->sc_dev,
   1118 			    "receive interrupt on empty fifo\n");
   1119 		}
   1120 		return;
   1121 	}
   1122 	first = false;
   1123 
   1124 	bus_space_write_2(bst, bsh, POINTER_REG_W,
   1125 	    PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */);
   1126 	delay(1);
   1127 
   1128 	/*
   1129 	 * First two words are status and packet length.
   1130 	 */
   1131 	dr = bus_space_read_4(bst, bsh, DATA_REG_W);
   1132 	status = (u_int16_t)dr;
   1133 	packetlen = (u_int16_t)(dr >> 16);
   1134 
   1135 	packetlen &= RLEN_MASK;
   1136 	if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) {
   1137 		ifp->if_ierrors++;
   1138 		goto out;
   1139 	}
   1140 
   1141 	/*
   1142 	 * The packet length includes 3 extra words: status, length,
   1143 	 * and an extra word that includes the control byte.
   1144 	 */
   1145 	packetlen -= 6;
   1146 
   1147 	/*
   1148 	 * Account for receive errors and discard.
   1149 	 */
   1150 	if (status & RS_ERRORS) {
   1151 		ifp->if_ierrors++;
   1152 		goto out;
   1153 	}
   1154 
   1155 	/*
   1156 	 * Adjust for odd-length packet.
   1157 	 */
   1158 	if (status & RS_ODDFRAME)
   1159 		packetlen++;
   1160 
   1161 	/*
   1162 	 * Allocate a header mbuf.
   1163 	 */
   1164 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   1165 	if (m == NULL)
   1166 		goto out;
   1167 	m->m_pkthdr.rcvif = ifp;
   1168 	m->m_pkthdr.len = packetlen;
   1169 
   1170 	/*
   1171 	 * Always put the packet in a cluster.
   1172 	 * XXX should chain small mbufs if less than threshold.
   1173 	 */
   1174 	MCLGET(m, M_DONTWAIT);
   1175 	if ((m->m_flags & M_EXT) == 0) {
   1176 		m_freem(m);
   1177 		ifp->if_ierrors++;
   1178 		aprint_error_dev(sc->sc_dev,
   1179 		     "can't allocate cluster for incoming packet\n");
   1180 		goto out;
   1181 	}
   1182 
   1183 	/*
   1184 	 * Pull the packet off the interface.  Make sure the payload
   1185 	 * is aligned.
   1186 	 */
   1187 	if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) {
   1188 		m->m_data = (char *) ALIGN(mtod(m, char *) +
   1189 		    sizeof(struct ether_header)) - sizeof(struct ether_header);
   1190 
   1191 		eh = mtod(m, struct ether_header *);
   1192 		data = mtod(m, u_int8_t *);
   1193 		KASSERT(trunc_page((uintptr_t)data) ==
   1194 			trunc_page((uintptr_t)data + packetlen - 1));
   1195 		if (packetlen > 1)
   1196 			bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W,
   1197 			    (u_int16_t *)data, packetlen >> 1);
   1198 		if (packetlen & 1) {
   1199 			data += packetlen & ~1;
   1200 			*data = bus_space_read_1(bst, bsh, DATA_REG_B);
   1201 		}
   1202 	} else {
   1203 		m->m_data = (void *) ALIGN(mtod(m, void *));
   1204 		eh = mtod(m, struct ether_header *);
   1205 		data = mtod(m, u_int8_t *);
   1206 		KASSERT(trunc_page((uintptr_t)data) ==
   1207 			trunc_page((uintptr_t)data + packetlen - 1));
   1208 		if (packetlen > 3)
   1209 			bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W,
   1210 			    (u_int32_t *)data, packetlen >> 2);
   1211 		if (packetlen & 3) {
   1212 			data += packetlen & ~3;
   1213 			*((u_int32_t *)data) =
   1214 			    bus_space_read_stream_4(bst, bsh, DATA_REG_W);
   1215 		}
   1216 	}
   1217 
   1218 	ifp->if_ipackets++;
   1219 
   1220 	/*
   1221 	 * Make sure to behave as IFF_SIMPLEX in all cases.
   1222 	 * This is to cope with SMC91C92 (Megahertz XJ10BT), which
   1223 	 * loops back packets to itself on promiscuous mode.
   1224 	 * (should be ensured by chipset configuration)
   1225 	 */
   1226 	if ((ifp->if_flags & IFF_PROMISC) != 0) {
   1227 		/*
   1228 		 * Drop packet looped back from myself.
   1229 		 */
   1230 		if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) {
   1231 			m_freem(m);
   1232 			goto out;
   1233 		}
   1234 	}
   1235 
   1236 	m->m_pkthdr.len = m->m_len = packetlen;
   1237 
   1238 	/*
   1239 	 * Hand the packet off to bpf listeners.
   1240 	 */
   1241 	bpf_mtap(ifp, m);
   1242 
   1243 	(*ifp->if_input)(ifp, m);
   1244 
   1245  out:
   1246 	/*
   1247 	 * Tell the card to free the memory occupied by this packet.
   1248 	 */
   1249 	while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
   1250 		/* XXX bound this loop! */ ;
   1251 	bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE);
   1252 
   1253 	/*
   1254 	 * Check for another packet.
   1255 	 */
   1256 	goto again;
   1257 }
   1258 
   1259 /*
   1260  * Process an ioctl request.
   1261  */
   1262 int
   1263 smc91cxx_ioctl(struct ifnet *ifp, u_long cmd, void *data)
   1264 {
   1265 	struct smc91cxx_softc *sc = ifp->if_softc;
   1266 	struct ifaddr *ifa = (struct ifaddr *)data;
   1267 	struct ifreq *ifr = (struct ifreq *)data;
   1268 	int s, error = 0;
   1269 
   1270 	s = splnet();
   1271 
   1272 	switch (cmd) {
   1273 	case SIOCINITIFADDR:
   1274 		if ((error = smc91cxx_enable(sc)) != 0)
   1275 			break;
   1276 		ifp->if_flags |= IFF_UP;
   1277 		smc91cxx_init(sc);
   1278 		switch (ifa->ifa_addr->sa_family) {
   1279 #ifdef INET
   1280 		case AF_INET:
   1281 			arp_ifinit(ifp, ifa);
   1282 			break;
   1283 #endif
   1284 		default:
   1285 			break;
   1286 		}
   1287 		break;
   1288 
   1289 
   1290 	case SIOCSIFFLAGS:
   1291 		if ((error = ifioctl_common(ifp, cmd, data)) != 0)
   1292 			break;
   1293 		/* XXX re-use ether_ioctl() */
   1294 		switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
   1295 		case IFF_RUNNING:
   1296 			/*
   1297 			 * If interface is marked down and it is running,
   1298 			 * stop it.
   1299 			 */
   1300 			smc91cxx_stop(sc);
   1301 			ifp->if_flags &= ~IFF_RUNNING;
   1302 			smc91cxx_disable(sc);
   1303 			break;
   1304 		case IFF_UP:
   1305 			/*
   1306 			 * If interface is marked up and it is stopped,
   1307 			 * start it.
   1308 			 */
   1309 			if ((error = smc91cxx_enable(sc)) != 0)
   1310 				break;
   1311 			smc91cxx_init(sc);
   1312 			break;
   1313 		case IFF_UP|IFF_RUNNING:
   1314 			/*
   1315 			 * Reset the interface to pick up changes in any
   1316 			 * other flags that affect hardware registers.
   1317 			 */
   1318 			smc91cxx_reset(sc);
   1319 			break;
   1320 		case 0:
   1321 			break;
   1322 		}
   1323 		break;
   1324 
   1325 	case SIOCADDMULTI:
   1326 	case SIOCDELMULTI:
   1327 		if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) {
   1328 			error = EIO;
   1329 			break;
   1330 		}
   1331 
   1332 		if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
   1333 			/*
   1334 			 * Multicast list has changed; set the hardware
   1335 			 * filter accordingly.
   1336 			 */
   1337 			if (ifp->if_flags & IFF_RUNNING)
   1338 				smc91cxx_reset(sc);
   1339 			error = 0;
   1340 		}
   1341 		break;
   1342 
   1343 	case SIOCGIFMEDIA:
   1344 	case SIOCSIFMEDIA:
   1345 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
   1346 		break;
   1347 
   1348 	default:
   1349 		error = ether_ioctl(ifp, cmd, data);
   1350 		break;
   1351 	}
   1352 
   1353 	splx(s);
   1354 	return (error);
   1355 }
   1356 
   1357 /*
   1358  * Reset the interface.
   1359  */
   1360 void
   1361 smc91cxx_reset(struct smc91cxx_softc *sc)
   1362 {
   1363 	int s;
   1364 
   1365 	s = splnet();
   1366 	smc91cxx_stop(sc);
   1367 	smc91cxx_init(sc);
   1368 	splx(s);
   1369 }
   1370 
   1371 /*
   1372  * Watchdog timer.
   1373  */
   1374 void
   1375 smc91cxx_watchdog(struct ifnet *ifp)
   1376 {
   1377 	struct smc91cxx_softc *sc = ifp->if_softc;
   1378 
   1379 	log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev));
   1380 	ifp->if_oerrors++;
   1381 	smc91cxx_reset(sc);
   1382 }
   1383 
   1384 /*
   1385  * Stop output on the interface.
   1386  */
   1387 void
   1388 smc91cxx_stop(struct smc91cxx_softc *sc)
   1389 {
   1390 	bus_space_tag_t bst = sc->sc_bst;
   1391 	bus_space_handle_t bsh = sc->sc_bsh;
   1392 
   1393 	/*
   1394 	 * Clear interrupt mask; disable all interrupts.
   1395 	 */
   1396 	SMC_SELECT_BANK(sc, 2);
   1397 	smc91cxx_intr_mask_write(bst, bsh, 0);
   1398 
   1399 	/*
   1400 	 * Disable transmitter and receiver.
   1401 	 */
   1402 	SMC_SELECT_BANK(sc, 0);
   1403 	bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0);
   1404 	bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0);
   1405 
   1406 	/*
   1407 	 * Cancel watchdog timer.
   1408 	 */
   1409 	sc->sc_ec.ec_if.if_timer = 0;
   1410 }
   1411 
   1412 /*
   1413  * Enable power on the interface.
   1414  */
   1415 int
   1416 smc91cxx_enable(struct smc91cxx_softc *sc)
   1417 {
   1418 
   1419 	if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) {
   1420 		if ((*sc->sc_enable)(sc) != 0) {
   1421 			aprint_error_dev(sc->sc_dev, "device enable failed\n");
   1422 			return (EIO);
   1423 		}
   1424 	}
   1425 
   1426 	sc->sc_flags |= SMC_FLAGS_ENABLED;
   1427 	return (0);
   1428 }
   1429 
   1430 /*
   1431  * Disable power on the interface.
   1432  */
   1433 void
   1434 smc91cxx_disable(struct smc91cxx_softc *sc)
   1435 {
   1436 
   1437 	if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) {
   1438 		(*sc->sc_disable)(sc);
   1439 		sc->sc_flags &= ~SMC_FLAGS_ENABLED;
   1440 	}
   1441 }
   1442 
   1443 int
   1444 smc91cxx_activate(device_t self, enum devact act)
   1445 {
   1446 	struct smc91cxx_softc *sc = device_private(self);
   1447 
   1448 	switch (act) {
   1449 	case DVACT_DEACTIVATE:
   1450 		if_deactivate(&sc->sc_ec.ec_if);
   1451 		return 0;
   1452 	default:
   1453 		return EOPNOTSUPP;
   1454 	}
   1455 }
   1456 
   1457 int
   1458 smc91cxx_detach(device_t self, int flags)
   1459 {
   1460 	struct smc91cxx_softc *sc = device_private(self);
   1461 	struct ifnet *ifp = &sc->sc_ec.ec_if;
   1462 
   1463 	/* Succeed now if there's no work to do. */
   1464 	if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0)
   1465 		return (0);
   1466 
   1467 	/* smc91cxx_disable() checks SMC_FLAGS_ENABLED */
   1468 	smc91cxx_disable(sc);
   1469 
   1470 	/* smc91cxx_attach() never fails */
   1471 
   1472 	/* Delete all media. */
   1473 	ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
   1474 
   1475 	rnd_detach_source(&sc->rnd_source);
   1476 
   1477 	ether_ifdetach(ifp);
   1478 	if_detach(ifp);
   1479 
   1480 	return (0);
   1481 }
   1482 
   1483 u_int32_t
   1484 smc91cxx_mii_bitbang_read(device_t self)
   1485 {
   1486 	struct smc91cxx_softc *sc = device_private(self);
   1487 
   1488 	/* We're already in bank 3. */
   1489 	return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W));
   1490 }
   1491 
   1492 void
   1493 smc91cxx_mii_bitbang_write(device_t self, u_int32_t val)
   1494 {
   1495 	struct smc91cxx_softc *sc = device_private(self);
   1496 
   1497 	/* We're already in bank 3. */
   1498 	bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val);
   1499 }
   1500 
   1501 int
   1502 smc91cxx_mii_readreg(device_t self, int phy, int reg)
   1503 {
   1504 	struct smc91cxx_softc *sc = device_private(self);
   1505 	int val;
   1506 
   1507 	SMC_SELECT_BANK(sc, 3);
   1508 
   1509 	val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg);
   1510 
   1511 	SMC_SELECT_BANK(sc, 2);
   1512 
   1513 	return (val);
   1514 }
   1515 
   1516 void
   1517 smc91cxx_mii_writereg(device_t self, int phy, int reg, int val)
   1518 {
   1519 	struct smc91cxx_softc *sc = device_private(self);
   1520 
   1521 	SMC_SELECT_BANK(sc, 3);
   1522 
   1523 	mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val);
   1524 
   1525 	SMC_SELECT_BANK(sc, 2);
   1526 }
   1527 
   1528 void
   1529 smc91cxx_statchg(struct ifnet *ifp)
   1530 {
   1531 	struct smc91cxx_softc *sc = ifp->if_softc;
   1532 	bus_space_tag_t bst = sc->sc_bst;
   1533 	bus_space_handle_t bsh = sc->sc_bsh;
   1534 	int mctl;
   1535 
   1536 	SMC_SELECT_BANK(sc, 0);
   1537 	mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W);
   1538 	if (sc->sc_mii.mii_media_active & IFM_FDX)
   1539 		mctl |= TCR_SWFDUP;
   1540 	else
   1541 		mctl &= ~TCR_SWFDUP;
   1542 	bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl);
   1543 	SMC_SELECT_BANK(sc, 2);	/* back to operating window */
   1544 }
   1545 
   1546 /*
   1547  * One second timer, used to tick the MII.
   1548  */
   1549 void
   1550 smc91cxx_tick(void *arg)
   1551 {
   1552 	struct smc91cxx_softc *sc = arg;
   1553 	int s;
   1554 
   1555 #ifdef DIAGNOSTIC
   1556 	if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0)
   1557 		panic("smc91cxx_tick");
   1558 #endif
   1559 
   1560 	if (!device_is_active(sc->sc_dev))
   1561 		return;
   1562 
   1563 	s = splnet();
   1564 	mii_tick(&sc->sc_mii);
   1565 	splx(s);
   1566 
   1567 	callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc);
   1568 }
   1569