ptcd.c revision 1.3 
1/* $NetBSD: ptcd.c,v 1.3 2012/12/17 17:46:27 mbalmer Exp $ */
2
3/*
4 * Copyright (c) 2012 Marc Balmer <marc@msys.ch>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * Driver for the Protech PS3100 cash drawer port.
30 */
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/device.h>
35#include <sys/gpio.h>
36#include <sys/kernel.h>
37#include <sys/bus.h>
38
39#include <dev/gpio/gpiovar.h>
40
41#include <dev/isa/isareg.h>
42#include <dev/isa/isavar.h>
43
44/*
45 * To assert the cash drawer pulse, 0x00 must be written to I/O register 0x48f
46 * To stop the cash drawer pulse, 0x02 must be written to I/O register 0x48f
47 * To read out the current cash drawer state (sense pin), read bit 7 of
48 * I/O register 0x48d
49 */
50
51#define PTCD_READ_REG	0x48d
52
53/* register offsets, counted from PTCD_READ_REG */
54#define PTCD_READ	0x00
55#define PTCD_WRITE	0x02
56
57/* Read mask */
58#define PTCD_SENSE	0x80
59
60/* Write values */
61#define PTCD_OPEN	0x00
62#define PTCD_CLOSE	0x02
63
64#define PTCD_NPINS	2
65#define PIN_WRITE	0
66#define	PIN_READ	1
67
68#define PTCD_ADDR_SIZE	0x03
69
70struct ptcd_softc {
71	bus_space_tag_t sc_iot;
72	bus_space_handle_t sc_ioh;
73
74	/* GPIO interface */
75	struct gpio_chipset_tag	sc_gpio_gc;
76	gpio_pin_t		sc_gpio_pins[PTCD_NPINS];
77};
78
79int ptcd_match(device_t, struct cfdata *, void *);
80void ptcd_attach(device_t, device_t, void *);
81
82int	ptcd_gpio_pin_read(void *, int);
83void	ptcd_gpio_pin_write(void *, int, int);
84void	ptcd_gpio_pin_ctl(void *, int, int);
85
86CFATTACH_DECL2_NEW(ptcd, sizeof(struct ptcd_softc), ptcd_match, ptcd_attach,
87    NULL, NULL, NULL, NULL);
88
89int
90ptcd_match(device_t parent, struct cfdata *match, void *aux)
91{
92	struct isa_attach_args *ia = aux;
93
94	if (ia->ia_nio < 1)
95		return 0;
96
97	if (ISA_DIRECT_CONFIG(ia))
98		return 0;
99
100	if (ia->ia_io[0].ir_addr != PTCD_READ_REG)
101		return 0;
102
103	ia->ia_io[0].ir_size = PTCD_ADDR_SIZE;
104	ia->ia_niomem = 0;
105	ia->ia_nirq = 0;
106	ia->ia_ndrq = 0;
107
108	return 1;
109}
110
111void
112ptcd_attach(device_t parent, device_t self, void *aux)
113{
114	struct ptcd_softc *sc;
115	struct isa_attach_args *ia = aux;
116	struct gpiobus_attach_args gba;
117
118	sc = device_private(self);
119
120	sc->sc_iot = ia->ia_iot;
121	if (bus_space_map(sc->sc_iot, ia->ia_io[0].ir_addr, PTCD_ADDR_SIZE, 0,
122	    &sc->sc_ioh)) {
123		aprint_error(": can't map i/o space\n");
124		return;
125	}
126
127	aprint_normal(": Protech PS3100 cash drawer\n");
128
129	/* Initialize pins array */
130	sc->sc_gpio_pins[PIN_WRITE].pin_num = 0;
131	sc->sc_gpio_pins[PIN_WRITE].pin_caps = GPIO_PIN_OUTPUT;
132	sc->sc_gpio_pins[PIN_READ].pin_num = 1;
133	sc->sc_gpio_pins[PIN_READ].pin_caps = GPIO_PIN_INPUT;
134
135	/* Create controller tag */
136	sc->sc_gpio_gc.gp_cookie = sc;
137	sc->sc_gpio_gc.gp_pin_read = ptcd_gpio_pin_read;
138	sc->sc_gpio_gc.gp_pin_write = ptcd_gpio_pin_write;
139	sc->sc_gpio_gc.gp_pin_ctl = ptcd_gpio_pin_ctl;
140
141	gba.gba_gc = &sc->sc_gpio_gc;
142	gba.gba_pins = sc->sc_gpio_pins;
143	gba.gba_npins = PTCD_NPINS;
144
145	/* Attach GPIO framework */
146	config_found_ia(self, "gpiobus", &gba, gpiobus_print);
147}
148
149int
150ptcd_gpio_pin_read(void *arg, int pin)
151{
152	struct ptcd_softc *sc = arg;
153	uint8_t data;
154
155	if (pin != PIN_READ)
156		return 0;
157
158	data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PTCD_READ);
159	return data & PTCD_SENSE ? 0 : 1;
160}
161
162void
163ptcd_gpio_pin_write(void *arg, int pin, int value)
164{
165	struct ptcd_softc *sc = arg;
166
167	if (pin != PIN_WRITE)
168		return;
169
170	bus_space_write_1(sc->sc_iot, sc->sc_ioh, PTCD_WRITE,
171	    value ? PTCD_OPEN : PTCD_CLOSE);
172}
173
174void
175ptcd_gpio_pin_ctl(void *arg, int pin, int flags)
176{
177	/* We ignore pin control requests since the pin functions are fixed. */
178}
179