ofw_isa.h revision 1.1 
1/*	$NetBSD: ofw_isa.h,v 1.1 2025/10/18 15:40:59 thorpej Exp $	*/
2
3/*-
4 * Copyright (c) 2025 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _DEV_OFW_OFW_ISA_H_
33#define	_DEV_OFW_OFW_ISA_H_
34
35/*
36 * ISA Bus Binding to:
37 *
38 * IEEE Std 1275-1994
39 * Standard for Boot (Initialization Configuration) Firmware
40 *
41 * Revision: 0.4 (Unapproved Draft)
42 * September 23, 1996
43 */
44
45/*
46 * Section 2.2.1. Physical Address Formats
47 *
48 * An ISA physical address is represented by 2 address cells:
49 *
50 *	phys.hi cell:	00000000 00000000 00000000 00000vti
51 *	phys.lo cell:	nnnnnnnn nnnnnnnn nnnnnnnn nnnnnnnn
52 *
53 *	v	address is 11-bit aliased
54 *	t	address is 10-bit aliased
55 *	i	address is in I/O space (vs memory space)
56 *	n	32-bit address
57 */
58
59#define	OFW_ISA_PHYS_HI_IO		__BIT(0)
60#define	OFW_ISA_PHYS_HI_10BIT		__BIT(1)
61#define	OFW_ISA_PHYS_HI_11BIT		__BIT(2)
62
63/*
64 * This has the 2 32bit cell values, plus another to make up a 32-bit size.
65 */
66struct ofw_isa_register {
67	uint32_t	phys_hi;
68	uint32_t	phys_lo;
69	uint32_t	size;
70};
71
72/*
73 * Section 4.1.1.  Properties for child nodes.
74 *
75 * "interrupts"
76 *
77 * Interrupts are encoded with a prop-encoded-array of the following
78 * integers:
79 *
80 *	irq		IRQ number (0-15)
81 *	type		IRQ type	0 active low level trigger
82 *					1 active high level trigger
83 *					2 falling edge trigger
84 *					3 rising edge trigger
85 */
86
87#define	OFW_ISA_INTR_TYPE_LOW_LEVEL	0
88#define	OFW_ISA_INTR_TYPE_HIGH_LEVEL	1
89#define	OFW_ISA_INTR_TYPE_FALLING_EDGE	2
90#define	OFW_ISA_INTR_TYPE_RISING_EDGE	3
91
92struct ofw_isa_interrupt {
93	uint32_t	irq;
94	uint32_t	type;
95};
96
97/*
98 * Section 4.1.2.  Bus-specific properties for child nodes.
99 *
100 * "dma"
101 *
102 * DMA information is encoded in a prop-encoded-array of the following
103 * integers:
104 *
105 *	dma#		DRQ (0-3, 5-7)
106 *	mode		DMA channel mode
107 *	width		DMA transfer size in bits (8, 16, 32)
108 *	coundwidth	DMA transfer size count units (8, 16, 32)
109 *	busmaster	1=bus master, 0=not-a-bus master
110 */
111
112#define	OFW_ISA_DMA_MODE_COMPAT		0
113#define	OFW_ISA_DMA_MODE_A		1
114#define	OFW_ISA_DMA_MODE_B		2
115#define	OFW_ISA_DMA_MODE_F		3
116#define	OFW_ISA_DMA_MODE_C		4
117
118struct ofw_isa_dma {
119	uint32_t	drq;
120	uint32_t	mode;
121	uint32_t	width;
122	uint32_t	countwidth;
123	uint32_t	busmaster;
124};
125
126#endif /* _DEV_OFW_OFW_ISA_H_ */
127