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agp_amd64.c revision 1.7
      1 /*-
      2  * Copyright (c) 2004, 2005 Jung-uk Kim <jkim (at) FreeBSD.org>
      3  * All rights reserved.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions
      7  * are met:
      8  * 1. Redistributions of source code must retain the above copyright
      9  *    notice, this list of conditions and the following disclaimer.
     10  * 2. Redistributions in binary form must reproduce the above copyright
     11  *    notice, this list of conditions and the following disclaimer in the
     12  *    documentation and/or other materials provided with the distribution.
     13  *
     14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     24  * SUCH DAMAGE.
     25  */
     26 
     27 #include <sys/cdefs.h>
     28 __KERNEL_RCSID(0, "$NetBSD: agp_amd64.c,v 1.6 2010/11/13 13:52:04 uebayasi Exp $");
     29 
     30 #include <sys/param.h>
     31 #include <sys/systm.h>
     32 #include <sys/malloc.h>
     33 #include <sys/kernel.h>
     34 #include <sys/proc.h>
     35 #include <sys/conf.h>
     36 #include <sys/device.h>
     37 #include <sys/agpio.h>
     38 
     39 #include <dev/pci/pcivar.h>
     40 #include <dev/pci/pcireg.h>
     41 #include <dev/pci/agpvar.h>
     42 #include <dev/pci/agpreg.h>
     43 
     44 #include <dev/pci/pcidevs.h>
     45 
     46 #include <sys/bus.h>
     47 
     48 
     49 #define	AMD64_MAX_MCTRL		8
     50 
     51 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
     52 #define AGP_AMD64_NVIDIA_PCITAG(pc)	pci_make_tag(pc, 0, 11, 0)
     53 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
     54 #define AGP_AMD64_VIA_PCITAG(pc)	pci_make_tag(pc, 0, 1, 0)
     55 
     56 
     57 static uint32_t agp_amd64_get_aperture(struct agp_softc *);
     58 static int agp_amd64_set_aperture(struct agp_softc *, uint32_t);
     59 static int agp_amd64_bind_page(struct agp_softc *, off_t, bus_addr_t);
     60 static int agp_amd64_unbind_page(struct agp_softc *, off_t);
     61 static void agp_amd64_flush_tlb(struct agp_softc *);
     62 
     63 static void agp_amd64_apbase_fixup(struct agp_softc *);
     64 
     65 static void agp_amd64_uli_init(struct agp_softc *);
     66 static int agp_amd64_uli_set_aperture(struct agp_softc *, uint32_t);
     67 
     68 static int agp_amd64_nvidia_match(const struct pci_attach_args *, uint16_t);
     69 static void agp_amd64_nvidia_init(struct agp_softc *);
     70 static int agp_amd64_nvidia_set_aperture(struct agp_softc *, uint32_t);
     71 
     72 static int agp_amd64_via_match(const struct pci_attach_args *);
     73 static void agp_amd64_via_init(struct agp_softc *);
     74 static int agp_amd64_via_set_aperture(struct agp_softc *, uint32_t);
     75 
     76 
     77 struct agp_amd64_softc {
     78 	uint32_t		initial_aperture;
     79 	struct agp_gatt		*gatt;
     80 	uint32_t		apbase;
     81 	pcitag_t		ctrl_tag;	/* use NVIDIA and VIA */
     82 	pcitag_t		mctrl_tag[AMD64_MAX_MCTRL];
     83 	int			n_mctrl;
     84 	int			via_agp;
     85 };
     86 
     87 static struct agp_methods agp_amd64_methods = {
     88 	agp_amd64_get_aperture,
     89 	agp_amd64_set_aperture,
     90 	agp_amd64_bind_page,
     91 	agp_amd64_unbind_page,
     92 	agp_amd64_flush_tlb,
     93 	agp_generic_enable,
     94 	agp_generic_alloc_memory,
     95 	agp_generic_free_memory,
     96 	agp_generic_bind_memory,
     97 	agp_generic_unbind_memory,
     98 };
     99 
    100 
    101 int
    102 agp_amd64_match(const struct pci_attach_args *pa)
    103 {
    104 
    105 	switch (PCI_VENDOR(pa->pa_id)) {
    106 	case PCI_VENDOR_AMD:
    107 		switch (PCI_PRODUCT(pa->pa_id)) {
    108 		case PCI_PRODUCT_AMD_AGP8151_DEV:
    109 			return 1;
    110 		}
    111 		break;
    112 
    113 	case PCI_VENDOR_SIS:
    114 		switch (PCI_PRODUCT(pa->pa_id)) {
    115 		case PCI_PRODUCT_SIS_755:
    116 		case PCI_PRODUCT_SIS_760:
    117 			return 1;
    118 		}
    119 		break;
    120 
    121 	case PCI_VENDOR_ALI:
    122 		switch (PCI_PRODUCT(pa->pa_id)) {
    123 		case PCI_PRODUCT_ALI_M1689:
    124 			return 1;
    125 		}
    126 		break;
    127 
    128 	case PCI_VENDOR_NVIDIA:
    129 		switch (PCI_PRODUCT(pa->pa_id)) {
    130 		case PCI_PRODUCT_NVIDIA_NFORCE3_PCHB:
    131 			return agp_amd64_nvidia_match(pa,
    132 			    PCI_PRODUCT_NVIDIA_NFORCE3_PPB2);
    133 
    134 			/* NOTREACHED */
    135 
    136 		case PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB:
    137 			return agp_amd64_nvidia_match(pa,
    138 			    PCI_PRODUCT_NVIDIA_NFORCE3_250_AGP);
    139 
    140 			/* NOTREACHED */
    141 		}
    142 		break;
    143 
    144 	case PCI_VENDOR_VIATECH:
    145 		switch (PCI_PRODUCT(pa->pa_id)) {
    146 		case PCI_PRODUCT_VIATECH_K8M800_0:
    147 		case PCI_PRODUCT_VIATECH_K8T890_0:
    148 		case PCI_PRODUCT_VIATECH_K8HTB_0:
    149 		case PCI_PRODUCT_VIATECH_K8HTB:
    150 			return 1;
    151 		}
    152 		break;
    153 	}
    154 
    155 	return 0;
    156 }
    157 
    158 static int
    159 agp_amd64_nvidia_match(const struct pci_attach_args *pa, uint16_t devid)
    160 {
    161 	pcitag_t tag;
    162 	pcireg_t reg;
    163 
    164 	tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
    165 
    166 	reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
    167 	if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
    168 	    PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
    169 		return 0;
    170 
    171 	reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
    172 	if (PCI_VENDOR(reg) != PCI_VENDOR_NVIDIA || PCI_PRODUCT(reg) != devid)
    173 		return 0;
    174 
    175 	return 1;
    176 }
    177 
    178 static int
    179 agp_amd64_via_match(const struct pci_attach_args *pa)
    180 {
    181 	pcitag_t tag;
    182 	pcireg_t reg;
    183 
    184 	tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
    185 
    186 	reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
    187 	if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
    188 	    PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
    189 		return 0;
    190 
    191 	reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
    192 	if (PCI_VENDOR(reg) != PCI_VENDOR_VIATECH ||
    193 	    PCI_PRODUCT(reg) != PCI_PRODUCT_VIATECH_K8HTB_AGP)
    194 		return 0;
    195 
    196 	return 1;
    197 }
    198 
    199 int
    200 agp_amd64_attach(device_t parent, device_t self, void *aux)
    201 {
    202 	struct agp_softc *sc = device_private(self);
    203 	struct agp_amd64_softc *asc;
    204 	struct pci_attach_args *pa = aux;
    205 	struct agp_gatt *gatt;
    206 	pcitag_t tag;
    207 	pcireg_t id, attbase, apctrl;
    208 	int maxdevs, i, n;
    209 
    210 	asc = malloc(sizeof(struct agp_amd64_softc), M_AGP, M_NOWAIT | M_ZERO);
    211 	if (asc == NULL) {
    212 		aprint_error(": can't allocate softc\n");
    213 		return ENOMEM;
    214 	}
    215 
    216 	if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) {
    217 		aprint_error(": can't map aperture\n");
    218 		free(asc, M_AGP);
    219 		return ENXIO;
    220 	}
    221 
    222 	maxdevs = pci_bus_maxdevs(pa->pa_pc, 0);
    223 	for (i = 0, n = 0; i < maxdevs && n < AMD64_MAX_MCTRL; i++) {
    224 		tag = pci_make_tag(pa->pa_pc, 0, i, 3);
    225 		id = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
    226 		if (PCI_VENDOR(id) == PCI_VENDOR_AMD &&
    227 		    (PCI_PRODUCT(id) == PCI_PRODUCT_AMD_AMD64_MISC ||
    228 		     PCI_PRODUCT(id) == PCI_PRODUCT_AMD_AMD64_F10_MISC)) {
    229 			asc->mctrl_tag[n] = tag;
    230 			n++;
    231 		}
    232 	}
    233 	if (n == 0) {
    234 		aprint_error(": No Miscellaneous Control unit found.\n");
    235 		return ENXIO;
    236 	}
    237 	asc->n_mctrl = n;
    238 
    239 	aprint_normal(": %d Miscellaneous Control unit(s) found.\n",
    240 	    asc->n_mctrl);
    241 	aprint_normal("%s", device_xname(self));
    242 
    243 	sc->as_chipc = asc;
    244 	sc->as_methods = &agp_amd64_methods;
    245 	pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
    246 	    NULL);
    247 	asc->initial_aperture = AGP_GET_APERTURE(sc);
    248 
    249 	for (;;) {
    250 		gatt = agp_alloc_gatt(sc);
    251 		if (gatt)
    252 			break;
    253 
    254 		/*
    255 		 * Probably contigmalloc failure. Try reducing the
    256 		 * aperture so that the gatt size reduces.
    257 		 */
    258 		if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
    259 			agp_generic_detach(sc);
    260 			return ENOMEM;
    261 		}
    262 	}
    263 	asc->gatt = gatt;
    264 
    265 	switch (PCI_VENDOR(sc->as_id)) {
    266 	case PCI_VENDOR_ALI:
    267 		agp_amd64_uli_init(sc);
    268 		if (agp_amd64_uli_set_aperture(sc, asc->initial_aperture))
    269 			return ENXIO;
    270 		break;
    271 
    272 	case PCI_VENDOR_NVIDIA:
    273 		asc->ctrl_tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
    274 		agp_amd64_nvidia_init(sc);
    275 		if (agp_amd64_nvidia_set_aperture(sc, asc->initial_aperture))
    276 			return ENXIO;
    277 		break;
    278 
    279 	case PCI_VENDOR_VIATECH:
    280 		asc->via_agp = agp_amd64_via_match(pa);
    281 		if (asc->via_agp) {
    282 			asc->ctrl_tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
    283 			agp_amd64_via_init(sc);
    284 			if (agp_amd64_via_set_aperture(sc,
    285 			    asc->initial_aperture))
    286 				return ENXIO;
    287 		}
    288 		break;
    289 	}
    290 
    291 	/* Install the gatt and enable aperture. */
    292 	attbase = (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK;
    293 	for (i = 0; i < asc->n_mctrl; i++) {
    294 		pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_ATTBASE,
    295 		    attbase);
    296 		apctrl = pci_conf_read(pa->pa_pc, asc->mctrl_tag[i],
    297 		    AGP_AMD64_APCTRL);
    298 		apctrl |= AGP_AMD64_APCTRL_GARTEN;
    299 		apctrl &=
    300 		    ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO);
    301 		pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_APCTRL,
    302 		    apctrl);
    303 	}
    304 
    305 	agp_flush_cache();
    306 
    307 	return 0;
    308 }
    309 
    310 
    311 static uint32_t agp_amd64_table[] = {
    312 	0x02000000,	/*   32 MB */
    313 	0x04000000,	/*   64 MB */
    314 	0x08000000,	/*  128 MB */
    315 	0x10000000,	/*  256 MB */
    316 	0x20000000,	/*  512 MB */
    317 	0x40000000,	/* 1024 MB */
    318 	0x80000000,	/* 2048 MB */
    319 };
    320 
    321 #define AGP_AMD64_TABLE_SIZE \
    322 	(sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
    323 
    324 static uint32_t
    325 agp_amd64_get_aperture(struct agp_softc *sc)
    326 {
    327 	struct agp_amd64_softc *asc = sc->as_chipc;
    328 	uint32_t i;
    329 
    330 	i = (pci_conf_read(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL) &
    331 		AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
    332 
    333 	if (i >= AGP_AMD64_TABLE_SIZE)
    334 		return 0;
    335 
    336 	return agp_amd64_table[i];
    337 }
    338 
    339 static int
    340 agp_amd64_set_aperture(struct agp_softc *sc, uint32_t aperture)
    341 {
    342 	struct agp_amd64_softc *asc = sc->as_chipc;
    343 	uint32_t i;
    344 	pcireg_t apctrl;
    345 	int j;
    346 
    347 	for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
    348 		if (agp_amd64_table[i] == aperture)
    349 			break;
    350 	if (i >= AGP_AMD64_TABLE_SIZE)
    351 		return EINVAL;
    352 
    353 	for (j = 0; j < asc->n_mctrl; j++) {
    354 		apctrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[0],
    355 		    AGP_AMD64_APCTRL);
    356 		pci_conf_write(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL,
    357 		    (apctrl & ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1));
    358 	}
    359 
    360 	switch (PCI_VENDOR(sc->as_id)) {
    361 	case PCI_VENDOR_ALI:
    362 		return agp_amd64_uli_set_aperture(sc, aperture);
    363 		break;
    364 
    365 	case PCI_VENDOR_NVIDIA:
    366 		return agp_amd64_nvidia_set_aperture(sc, aperture);
    367 		break;
    368 
    369 	case PCI_VENDOR_VIATECH:
    370 		if (asc->via_agp)
    371 			return agp_amd64_via_set_aperture(sc, aperture);
    372 		break;
    373 	}
    374 
    375 	return 0;
    376 }
    377 
    378 static int
    379 agp_amd64_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
    380 {
    381 	struct agp_amd64_softc *asc = sc->as_chipc;
    382 
    383 	if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
    384 		return EINVAL;
    385 
    386 	asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
    387 	    (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
    388 
    389 	return 0;
    390 }
    391 
    392 static int
    393 agp_amd64_unbind_page(struct agp_softc *sc, off_t offset)
    394 {
    395 	struct agp_amd64_softc *asc = sc->as_chipc;
    396 
    397 	if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
    398 		return EINVAL;
    399 
    400 	asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
    401 
    402 	return 0;
    403 }
    404 
    405 static void
    406 agp_amd64_flush_tlb(struct agp_softc *sc)
    407 {
    408 	struct agp_amd64_softc *asc = sc->as_chipc;
    409 	pcireg_t cachectrl;
    410 	int i;
    411 
    412 	for (i = 0; i < asc->n_mctrl; i++) {
    413 		cachectrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[i],
    414 		    AGP_AMD64_CACHECTRL);
    415 		pci_conf_write(sc->as_pc, asc->mctrl_tag[i],
    416 		    AGP_AMD64_CACHECTRL,
    417 		    cachectrl | AGP_AMD64_CACHECTRL_INVGART);
    418 	}
    419 }
    420 
    421 static void
    422 agp_amd64_apbase_fixup(struct agp_softc *sc)
    423 {
    424 	struct agp_amd64_softc *asc = sc->as_chipc;
    425 	uint32_t apbase;
    426 	int i;
    427 
    428 	apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_APBASE);
    429 	asc->apbase = PCI_MAPREG_MEM_ADDR(apbase);
    430 	apbase = (asc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
    431 	for (i = 0; i < asc->n_mctrl; i++)
    432 		pci_conf_write(sc->as_pc, asc->mctrl_tag[i], AGP_AMD64_APBASE,
    433 		    apbase);
    434 }
    435 
    436 static void
    437 agp_amd64_uli_init(struct agp_softc *sc)
    438 {
    439 	struct agp_amd64_softc *asc = sc->as_chipc;
    440 	pcireg_t apbase;
    441 
    442 	agp_amd64_apbase_fixup(sc);
    443 	apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE);
    444 	pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE,
    445 	    (apbase & 0x0000000f) | asc->apbase);
    446 	pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_HTT_FEATURE,
    447 	    asc->apbase);
    448 }
    449 
    450 static int
    451 agp_amd64_uli_set_aperture(struct agp_softc *sc, uint32_t aperture)
    452 {
    453 	struct agp_amd64_softc *asc = sc->as_chipc;
    454 
    455 	switch (aperture) {
    456 	case 0x02000000:	/*  32 MB */
    457 	case 0x04000000:	/*  64 MB */
    458 	case 0x08000000:	/* 128 MB */
    459 	case 0x10000000:	/* 256 MB */
    460 		break;
    461 	default:
    462 		return EINVAL;
    463 	}
    464 
    465 	pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_ENU_SCR,
    466 	    asc->apbase + aperture - 1);
    467 
    468 	return 0;
    469 }
    470 
    471 static void
    472 agp_amd64_nvidia_init(struct agp_softc *sc)
    473 {
    474 	struct agp_amd64_softc *asc = sc->as_chipc;
    475 	pcireg_t apbase;
    476 
    477 	agp_amd64_apbase_fixup(sc);
    478 	apbase =
    479 	    pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE);
    480 	pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE,
    481 	    (apbase & 0x0000000f) | asc->apbase);
    482 	pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE1,
    483 	    asc->apbase);
    484 	pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE2,
    485 	    asc->apbase);
    486 }
    487 
    488 static int
    489 agp_amd64_nvidia_set_aperture(struct agp_softc *sc, uint32_t aperture)
    490 {
    491 	struct agp_amd64_softc *asc = sc->as_chipc;
    492 	uint32_t apsize;
    493 
    494 	switch (aperture) {
    495 	case 0x02000000:	apsize = 0x0f;	break;	/*  32 MB */
    496 	case 0x04000000:	apsize = 0x0e;	break;	/*  64 MB */
    497 	case 0x08000000:	apsize = 0x0c;	break;	/* 128 MB */
    498 	case 0x10000000:	apsize = 0x08;	break;	/* 256 MB */
    499 	case 0x20000000:	apsize = 0x00;	break;	/* 512 MB */
    500 	default:
    501 		return EINVAL;
    502 	}
    503 
    504 	pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APSIZE,
    505 	    (pci_conf_read(sc->as_pc, asc->ctrl_tag,
    506 	    AGP_AMD64_NVIDIA_1_APSIZE) & 0xfffffff0) | apsize);
    507 	pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT1,
    508 	    asc->apbase + aperture - 1);
    509 	pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT2,
    510 	    asc->apbase + aperture - 1);
    511 
    512 	return 0;
    513 }
    514 
    515 static void
    516 agp_amd64_via_init(struct agp_softc *sc)
    517 {
    518 	struct agp_amd64_softc *asc = sc->as_chipc;
    519 
    520 	agp_amd64_apbase_fixup(sc);
    521 	pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE,
    522 	    asc->gatt->ag_physical);
    523 	pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_GARTCTRL,
    524 	    pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE) | 0x180);
    525 }
    526 
    527 static int
    528 agp_amd64_via_set_aperture(struct agp_softc *sc, uint32_t aperture)
    529 {
    530 	struct agp_amd64_softc *asc = sc->as_chipc;
    531 	uint32_t apsize;
    532 
    533 	apsize = ((aperture - 1) >> 20) ^ 0xff;
    534 	if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
    535 		return EINVAL;
    536 	pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE,
    537 	    (pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE) & ~0xff) |
    538 	    apsize);
    539 
    540 	return 0;
    541 }
    542