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      1 /* $NetBSD: if_bce.c,v 1.43 2016/12/08 01:12:01 ozaki-r Exp $	 */
      2 
      3 /*
      4  * Copyright (c) 2003 Clifford Wright. All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     22  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     23  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     24  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     25  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     27  * SUCH DAMAGE.
     28  */
     29 
     30 /*
     31  * Broadcom BCM440x 10/100 ethernet (broadcom.com)
     32  * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com)
     33  *
     34  * Cliff Wright cliff (at) snipe444.org
     35  */
     36 
     37 #include <sys/cdefs.h>
     38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.43 2016/12/08 01:12:01 ozaki-r Exp $");
     39 
     40 #include "vlan.h"
     41 
     42 #include <sys/param.h>
     43 #include <sys/systm.h>
     44 #include <sys/callout.h>
     45 #include <sys/sockio.h>
     46 #include <sys/mbuf.h>
     47 #include <sys/malloc.h>
     48 #include <sys/kernel.h>
     49 #include <sys/device.h>
     50 #include <sys/socket.h>
     51 
     52 #include <net/if.h>
     53 #include <net/if_dl.h>
     54 #include <net/if_media.h>
     55 #include <net/if_ether.h>
     56 
     57 #include <net/bpf.h>
     58 #include <sys/rndsource.h>
     59 
     60 #include <dev/pci/pcireg.h>
     61 #include <dev/pci/pcivar.h>
     62 #include <dev/pci/pcidevs.h>
     63 
     64 #include <dev/mii/mii.h>
     65 #include <dev/mii/miivar.h>
     66 #include <dev/mii/miidevs.h>
     67 #include <dev/mii/brgphyreg.h>
     68 
     69 #include <dev/pci/if_bcereg.h>
     70 
     71 /* transmit buffer max frags allowed */
     72 #define BCE_NTXFRAGS	16
     73 
     74 /* ring descriptor */
     75 struct bce_dma_slot {
     76 	uint32_t ctrl;
     77 	uint32_t addr;
     78 };
     79 #define CTRL_BC_MASK	0x1fff	/* buffer byte count */
     80 #define CTRL_EOT	0x10000000	/* end of descriptor table */
     81 #define CTRL_IOC	0x20000000	/* interrupt on completion */
     82 #define CTRL_EOF	0x40000000	/* end of frame */
     83 #define CTRL_SOF	0x80000000	/* start of frame */
     84 
     85 /* Packet status is returned in a pre-packet header */
     86 struct rx_pph {
     87 	uint16_t len;
     88 	uint16_t flags;
     89 	uint16_t pad[12];
     90 };
     91 
     92 /* packet status flags bits */
     93 #define RXF_NO				0x8	/* odd number of nibbles */
     94 #define RXF_RXER			0x4	/* receive symbol error */
     95 #define RXF_CRC				0x2	/* crc error */
     96 #define RXF_OV				0x1	/* fifo overflow */
     97 
     98 /* number of descriptors used in a ring */
     99 #define BCE_NRXDESC		128
    100 #define BCE_NTXDESC		128
    101 
    102 /*
    103  * Mbuf pointers. We need these to keep track of the virtual addresses
    104  * of our mbuf chains since we can only convert from physical to virtual,
    105  * not the other way around.
    106  */
    107 struct bce_chain_data {
    108 	struct mbuf    *bce_tx_chain[BCE_NTXDESC];
    109 	struct mbuf    *bce_rx_chain[BCE_NRXDESC];
    110 	bus_dmamap_t	bce_tx_map[BCE_NTXDESC];
    111 	bus_dmamap_t	bce_rx_map[BCE_NRXDESC];
    112 };
    113 
    114 #define BCE_TIMEOUT		100	/* # 10us for mii read/write */
    115 
    116 struct bce_softc {
    117 	device_t		bce_dev;
    118 	bus_space_tag_t		bce_btag;
    119 	bus_space_handle_t	bce_bhandle;
    120 	bus_dma_tag_t		bce_dmatag;
    121 	struct ethercom		ethercom;	/* interface info */
    122 	void			*bce_intrhand;
    123 	struct pci_attach_args	bce_pa;
    124 	struct mii_data		bce_mii;
    125 	uint32_t		bce_phy;	/* eeprom indicated phy */
    126 	struct ifmedia		bce_ifmedia;	/* media info *//* Check */
    127 	uint8_t			enaddr[ETHER_ADDR_LEN];
    128 	struct bce_dma_slot	*bce_rx_ring;	/* receive ring */
    129 	struct bce_dma_slot	*bce_tx_ring;	/* transmit ring */
    130 	struct bce_chain_data	bce_cdata;	/* mbufs */
    131 	bus_dmamap_t		bce_ring_map;
    132 	uint32_t		bce_intmask;	/* current intr mask */
    133 	uint32_t		bce_rxin;	/* last rx descriptor seen */
    134 	uint32_t		bce_txin;	/* last tx descriptor seen */
    135 	int			bce_txsfree;	/* no. tx slots available */
    136 	int			bce_txsnext;	/* next available tx slot */
    137 	callout_t		bce_timeout;
    138 	krndsource_t	rnd_source;
    139 };
    140 
    141 /* for ring descriptors */
    142 #define BCE_RXBUF_LEN	(MCLBYTES - 4)
    143 #define BCE_INIT_RXDESC(sc, x)						\
    144 do {									\
    145 	struct bce_dma_slot *__bced = &sc->bce_rx_ring[x];		\
    146 									\
    147 	*mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0;		\
    148 	__bced->addr =							\
    149 	    htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr	\
    150 	    + 0x40000000);						\
    151 	if (x != (BCE_NRXDESC - 1))					\
    152 		__bced->ctrl = htole32(BCE_RXBUF_LEN);			\
    153 	else								\
    154 		__bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT);	\
    155 	bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map,		\
    156 	    sizeof(struct bce_dma_slot) * x,				\
    157 	    sizeof(struct bce_dma_slot),				\
    158 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);			\
    159 } while (/* CONSTCOND */ 0)
    160 
    161 static	int	bce_probe(device_t, cfdata_t, void *);
    162 static	void	bce_attach(device_t, device_t, void *);
    163 static	int	bce_ioctl(struct ifnet *, u_long, void *);
    164 static	void	bce_start(struct ifnet *);
    165 static	void	bce_watchdog(struct ifnet *);
    166 static	int	bce_intr(void *);
    167 static	void	bce_rxintr(struct bce_softc *);
    168 static	void	bce_txintr(struct bce_softc *);
    169 static	int	bce_init(struct ifnet *);
    170 static	void	bce_add_mac(struct bce_softc *, uint8_t *, unsigned long);
    171 static	int	bce_add_rxbuf(struct bce_softc *, int);
    172 static	void	bce_rxdrain(struct bce_softc *);
    173 static	void	bce_stop(struct ifnet *, int);
    174 static	void	bce_reset(struct bce_softc *);
    175 static	bool	bce_resume(device_t, const pmf_qual_t *);
    176 static	void	bce_set_filter(struct ifnet *);
    177 static	int	bce_mii_read(device_t, int, int);
    178 static	void	bce_mii_write(device_t, int, int, int);
    179 static	void	bce_statchg(struct ifnet *);
    180 static	void	bce_tick(void *);
    181 
    182 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc),
    183 		  bce_probe, bce_attach, NULL, NULL);
    184 
    185 static const struct bce_product {
    186 	pci_vendor_id_t bp_vendor;
    187 	pci_product_id_t bp_product;
    188 	const	char *bp_name;
    189 } bce_products[] = {
    190 	{
    191 		PCI_VENDOR_BROADCOM,
    192 		PCI_PRODUCT_BROADCOM_BCM4401,
    193 		"Broadcom BCM4401 10/100 Ethernet"
    194 	},
    195 	{
    196 		PCI_VENDOR_BROADCOM,
    197 		PCI_PRODUCT_BROADCOM_BCM4401_B0,
    198 		"Broadcom BCM4401-B0 10/100 Ethernet"
    199 	},
    200 	{
    201 
    202 		0,
    203 		0,
    204 		NULL
    205 	},
    206 };
    207 
    208 static const struct bce_product *
    209 bce_lookup(const struct pci_attach_args * pa)
    210 {
    211 	const struct bce_product *bp;
    212 
    213 	for (bp = bce_products; bp->bp_name != NULL; bp++) {
    214 		if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor &&
    215 		    PCI_PRODUCT(pa->pa_id) == bp->bp_product)
    216 			return (bp);
    217 	}
    218 
    219 	return (NULL);
    220 }
    221 
    222 /*
    223  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
    224  * against drivers product list, and return its name if a match is found.
    225  */
    226 static int
    227 bce_probe(device_t parent, cfdata_t match, void *aux)
    228 {
    229 	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
    230 
    231 	if (bce_lookup(pa) != NULL)
    232 		return (1);
    233 
    234 	return (0);
    235 }
    236 
    237 static void
    238 bce_attach(device_t parent, device_t self, void *aux)
    239 {
    240 	struct bce_softc *sc = device_private(self);
    241 	struct pci_attach_args *pa = aux;
    242 	const struct bce_product *bp;
    243 	pci_chipset_tag_t pc = pa->pa_pc;
    244 	pci_intr_handle_t ih;
    245 	const char     *intrstr = NULL;
    246 	uint32_t	command;
    247 	pcireg_t	memtype, pmode;
    248 	bus_addr_t	memaddr;
    249 	bus_size_t	memsize;
    250 	void		*kva;
    251 	bus_dma_segment_t seg;
    252 	int             error, i, pmreg, rseg;
    253 	struct ifnet   *ifp;
    254 	char intrbuf[PCI_INTRSTR_LEN];
    255 
    256 	sc->bce_dev = self;
    257 
    258 	bp = bce_lookup(pa);
    259 	KASSERT(bp != NULL);
    260 
    261 	sc->bce_pa = *pa;
    262 
    263 	/* BCM440x can only address 30 bits (1GB) */
    264 	if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30),
    265 	    &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) {
    266 		aprint_error_dev(self,
    267 		    "WARNING: failed to restrict dma range,"
    268 		    " falling back to parent bus dma range\n");
    269 		sc->bce_dmatag = pa->pa_dmat;
    270 	}
    271 
    272 	 aprint_naive(": Ethernet controller\n");
    273 	 aprint_normal(": %s\n", bp->bp_name);
    274 
    275 	/*
    276 	 * Map control/status registers.
    277 	 */
    278 	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    279 	command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
    280 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
    281 	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    282 
    283 	if (!(command & PCI_COMMAND_MEM_ENABLE)) {
    284 		aprint_error_dev(self, "failed to enable memory mapping!\n");
    285 		return;
    286 	}
    287 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0);
    288 	switch (memtype) {
    289 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
    290 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
    291 		if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag,
    292 		    &sc->bce_bhandle, &memaddr, &memsize) == 0)
    293 			break;
    294 	default:
    295 		aprint_error_dev(self, "unable to find mem space\n");
    296 		return;
    297 	}
    298 
    299 	/* Get it out of power save mode if needed. */
    300 	if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) {
    301 		pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3;
    302 		if (pmode == 3) {
    303 			/*
    304 			 * The card has lost all configuration data in
    305 			 * this state, so punt.
    306 			 */
    307 			aprint_error_dev(self,
    308 			    "unable to wake up from power state D3\n");
    309 			return;
    310 		}
    311 		if (pmode != 0) {
    312 			aprint_normal_dev(self,
    313 			    "waking up from power state D%d\n", pmode);
    314 			pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0);
    315 		}
    316 	}
    317 	if (pci_intr_map(pa, &ih)) {
    318 		aprint_error_dev(self, "couldn't map interrupt\n");
    319 		return;
    320 	}
    321 	intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
    322 
    323 	sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc);
    324 
    325 	if (sc->bce_intrhand == NULL) {
    326 		aprint_error_dev(self, "couldn't establish interrupt\n");
    327 		if (intrstr != NULL)
    328 			aprint_error(" at %s", intrstr);
    329 		aprint_error("\n");
    330 		return;
    331 	}
    332 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
    333 
    334 	/* reset the chip */
    335 	bce_reset(sc);
    336 
    337 	/*
    338 	 * Allocate DMA-safe memory for ring descriptors.
    339 	 * The receive, and transmit rings can not share the same
    340 	 * 4k space, however both are allocated at once here.
    341 	 */
    342 	/*
    343 	 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but
    344 	 * due to the limition above. ??
    345 	 */
    346 	if ((error = bus_dmamem_alloc(sc->bce_dmatag,
    347 	    2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE,
    348 	    &seg, 1, &rseg, BUS_DMA_NOWAIT))) {
    349 		aprint_error_dev(self,
    350 		    "unable to alloc space for ring descriptors, error = %d\n",
    351 		    error);
    352 		return;
    353 	}
    354 	/* map ring space to kernel */
    355 	if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg,
    356 	    2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) {
    357 		aprint_error_dev(self,
    358 		    "unable to map DMA buffers, error = %d\n", error);
    359 		bus_dmamem_free(sc->bce_dmatag, &seg, rseg);
    360 		return;
    361 	}
    362 	/* create a dma map for the ring */
    363 	if ((error = bus_dmamap_create(sc->bce_dmatag,
    364 	    2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT,
    365 	    &sc->bce_ring_map))) {
    366 		aprint_error_dev(self,
    367 		    "unable to create ring DMA map, error = %d\n", error);
    368 		bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE);
    369 		bus_dmamem_free(sc->bce_dmatag, &seg, rseg);
    370 		return;
    371 	}
    372 	/* connect the ring space to the dma map */
    373 	if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva,
    374 	    2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) {
    375 		bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map);
    376 		bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE);
    377 		bus_dmamem_free(sc->bce_dmatag, &seg, rseg);
    378 		return;
    379 	}
    380 	/* save the ring space in softc */
    381 	sc->bce_rx_ring = (struct bce_dma_slot *) kva;
    382 	sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE);
    383 
    384 	/* Create the transmit buffer DMA maps. */
    385 	for (i = 0; i < BCE_NTXDESC; i++) {
    386 		if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES,
    387 		    BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) {
    388 			aprint_error_dev(self,
    389 			    "unable to create tx DMA map, error = %d\n", error);
    390 		}
    391 		sc->bce_cdata.bce_tx_chain[i] = NULL;
    392 	}
    393 
    394 	/* Create the receive buffer DMA maps. */
    395 	for (i = 0; i < BCE_NRXDESC; i++) {
    396 		if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1,
    397 		    MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) {
    398 			aprint_error_dev(self,
    399 			    "unable to create rx DMA map, error = %d\n", error);
    400 		}
    401 		sc->bce_cdata.bce_rx_chain[i] = NULL;
    402 	}
    403 
    404 	/* Set up ifnet structure */
    405 	ifp = &sc->ethercom.ec_if;
    406 	strcpy(ifp->if_xname, device_xname(self));
    407 	ifp->if_softc = sc;
    408 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
    409 	ifp->if_ioctl = bce_ioctl;
    410 	ifp->if_start = bce_start;
    411 	ifp->if_watchdog = bce_watchdog;
    412 	ifp->if_init = bce_init;
    413 	ifp->if_stop = bce_stop;
    414 	IFQ_SET_READY(&ifp->if_snd);
    415 
    416 	/* Initialize our media structures and probe the MII. */
    417 
    418 	sc->bce_mii.mii_ifp = ifp;
    419 	sc->bce_mii.mii_readreg = bce_mii_read;
    420 	sc->bce_mii.mii_writereg = bce_mii_write;
    421 	sc->bce_mii.mii_statchg = bce_statchg;
    422 
    423 	sc->ethercom.ec_mii = &sc->bce_mii;
    424 	ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange,
    425 	    ether_mediastatus);
    426 	mii_attach(sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY,
    427 	    MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE);
    428 	if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) {
    429 		ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
    430 		ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE);
    431 	} else
    432 		ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO);
    433 	/* get the phy */
    434 	sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle,
    435 	    BCE_MAGIC_PHY) & 0x1f;
    436 	/*
    437 	 * Enable activity led.
    438 	 * XXX This should be in a phy driver, but not currently.
    439 	 */
    440 	bce_mii_write(sc->bce_dev, 1, 26,	 /* MAGIC */
    441 	    bce_mii_read(sc->bce_dev, 1, 26) & 0x7fff);	 /* MAGIC */
    442 	/* enable traffic meter led mode */
    443 	bce_mii_write(sc->bce_dev, 1, 27,	 /* MAGIC */
    444 	    bce_mii_read(sc->bce_dev, 1, 27) | (1 << 6));	 /* MAGIC */
    445 
    446 	/* Attach the interface */
    447 	if_attach(ifp);
    448 	if_deferred_start_init(ifp, NULL);
    449 	sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle,
    450 	    BCE_MAGIC_ENET0);
    451 	sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle,
    452 	    BCE_MAGIC_ENET1);
    453 	sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle,
    454 	    BCE_MAGIC_ENET2);
    455 	sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle,
    456 	    BCE_MAGIC_ENET3);
    457 	sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle,
    458 	    BCE_MAGIC_ENET4);
    459 	sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle,
    460 	    BCE_MAGIC_ENET5);
    461 	aprint_normal_dev(self, "Ethernet address %s\n",
    462 	    ether_sprintf(sc->enaddr));
    463 	ether_ifattach(ifp, sc->enaddr);
    464 	rnd_attach_source(&sc->rnd_source, device_xname(self),
    465 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
    466 	callout_init(&sc->bce_timeout, 0);
    467 
    468 	if (pmf_device_register(self, NULL, bce_resume))
    469 		pmf_class_network_register(self, ifp);
    470 	else
    471 		aprint_error_dev(self, "couldn't establish power handler\n");
    472 }
    473 
    474 /* handle media, and ethernet requests */
    475 static int
    476 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data)
    477 {
    478 	int		s, error;
    479 
    480 	s = splnet();
    481 	error = ether_ioctl(ifp, cmd, data);
    482 	if (error == ENETRESET) {
    483 		/* change multicast list */
    484 		error = 0;
    485 	}
    486 
    487 	/* Try to get more packets going. */
    488 	bce_start(ifp);
    489 
    490 	splx(s);
    491 	return error;
    492 }
    493 
    494 /* Start packet transmission on the interface. */
    495 static void
    496 bce_start(struct ifnet *ifp)
    497 {
    498 	struct bce_softc *sc = ifp->if_softc;
    499 	struct mbuf    *m0;
    500 	bus_dmamap_t	dmamap;
    501 	int		txstart;
    502 	int		txsfree;
    503 	int		newpkts = 0;
    504 	int		error;
    505 
    506 	/*
    507 	 * do not start another if currently transmitting, and more
    508 	 * descriptors(tx slots) are needed for next packet.
    509 	 */
    510 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
    511 		return;
    512 
    513 	/* determine number of descriptors available */
    514 	if (sc->bce_txsnext >= sc->bce_txin)
    515 		txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext;
    516 	else
    517 		txsfree = sc->bce_txin - sc->bce_txsnext - 1;
    518 
    519 	/*
    520 	 * Loop through the send queue, setting up transmit descriptors
    521 	 * until we drain the queue, or use up all available transmit
    522 	 * descriptors.
    523 	 */
    524 	while (txsfree > 0) {
    525 		int		seg;
    526 
    527 		/* Grab a packet off the queue. */
    528 		IFQ_POLL(&ifp->if_snd, m0);
    529 		if (m0 == NULL)
    530 			break;
    531 
    532 		/* get the transmit slot dma map */
    533 		dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext];
    534 
    535 		/*
    536 		 * Load the DMA map.  If this fails, the packet either
    537 		 * didn't fit in the alloted number of segments, or we
    538 		 * were short on resources. If the packet will not fit,
    539 		 * it will be dropped. If short on resources, it will
    540 		 * be tried again later.
    541 		 */
    542 		error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0,
    543 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
    544 		if (error == EFBIG) {
    545 			aprint_error_dev(sc->bce_dev,
    546 			    "Tx packet consumes too many DMA segments, "
    547 			    "dropping...\n");
    548 			IFQ_DEQUEUE(&ifp->if_snd, m0);
    549 			m_freem(m0);
    550 			ifp->if_oerrors++;
    551 			continue;
    552 		} else if (error) {
    553 			/* short on resources, come back later */
    554 			aprint_error_dev(sc->bce_dev,
    555 			    "unable to load Tx buffer, error = %d\n",
    556 			    error);
    557 			break;
    558 		}
    559 		/* If not enough descriptors available, try again later */
    560 		if (dmamap->dm_nsegs > txsfree) {
    561 			ifp->if_flags |= IFF_OACTIVE;
    562 			bus_dmamap_unload(sc->bce_dmatag, dmamap);
    563 			break;
    564 		}
    565 		/* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
    566 
    567 		/* So take it off the queue */
    568 		IFQ_DEQUEUE(&ifp->if_snd, m0);
    569 
    570 		/* save the pointer so it can be freed later */
    571 		sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0;
    572 
    573 		/* Sync the data DMA map. */
    574 		bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize,
    575 				BUS_DMASYNC_PREWRITE);
    576 
    577 		/* Initialize the transmit descriptor(s). */
    578 		txstart = sc->bce_txsnext;
    579 		for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
    580 			uint32_t ctrl;
    581 
    582 			ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK;
    583 			if (seg == 0)
    584 				ctrl |= CTRL_SOF;
    585 			if (seg == dmamap->dm_nsegs - 1)
    586 				ctrl |= CTRL_EOF;
    587 			if (sc->bce_txsnext == BCE_NTXDESC - 1)
    588 				ctrl |= CTRL_EOT;
    589 			ctrl |= CTRL_IOC;
    590 			sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl);
    591 			sc->bce_tx_ring[sc->bce_txsnext].addr =
    592 			    htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000);	/* MAGIC */
    593 			if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1)
    594 				sc->bce_txsnext = 0;
    595 			else
    596 				sc->bce_txsnext++;
    597 			txsfree--;
    598 		}
    599 		/* sync descriptors being used */
    600 		if ( sc->bce_txsnext > txstart ) {
    601 			bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map,
    602 			    PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart,
    603 			    sizeof(struct bce_dma_slot) * dmamap->dm_nsegs,
    604 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
    605 		} else {
    606 			bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map,
    607 			    PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart,
    608 			    sizeof(struct bce_dma_slot) *
    609 			    (BCE_NTXDESC - txstart),
    610 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
    611 			if ( sc->bce_txsnext != 0 ) {
    612 				bus_dmamap_sync(sc->bce_dmatag,
    613 				    sc->bce_ring_map, PAGE_SIZE,
    614 				    sc->bce_txsnext *
    615 				    sizeof(struct bce_dma_slot),
    616 				    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
    617 			}
    618 		}
    619 
    620 		/* Give the packet to the chip. */
    621 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR,
    622 		    sc->bce_txsnext * sizeof(struct bce_dma_slot));
    623 
    624 		newpkts++;
    625 
    626 		/* Pass the packet to any BPF listeners. */
    627 		bpf_mtap(ifp, m0);
    628 	}
    629 	if (txsfree == 0) {
    630 		/* No more slots left; notify upper layer. */
    631 		ifp->if_flags |= IFF_OACTIVE;
    632 	}
    633 	if (newpkts) {
    634 		/* Set a watchdog timer in case the chip flakes out. */
    635 		ifp->if_timer = 5;
    636 	}
    637 }
    638 
    639 /* Watchdog timer handler. */
    640 static void
    641 bce_watchdog(struct ifnet *ifp)
    642 {
    643 	struct bce_softc *sc = ifp->if_softc;
    644 
    645 	aprint_error_dev(sc->bce_dev, "device timeout\n");
    646 	ifp->if_oerrors++;
    647 
    648 	(void) bce_init(ifp);
    649 
    650 	/* Try to get more packets going. */
    651 	bce_start(ifp);
    652 }
    653 
    654 int
    655 bce_intr(void *xsc)
    656 {
    657 	struct bce_softc *sc;
    658 	struct ifnet   *ifp;
    659 	uint32_t	intstatus;
    660 	int		wantinit;
    661 	int		handled = 0;
    662 
    663 	sc = xsc;
    664 	ifp = &sc->ethercom.ec_if;
    665 
    666 	for (wantinit = 0; wantinit == 0;) {
    667 		intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
    668 		    BCE_INT_STS);
    669 
    670 		/* ignore if not ours, or unsolicited interrupts */
    671 		intstatus &= sc->bce_intmask;
    672 		if (intstatus == 0)
    673 			break;
    674 
    675 		handled = 1;
    676 
    677 		/* Ack interrupt */
    678 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS,
    679 		    intstatus);
    680 
    681 		/* Receive interrupts. */
    682 		if (intstatus & I_RI)
    683 			bce_rxintr(sc);
    684 		/* Transmit interrupts. */
    685 		if (intstatus & I_XI)
    686 			bce_txintr(sc);
    687 		/* Error interrupts */
    688 		if (intstatus & ~(I_RI | I_XI)) {
    689 			const char *msg = NULL;
    690 			if (intstatus & I_XU)
    691 				msg = "transmit fifo underflow";
    692 			if (intstatus & I_RO) {
    693 				msg = "receive fifo overflow";
    694 				ifp->if_ierrors++;
    695 			}
    696 			if (intstatus & I_RU)
    697 				msg = "receive descriptor underflow";
    698 			if (intstatus & I_DE)
    699 				msg = "descriptor protocol error";
    700 			if (intstatus & I_PD)
    701 				msg = "data error";
    702 			if (intstatus & I_PC)
    703 				msg = "descriptor error";
    704 			if (intstatus & I_TO)
    705 				msg = "general purpose timeout";
    706 			if (msg != NULL)
    707 				aprint_error_dev(sc->bce_dev, "%s\n", msg);
    708 			wantinit = 1;
    709 		}
    710 	}
    711 
    712 	if (handled) {
    713 		if (wantinit)
    714 			bce_init(ifp);
    715 		rnd_add_uint32(&sc->rnd_source, intstatus);
    716 		/* Try to get more packets going. */
    717 		if_schedule_deferred_start(ifp);
    718 	}
    719 	return (handled);
    720 }
    721 
    722 /* Receive interrupt handler */
    723 void
    724 bce_rxintr(struct bce_softc *sc)
    725 {
    726 	struct ifnet   *ifp = &sc->ethercom.ec_if;
    727 	struct rx_pph  *pph;
    728 	struct mbuf    *m;
    729 	int		curr;
    730 	int		len;
    731 	int		i;
    732 
    733 	/* get pointer to active receive slot */
    734 	curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS)
    735 	    & RS_CD_MASK;
    736 	curr = curr / sizeof(struct bce_dma_slot);
    737 	if (curr >= BCE_NRXDESC)
    738 		curr = BCE_NRXDESC - 1;
    739 
    740 	/* process packets up to but not current packet being worked on */
    741 	for (i = sc->bce_rxin; i != curr;
    742 	    i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) {
    743 		/* complete any post dma memory ops on packet */
    744 		bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0,
    745 		    sc->bce_cdata.bce_rx_map[i]->dm_mapsize,
    746 		    BUS_DMASYNC_POSTREAD);
    747 
    748 		/*
    749 		 * If the packet had an error, simply recycle the buffer,
    750 		 * resetting the len, and flags.
    751 		 */
    752 		pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *);
    753 		if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) {
    754 			ifp->if_ierrors++;
    755 			pph->len = 0;
    756 			pph->flags = 0;
    757 			continue;
    758 		}
    759 		/* receive the packet */
    760 		len = pph->len;
    761 		if (len == 0)
    762 			continue;	/* no packet if empty */
    763 		pph->len = 0;
    764 		pph->flags = 0;
    765 		/* bump past pre header to packet */
    766 		sc->bce_cdata.bce_rx_chain[i]->m_data += 30;	/* MAGIC */
    767 
    768 		/*
    769 		 * The chip includes the CRC with every packet.  Trim
    770 		 * it off here.
    771 		 */
    772 		len -= ETHER_CRC_LEN;
    773 
    774 		/*
    775 		 * If the packet is small enough to fit in a
    776 		 * single header mbuf, allocate one and copy
    777 		 * the data into it.  This greatly reduces
    778 		 * memory consumption when receiving lots
    779 		 * of small packets.
    780 		 *
    781 		 * Otherwise, add a new buffer to the receive
    782 		 * chain.  If this fails, drop the packet and
    783 		 * recycle the old buffer.
    784 		 */
    785 		if (len <= (MHLEN - 2)) {
    786 			MGETHDR(m, M_DONTWAIT, MT_DATA);
    787 			if (m == NULL)
    788 				goto dropit;
    789 			m->m_data += 2;
    790 			memcpy(mtod(m, void *),
    791 			 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len);
    792 			sc->bce_cdata.bce_rx_chain[i]->m_data -= 30;	/* MAGIC */
    793 		} else {
    794 			m = sc->bce_cdata.bce_rx_chain[i];
    795 			if (bce_add_rxbuf(sc, i) != 0) {
    796 		dropit:
    797 				ifp->if_ierrors++;
    798 				/* continue to use old buffer */
    799 				sc->bce_cdata.bce_rx_chain[i]->m_data -= 30;
    800 				bus_dmamap_sync(sc->bce_dmatag,
    801 				    sc->bce_cdata.bce_rx_map[i], 0,
    802 				    sc->bce_cdata.bce_rx_map[i]->dm_mapsize,
    803 				    BUS_DMASYNC_PREREAD);
    804 				continue;
    805 			}
    806 		}
    807 
    808 		m_set_rcvif(m, ifp);
    809 		m->m_pkthdr.len = m->m_len = len;
    810 
    811 		/* Pass it on. */
    812 		if_percpuq_enqueue(ifp->if_percpuq, m);
    813 
    814 		/* re-check current in case it changed */
    815 		curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
    816 		    BCE_DMA_RXSTATUS) & RS_CD_MASK) /
    817 		    sizeof(struct bce_dma_slot);
    818 		if (curr >= BCE_NRXDESC)
    819 			curr = BCE_NRXDESC - 1;
    820 	}
    821 	sc->bce_rxin = curr;
    822 }
    823 
    824 /* Transmit interrupt handler */
    825 void
    826 bce_txintr(struct bce_softc *sc)
    827 {
    828 	struct ifnet   *ifp = &sc->ethercom.ec_if;
    829 	int		curr;
    830 	int		i;
    831 
    832 	ifp->if_flags &= ~IFF_OACTIVE;
    833 
    834 	/*
    835 	 * Go through the Tx list and free mbufs for those
    836 	 * frames which have been transmitted.
    837 	 */
    838 	curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) &
    839 		RS_CD_MASK;
    840 	curr = curr / sizeof(struct bce_dma_slot);
    841 	if (curr >= BCE_NTXDESC)
    842 		curr = BCE_NTXDESC - 1;
    843 	for (i = sc->bce_txin; i != curr;
    844 	    i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) {
    845 		/* do any post dma memory ops on transmit data */
    846 		if (sc->bce_cdata.bce_tx_chain[i] == NULL)
    847 			continue;
    848 		bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0,
    849 		    sc->bce_cdata.bce_tx_map[i]->dm_mapsize,
    850 		    BUS_DMASYNC_POSTWRITE);
    851 		bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]);
    852 		m_freem(sc->bce_cdata.bce_tx_chain[i]);
    853 		sc->bce_cdata.bce_tx_chain[i] = NULL;
    854 		ifp->if_opackets++;
    855 	}
    856 	sc->bce_txin = curr;
    857 
    858 	/*
    859 	 * If there are no more pending transmissions, cancel the watchdog
    860 	 * timer
    861 	 */
    862 	if (sc->bce_txsnext == sc->bce_txin)
    863 		ifp->if_timer = 0;
    864 }
    865 
    866 /* initialize the interface */
    867 static int
    868 bce_init(struct ifnet *ifp)
    869 {
    870 	struct bce_softc *sc = ifp->if_softc;
    871 	uint32_t	reg_win;
    872 	int		error;
    873 	int		i;
    874 
    875 	/* Cancel any pending I/O. */
    876 	bce_stop(ifp, 0);
    877 
    878 	/* enable pci inerrupts, bursts, and prefetch */
    879 
    880 	/* remap the pci registers to the Sonics config registers */
    881 
    882 	/* save the current map, so it can be restored */
    883 	reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag,
    884 	    BCE_REG_WIN);
    885 
    886 	/* set register window to Sonics registers */
    887 	pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN,
    888 	    BCE_SONICS_WIN);
    889 
    890 	/* enable SB to PCI interrupt */
    891 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC,
    892 	    bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) |
    893 	    SBIV_ENET0);
    894 
    895 	/* enable prefetch and bursts for sonics-to-pci translation 2 */
    896 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2,
    897 	    bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) |
    898 	    SBTOPCI_PREF | SBTOPCI_BURST);
    899 
    900 	/* restore to ethernet register space */
    901 	pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN,
    902 	    reg_win);
    903 
    904 	/* Reset the chip to a known state. */
    905 	bce_reset(sc);
    906 
    907 	/* Initialize transmit descriptors */
    908 	memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot));
    909 	sc->bce_txsnext = 0;
    910 	sc->bce_txin = 0;
    911 
    912 	/* enable crc32 generation */
    913 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL,
    914 	    bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) |
    915 	    BCE_EMC_CG);
    916 
    917 	/* setup DMA interrupt control */
    918 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24);	/* MAGIC */
    919 
    920 	/* setup packet filter */
    921 	bce_set_filter(ifp);
    922 
    923 	/* set max frame length, account for possible vlan tag */
    924 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX,
    925 	    ETHER_MAX_LEN + 32);
    926 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX,
    927 	    ETHER_MAX_LEN + 32);
    928 
    929 	/* set tx watermark */
    930 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56);
    931 
    932 	/* enable transmit */
    933 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE);
    934 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR,
    935 	    sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000);	/* MAGIC */
    936 
    937 	/*
    938 	 * Give the receive ring to the chip, and
    939 	 * start the receive DMA engine.
    940 	 */
    941 	sc->bce_rxin = 0;
    942 
    943 	/* clear the rx descriptor ring */
    944 	memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot));
    945 	/* enable receive */
    946 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL,
    947 	    30 << 1 | 1);	/* MAGIC */
    948 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR,
    949 	    sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000);		/* MAGIC */
    950 
    951 	/* Initalize receive descriptors */
    952 	for (i = 0; i < BCE_NRXDESC; i++) {
    953 		if (sc->bce_cdata.bce_rx_chain[i] == NULL) {
    954 			if ((error = bce_add_rxbuf(sc, i)) != 0) {
    955 				aprint_error_dev(sc->bce_dev,
    956 				    "unable to allocate or map rx(%d) "
    957 				    "mbuf, error = %d\n", i, error);
    958 				bce_rxdrain(sc);
    959 				return (error);
    960 			}
    961 		} else
    962 			BCE_INIT_RXDESC(sc, i);
    963 	}
    964 
    965 	/* Enable interrupts */
    966 	sc->bce_intmask =
    967 	    I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO;
    968 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK,
    969 	    sc->bce_intmask);
    970 
    971 	/* start the receive dma */
    972 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR,
    973 	    BCE_NRXDESC * sizeof(struct bce_dma_slot));
    974 
    975 	/* set media */
    976 	if ((error = ether_mediachange(ifp)) != 0)
    977 		return error;
    978 
    979 	/* turn on the ethernet mac */
    980 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL,
    981 	    bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
    982 	    BCE_ENET_CTL) | EC_EE);
    983 
    984 	/* start timer */
    985 	callout_reset(&sc->bce_timeout, hz, bce_tick, sc);
    986 
    987 	/* mark as running, and no outputs active */
    988 	ifp->if_flags |= IFF_RUNNING;
    989 	ifp->if_flags &= ~IFF_OACTIVE;
    990 
    991 	return 0;
    992 }
    993 
    994 /* add a mac address to packet filter */
    995 void
    996 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx)
    997 {
    998 	int		i;
    999 	uint32_t	rval;
   1000 
   1001 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW,
   1002 	    mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]);
   1003 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI,
   1004 	    mac[0] << 8 | mac[1] | 0x10000);	/* MAGIC */
   1005 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL,
   1006 	    idx << 16 | 8);	/* MAGIC */
   1007 	/* wait for write to complete */
   1008 	for (i = 0; i < 100; i++) {
   1009 		rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1010 		    BCE_FILT_CTL);
   1011 		if (!(rval & 0x80000000))	/* MAGIC */
   1012 			break;
   1013 		delay(10);
   1014 	}
   1015 	if (i == 100) {
   1016 		aprint_error_dev(sc->bce_dev,
   1017 		    "timed out writing pkt filter ctl\n");
   1018 	}
   1019 }
   1020 
   1021 /* Add a receive buffer to the indiciated descriptor. */
   1022 static int
   1023 bce_add_rxbuf(struct bce_softc *sc, int idx)
   1024 {
   1025 	struct mbuf    *m;
   1026 	int		error;
   1027 
   1028 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   1029 	if (m == NULL)
   1030 		return (ENOBUFS);
   1031 
   1032 	MCLGET(m, M_DONTWAIT);
   1033 	if ((m->m_flags & M_EXT) == 0) {
   1034 		m_freem(m);
   1035 		return (ENOBUFS);
   1036 	}
   1037 	if (sc->bce_cdata.bce_rx_chain[idx] != NULL)
   1038 		bus_dmamap_unload(sc->bce_dmatag,
   1039 		    sc->bce_cdata.bce_rx_map[idx]);
   1040 
   1041 	sc->bce_cdata.bce_rx_chain[idx] = m;
   1042 
   1043 	error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx],
   1044 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
   1045 	    BUS_DMA_READ | BUS_DMA_NOWAIT);
   1046 	if (error)
   1047 		return (error);
   1048 
   1049 	bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0,
   1050 	    sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD);
   1051 
   1052 	BCE_INIT_RXDESC(sc, idx);
   1053 
   1054 	return (0);
   1055 
   1056 }
   1057 
   1058 /* Drain the receive queue. */
   1059 static void
   1060 bce_rxdrain(struct bce_softc *sc)
   1061 {
   1062 	int		i;
   1063 
   1064 	for (i = 0; i < BCE_NRXDESC; i++) {
   1065 		if (sc->bce_cdata.bce_rx_chain[i] != NULL) {
   1066 			bus_dmamap_unload(sc->bce_dmatag,
   1067 			    sc->bce_cdata.bce_rx_map[i]);
   1068 			m_freem(sc->bce_cdata.bce_rx_chain[i]);
   1069 			sc->bce_cdata.bce_rx_chain[i] = NULL;
   1070 		}
   1071 	}
   1072 }
   1073 
   1074 /* Stop transmission on the interface */
   1075 static void
   1076 bce_stop(struct ifnet *ifp, int disable)
   1077 {
   1078 	struct bce_softc *sc = ifp->if_softc;
   1079 	int		i;
   1080 	uint32_t	val;
   1081 
   1082 	/* Stop the 1 second timer */
   1083 	callout_stop(&sc->bce_timeout);
   1084 
   1085 	/* Down the MII. */
   1086 	mii_down(&sc->bce_mii);
   1087 
   1088 	/* Disable interrupts. */
   1089 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0);
   1090 	sc->bce_intmask = 0;
   1091 	delay(10);
   1092 
   1093 	/* Disable emac */
   1094 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED);
   1095 	for (i = 0; i < 200; i++) {
   1096 		val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1097 		    BCE_ENET_CTL);
   1098 		if (!(val & EC_ED))
   1099 			break;
   1100 		delay(10);
   1101 	}
   1102 
   1103 	/* Stop the DMA */
   1104 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0);
   1105 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0);
   1106 	delay(10);
   1107 
   1108 	/* Release any queued transmit buffers. */
   1109 	for (i = 0; i < BCE_NTXDESC; i++) {
   1110 		if (sc->bce_cdata.bce_tx_chain[i] != NULL) {
   1111 			bus_dmamap_unload(sc->bce_dmatag,
   1112 			    sc->bce_cdata.bce_tx_map[i]);
   1113 			m_freem(sc->bce_cdata.bce_tx_chain[i]);
   1114 			sc->bce_cdata.bce_tx_chain[i] = NULL;
   1115 		}
   1116 	}
   1117 
   1118 	/* Mark the interface down and cancel the watchdog timer. */
   1119 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   1120 	ifp->if_timer = 0;
   1121 
   1122 	/* drain receive queue */
   1123 	if (disable)
   1124 		bce_rxdrain(sc);
   1125 }
   1126 
   1127 /* reset the chip */
   1128 static void
   1129 bce_reset(struct bce_softc *sc)
   1130 {
   1131 	uint32_t	val;
   1132 	uint32_t	sbval;
   1133 	int		i;
   1134 
   1135 	/* if SB core is up */
   1136 	sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1137 	    BCE_SBTMSTATELOW);
   1138 	if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) {
   1139 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL,
   1140 		    0);
   1141 
   1142 		/* disable emac */
   1143 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL,
   1144 		    EC_ED);
   1145 		for (i = 0; i < 200; i++) {
   1146 			val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1147 			    BCE_ENET_CTL);
   1148 			if (!(val & EC_ED))
   1149 				break;
   1150 			delay(10);
   1151 		}
   1152 		if (i == 200) {
   1153 			aprint_error_dev(sc->bce_dev,
   1154 			    "timed out disabling ethernet mac\n");
   1155 		}
   1156 
   1157 		/* reset the dma engines */
   1158 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0);
   1159 		val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS);
   1160 		/* if error on receive, wait to go idle */
   1161 		if (val & RS_ERROR) {
   1162 			for (i = 0; i < 100; i++) {
   1163 				val = bus_space_read_4(sc->bce_btag,
   1164 				    sc->bce_bhandle, BCE_DMA_RXSTATUS);
   1165 				if (val & RS_DMA_IDLE)
   1166 					break;
   1167 				delay(10);
   1168 			}
   1169 			if (i == 100) {
   1170 				aprint_error_dev(sc->bce_dev,
   1171 				    "receive dma did not go idle after"
   1172 				    " error\n");
   1173 			}
   1174 		}
   1175 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
   1176 		   BCE_DMA_RXSTATUS, 0);
   1177 
   1178 		/* reset ethernet mac */
   1179 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL,
   1180 		    EC_ES);
   1181 		for (i = 0; i < 200; i++) {
   1182 			val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1183 			    BCE_ENET_CTL);
   1184 			if (!(val & EC_ES))
   1185 				break;
   1186 			delay(10);
   1187 		}
   1188 		if (i == 200) {
   1189 			aprint_error_dev(sc->bce_dev,
   1190 			    "timed out resetting ethernet mac\n");
   1191 		}
   1192 	} else {
   1193 		uint32_t reg_win;
   1194 
   1195 		/* remap the pci registers to the Sonics config registers */
   1196 
   1197 		/* save the current map, so it can be restored */
   1198 		reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag,
   1199 		    BCE_REG_WIN);
   1200 		/* set register window to Sonics registers */
   1201 		pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag,
   1202 		    BCE_REG_WIN, BCE_SONICS_WIN);
   1203 
   1204 		/* enable SB to PCI interrupt */
   1205 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC,
   1206 		    bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1207 			BCE_SBINTVEC) |
   1208 		    SBIV_ENET0);
   1209 
   1210 		/* enable prefetch and bursts for sonics-to-pci translation 2 */
   1211 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2,
   1212 		    bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1213 			BCE_SPCI_TR2) |
   1214 		    SBTOPCI_PREF | SBTOPCI_BURST);
   1215 
   1216 		/* restore to ethernet register space */
   1217 		pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN,
   1218 		    reg_win);
   1219 	}
   1220 
   1221 	/* disable SB core if not in reset */
   1222 	if (!(sbval & SBTML_RESET)) {
   1223 
   1224 		/* set the reject bit */
   1225 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
   1226 		    BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK);
   1227 		for (i = 0; i < 200; i++) {
   1228 			val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1229 			    BCE_SBTMSTATELOW);
   1230 			if (val & SBTML_REJ)
   1231 				break;
   1232 			delay(1);
   1233 		}
   1234 		if (i == 200) {
   1235 			aprint_error_dev(sc->bce_dev,
   1236 			    "while resetting core, reject did not set\n");
   1237 		}
   1238 		/* wait until busy is clear */
   1239 		for (i = 0; i < 200; i++) {
   1240 			val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1241 			    BCE_SBTMSTATEHI);
   1242 			if (!(val & 0x4))
   1243 				break;
   1244 			delay(1);
   1245 		}
   1246 		if (i == 200) {
   1247 			aprint_error_dev(sc->bce_dev,
   1248 			    "while resetting core, busy did not clear\n");
   1249 		}
   1250 		/* set reset and reject while enabling the clocks */
   1251 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
   1252 		    BCE_SBTMSTATELOW,
   1253 		    SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET);
   1254 		val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1255 		    BCE_SBTMSTATELOW);
   1256 		delay(10);
   1257 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
   1258 		    BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET);
   1259 		delay(1);
   1260 	}
   1261 	/* enable clock */
   1262 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW,
   1263 	    SBTML_FGC | SBTML_CLK | SBTML_RESET);
   1264 	val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
   1265 	delay(1);
   1266 
   1267 	/* clear any error bits that may be on */
   1268 	val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI);
   1269 	if (val & 1)
   1270 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI,
   1271 		    0);
   1272 	val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE);
   1273 	if (val & SBIM_MAGIC_ERRORBITS)
   1274 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE,
   1275 		    val & ~SBIM_MAGIC_ERRORBITS);
   1276 
   1277 	/* clear reset and allow it to propagate throughout the core */
   1278 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW,
   1279 	    SBTML_FGC | SBTML_CLK);
   1280 	val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
   1281 	delay(1);
   1282 
   1283 	/* leave clock enabled */
   1284 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW,
   1285 	    SBTML_CLK);
   1286 	val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
   1287 	delay(1);
   1288 
   1289 	/* initialize MDC preamble, frequency */
   1290 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d);	/* MAGIC */
   1291 
   1292 	/* enable phy, differs for internal, and external */
   1293 	val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL);
   1294 	if (!(val & BCE_DC_IP)) {
   1295 		/* select external phy */
   1296 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP);
   1297 	} else if (val & BCE_DC_ER) {	/* internal, clear reset bit if on */
   1298 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL,
   1299 		    val & ~BCE_DC_ER);
   1300 		delay(100);
   1301 	}
   1302 }
   1303 
   1304 /* Set up the receive filter. */
   1305 void
   1306 bce_set_filter(struct ifnet *ifp)
   1307 {
   1308 	struct bce_softc *sc = ifp->if_softc;
   1309 
   1310 	if (ifp->if_flags & IFF_PROMISC) {
   1311 		ifp->if_flags |= IFF_ALLMULTI;
   1312 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL,
   1313 		    bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL)
   1314 		    | ERC_PE);
   1315 	} else {
   1316 		ifp->if_flags &= ~IFF_ALLMULTI;
   1317 
   1318 		/* turn off promiscuous */
   1319 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL,
   1320 		    bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1321 		    BCE_RX_CTL) & ~ERC_PE);
   1322 
   1323 		/* enable/disable broadcast */
   1324 		if (ifp->if_flags & IFF_BROADCAST)
   1325 			bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
   1326 			    BCE_RX_CTL, bus_space_read_4(sc->bce_btag,
   1327 			    sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB);
   1328 		else
   1329 			bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
   1330 			    BCE_RX_CTL, bus_space_read_4(sc->bce_btag,
   1331 			    sc->bce_bhandle, BCE_RX_CTL) | ERC_DB);
   1332 
   1333 		/* disable the filter */
   1334 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL,
   1335 		    0);
   1336 
   1337 		/* add our own address */
   1338 		bce_add_mac(sc, sc->enaddr, 0);
   1339 
   1340 		/* for now accept all multicast */
   1341 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL,
   1342 		bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) |
   1343 		    ERC_AM);
   1344 		ifp->if_flags |= IFF_ALLMULTI;
   1345 
   1346 		/* enable the filter */
   1347 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL,
   1348 		    bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1349 		    BCE_FILT_CTL) | 1);
   1350 	}
   1351 }
   1352 
   1353 static bool
   1354 bce_resume(device_t self, const pmf_qual_t *qual)
   1355 {
   1356 	struct bce_softc *sc = device_private(self);
   1357 
   1358 	bce_reset(sc);
   1359 
   1360 	return true;
   1361 }
   1362 
   1363 /* Read a PHY register on the MII. */
   1364 int
   1365 bce_mii_read(device_t self, int phy, int reg)
   1366 {
   1367 	struct bce_softc *sc = device_private(self);
   1368 	int		i;
   1369 	uint32_t	val;
   1370 
   1371 	/* clear mii_int */
   1372 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR);
   1373 
   1374 	/* Read the PHY register */
   1375 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM,
   1376 	    (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) |	/* MAGIC */
   1377 	    (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg));	/* MAGIC */
   1378 
   1379 	for (i = 0; i < BCE_TIMEOUT; i++) {
   1380 		val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS);
   1381 		if (val & BCE_MIINTR)
   1382 			break;
   1383 		delay(10);
   1384 	}
   1385 	val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM);
   1386 	if (i == BCE_TIMEOUT) {
   1387 		aprint_error_dev(sc->bce_dev,
   1388 		    "PHY read timed out reading phy %d, reg %d, val = "
   1389 		    "0x%08x\n", phy, reg, val);
   1390 		return (0);
   1391 	}
   1392 	return (val & BCE_MICOMM_DATA);
   1393 }
   1394 
   1395 /* Write a PHY register on the MII */
   1396 void
   1397 bce_mii_write(device_t self, int phy, int reg, int val)
   1398 {
   1399 	struct bce_softc *sc = device_private(self);
   1400 	int		i;
   1401 	uint32_t	rval;
   1402 
   1403 	/* clear mii_int */
   1404 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS,
   1405 	    BCE_MIINTR);
   1406 
   1407 	/* Write the PHY register */
   1408 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM,
   1409 	    (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) |	/* MAGIC */
   1410 	    (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) |	/* MAGIC */
   1411 	    BCE_MIPHY(phy) | BCE_MIREG(reg));
   1412 
   1413 	/* wait for write to complete */
   1414 	for (i = 0; i < BCE_TIMEOUT; i++) {
   1415 		rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
   1416 		    BCE_MI_STS);
   1417 		if (rval & BCE_MIINTR)
   1418 			break;
   1419 		delay(10);
   1420 	}
   1421 	rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM);
   1422 	if (i == BCE_TIMEOUT) {
   1423 		aprint_error_dev(sc->bce_dev,
   1424 		    "PHY timed out writing phy %d, reg %d, val = 0x%08x\n", phy,
   1425 		    reg, val);
   1426 	}
   1427 }
   1428 
   1429 /* sync hardware duplex mode to software state */
   1430 void
   1431 bce_statchg(struct ifnet *ifp)
   1432 {
   1433 	struct bce_softc *sc = ifp->if_softc;
   1434 	uint32_t	reg;
   1435 
   1436 	/* if needed, change register to match duplex mode */
   1437 	reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL);
   1438 	if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD))
   1439 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL,
   1440 		    reg | EXC_FD);
   1441 	else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD)
   1442 		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL,
   1443 		    reg & ~EXC_FD);
   1444 
   1445 	/*
   1446 	 * Enable activity led.
   1447 	 * XXX This should be in a phy driver, but not currently.
   1448 	 */
   1449 	bce_mii_write(sc->bce_dev, 1, 26,	/* MAGIC */
   1450 	    bce_mii_read(sc->bce_dev, 1, 26) & 0x7fff);	/* MAGIC */
   1451 	/* enable traffic meter led mode */
   1452 	bce_mii_write(sc->bce_dev, 1, 26,	/* MAGIC */
   1453 	    bce_mii_read(sc->bce_dev, 1, 27) | (1 << 6));	/* MAGIC */
   1454 }
   1455 
   1456 /* One second timer, checks link status */
   1457 static void
   1458 bce_tick(void *v)
   1459 {
   1460 	struct bce_softc *sc = v;
   1461 
   1462 	/* Tick the MII. */
   1463 	mii_tick(&sc->bce_mii);
   1464 
   1465 	callout_reset(&sc->bce_timeout, hz, bce_tick, sc);
   1466 }
   1467