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if_pcn.c revision 1.59
      1 /*	$NetBSD: if_pcn.c,v 1.58 2014/08/10 16:44:36 tls Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 /*
     39  * Device driver for the AMD PCnet-PCI series of Ethernet
     40  * chips:
     41  *
     42  *	* Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
     43  *	  Local Bus
     44  *
     45  *	* Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
     46  *	  for PCI Local Bus
     47  *
     48  *	* Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
     49  *	  Ethernet Controller for PCI Local Bus
     50  *
     51  *	* Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
     52  *	  with OnNow Support
     53  *
     54  *	* Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
     55  *	  Ethernet Controller with Integrated PHY
     56  *
     57  * This also supports the virtual PCnet-PCI Ethernet interface found
     58  * in VMware.
     59  *
     60  * TODO:
     61  *
     62  *	* Split this into bus-specific and bus-independent portions.
     63  *	  The core could also be used for the ILACC (Am79900) 32-bit
     64  *	  Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE).
     65  */
     66 
     67 #include <sys/cdefs.h>
     68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.58 2014/08/10 16:44:36 tls Exp $");
     69 
     70 #include <sys/param.h>
     71 #include <sys/systm.h>
     72 #include <sys/callout.h>
     73 #include <sys/mbuf.h>
     74 #include <sys/malloc.h>
     75 #include <sys/kernel.h>
     76 #include <sys/socket.h>
     77 #include <sys/ioctl.h>
     78 #include <sys/errno.h>
     79 #include <sys/device.h>
     80 #include <sys/queue.h>
     81 
     82 #include <sys/rndsource.h>
     83 
     84 #include <net/if.h>
     85 #include <net/if_dl.h>
     86 #include <net/if_media.h>
     87 #include <net/if_ether.h>
     88 
     89 #include <net/bpf.h>
     90 
     91 #include <sys/bus.h>
     92 #include <sys/intr.h>
     93 #include <machine/endian.h>
     94 
     95 #include <dev/mii/mii.h>
     96 #include <dev/mii/miivar.h>
     97 
     98 #include <dev/ic/am79900reg.h>
     99 #include <dev/ic/lancereg.h>
    100 
    101 #include <dev/pci/pcireg.h>
    102 #include <dev/pci/pcivar.h>
    103 #include <dev/pci/pcidevs.h>
    104 
    105 #include <dev/pci/if_pcnreg.h>
    106 
    107 /*
    108  * Transmit descriptor list size.  This is arbitrary, but allocate
    109  * enough descriptors for 128 pending transmissions, and 4 segments
    110  * per packet.  This MUST work out to a power of 2.
    111  *
    112  * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL!
    113  *
    114  * So we play a little trick here.  We give each packet up to 16
    115  * DMA segments, but only allocate the max of 512 descriptors.  The
    116  * transmit logic can deal with this, we just are hoping to sneak by.
    117  */
    118 #define	PCN_NTXSEGS		16
    119 #define	PCN_NTXSEGS_VMWARE	8	/* bug in VMware's emulation */
    120 
    121 #define	PCN_TXQUEUELEN		128
    122 #define	PCN_TXQUEUELEN_MASK	(PCN_TXQUEUELEN - 1)
    123 #define	PCN_NTXDESC		512
    124 #define	PCN_NTXDESC_MASK	(PCN_NTXDESC - 1)
    125 #define	PCN_NEXTTX(x)		(((x) + 1) & PCN_NTXDESC_MASK)
    126 #define	PCN_NEXTTXS(x)		(((x) + 1) & PCN_TXQUEUELEN_MASK)
    127 
    128 /* Tx interrupt every N + 1 packets. */
    129 #define	PCN_TXINTR_MASK		7
    130 
    131 /*
    132  * Receive descriptor list size.  We have one Rx buffer per incoming
    133  * packet, so this logic is a little simpler.
    134  */
    135 #define	PCN_NRXDESC		128
    136 #define	PCN_NRXDESC_MASK	(PCN_NRXDESC - 1)
    137 #define	PCN_NEXTRX(x)		(((x) + 1) & PCN_NRXDESC_MASK)
    138 
    139 /*
    140  * Control structures are DMA'd to the PCnet chip.  We allocate them in
    141  * a single clump that maps to a single DMA segment to make several things
    142  * easier.
    143  */
    144 struct pcn_control_data {
    145 	/* The transmit descriptors. */
    146 	struct letmd pcd_txdescs[PCN_NTXDESC];
    147 
    148 	/* The receive descriptors. */
    149 	struct lermd pcd_rxdescs[PCN_NRXDESC];
    150 
    151 	/* The init block. */
    152 	struct leinit pcd_initblock;
    153 };
    154 
    155 #define	PCN_CDOFF(x)	offsetof(struct pcn_control_data, x)
    156 #define	PCN_CDTXOFF(x)	PCN_CDOFF(pcd_txdescs[(x)])
    157 #define	PCN_CDRXOFF(x)	PCN_CDOFF(pcd_rxdescs[(x)])
    158 #define	PCN_CDINITOFF	PCN_CDOFF(pcd_initblock)
    159 
    160 /*
    161  * Software state for transmit jobs.
    162  */
    163 struct pcn_txsoft {
    164 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
    165 	bus_dmamap_t txs_dmamap;	/* our DMA map */
    166 	int txs_firstdesc;		/* first descriptor in packet */
    167 	int txs_lastdesc;		/* last descriptor in packet */
    168 };
    169 
    170 /*
    171  * Software state for receive jobs.
    172  */
    173 struct pcn_rxsoft {
    174 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
    175 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
    176 };
    177 
    178 /*
    179  * Description of Rx FIFO watermarks for various revisions.
    180  */
    181 static const char * const pcn_79c970_rcvfw[] = {
    182 	"16 bytes",
    183 	"64 bytes",
    184 	"128 bytes",
    185 	NULL,
    186 };
    187 
    188 static const char * const pcn_79c971_rcvfw[] = {
    189 	"16 bytes",
    190 	"64 bytes",
    191 	"112 bytes",
    192 	NULL,
    193 };
    194 
    195 /*
    196  * Description of Tx start points for various revisions.
    197  */
    198 static const char * const pcn_79c970_xmtsp[] = {
    199 	"8 bytes",
    200 	"64 bytes",
    201 	"128 bytes",
    202 	"248 bytes",
    203 };
    204 
    205 static const char * const pcn_79c971_xmtsp[] = {
    206 	"20 bytes",
    207 	"64 bytes",
    208 	"128 bytes",
    209 	"248 bytes",
    210 };
    211 
    212 static const char * const pcn_79c971_xmtsp_sram[] = {
    213 	"44 bytes",
    214 	"64 bytes",
    215 	"128 bytes",
    216 	"store-and-forward",
    217 };
    218 
    219 /*
    220  * Description of Tx FIFO watermarks for various revisions.
    221  */
    222 static const char * const pcn_79c970_xmtfw[] = {
    223 	"16 bytes",
    224 	"64 bytes",
    225 	"128 bytes",
    226 	NULL,
    227 };
    228 
    229 static const char * const pcn_79c971_xmtfw[] = {
    230 	"16 bytes",
    231 	"64 bytes",
    232 	"108 bytes",
    233 	NULL,
    234 };
    235 
    236 /*
    237  * Software state per device.
    238  */
    239 struct pcn_softc {
    240 	device_t sc_dev;		/* generic device information */
    241 	bus_space_tag_t sc_st;		/* bus space tag */
    242 	bus_space_handle_t sc_sh;	/* bus space handle */
    243 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
    244 	struct ethercom sc_ethercom;	/* Ethernet common data */
    245 
    246 	/* Points to our media routines, etc. */
    247 	const struct pcn_variant *sc_variant;
    248 
    249 	void *sc_ih;			/* interrupt cookie */
    250 
    251 	struct mii_data sc_mii;		/* MII/media information */
    252 
    253 	callout_t sc_tick_ch;		/* tick callout */
    254 
    255 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
    256 #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
    257 
    258 	/* Software state for transmit and receive descriptors. */
    259 	struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN];
    260 	struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC];
    261 
    262 	/* Control data structures */
    263 	struct pcn_control_data *sc_control_data;
    264 #define	sc_txdescs	sc_control_data->pcd_txdescs
    265 #define	sc_rxdescs	sc_control_data->pcd_rxdescs
    266 #define	sc_initblock	sc_control_data->pcd_initblock
    267 
    268 #ifdef PCN_EVENT_COUNTERS
    269 	/* Event counters. */
    270 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
    271 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
    272 	struct evcnt sc_ev_txintr;	/* Tx interrupts */
    273 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
    274 	struct evcnt sc_ev_babl;	/* BABL in pcn_intr() */
    275 	struct evcnt sc_ev_miss;	/* MISS in pcn_intr() */
    276 	struct evcnt sc_ev_merr;	/* MERR in pcn_intr() */
    277 
    278 	struct evcnt sc_ev_txseg1;	/* Tx packets w/ 1 segment */
    279 	struct evcnt sc_ev_txseg2;	/* Tx packets w/ 2 segments */
    280 	struct evcnt sc_ev_txseg3;	/* Tx packets w/ 3 segments */
    281 	struct evcnt sc_ev_txseg4;	/* Tx packets w/ 4 segments */
    282 	struct evcnt sc_ev_txseg5;	/* Tx packets w/ 5 segments */
    283 	struct evcnt sc_ev_txsegmore;	/* Tx packets w/ more than 5 segments */
    284 	struct evcnt sc_ev_txcopy;	/* Tx copies required */
    285 #endif /* PCN_EVENT_COUNTERS */
    286 
    287 	const char * const *sc_rcvfw_desc;	/* Rx FIFO watermark info */
    288 	int sc_rcvfw;
    289 
    290 	const char * const *sc_xmtsp_desc;	/* Tx start point info */
    291 	int sc_xmtsp;
    292 
    293 	const char * const *sc_xmtfw_desc;	/* Tx FIFO watermark info */
    294 	int sc_xmtfw;
    295 
    296 	int sc_flags;			/* misc. flags; see below */
    297 	int sc_swstyle;			/* the software style in use */
    298 
    299 	int sc_txfree;			/* number of free Tx descriptors */
    300 	int sc_txnext;			/* next ready Tx descriptor */
    301 
    302 	int sc_txsfree;			/* number of free Tx jobs */
    303 	int sc_txsnext;			/* next free Tx job */
    304 	int sc_txsdirty;		/* dirty Tx jobs */
    305 
    306 	int sc_rxptr;			/* next ready Rx descriptor/job */
    307 
    308 	uint32_t sc_csr5;		/* prototype CSR5 register */
    309 	uint32_t sc_mode;		/* prototype MODE register */
    310 
    311 	krndsource_t rnd_source;	/* random source */
    312 };
    313 
    314 /* sc_flags */
    315 #define	PCN_F_HAS_MII		0x0001	/* has MII */
    316 
    317 #ifdef PCN_EVENT_COUNTERS
    318 #define	PCN_EVCNT_INCR(ev)	(ev)->ev_count++
    319 #else
    320 #define	PCN_EVCNT_INCR(ev)	/* nothing */
    321 #endif
    322 
    323 #define	PCN_CDTXADDR(sc, x)	((sc)->sc_cddma + PCN_CDTXOFF((x)))
    324 #define	PCN_CDRXADDR(sc, x)	((sc)->sc_cddma + PCN_CDRXOFF((x)))
    325 #define	PCN_CDINITADDR(sc)	((sc)->sc_cddma + PCN_CDINITOFF)
    326 
    327 #define	PCN_CDTXSYNC(sc, x, n, ops)					\
    328 do {									\
    329 	int __x, __n;							\
    330 									\
    331 	__x = (x);							\
    332 	__n = (n);							\
    333 									\
    334 	/* If it will wrap around, sync to the end of the ring. */	\
    335 	if ((__x + __n) > PCN_NTXDESC) {				\
    336 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
    337 		    PCN_CDTXOFF(__x), sizeof(struct letmd) *		\
    338 		    (PCN_NTXDESC - __x), (ops));			\
    339 		__n -= (PCN_NTXDESC - __x);				\
    340 		__x = 0;						\
    341 	}								\
    342 									\
    343 	/* Now sync whatever is left. */				\
    344 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    345 	    PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops));	\
    346 } while (/*CONSTCOND*/0)
    347 
    348 #define	PCN_CDRXSYNC(sc, x, ops)					\
    349 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    350 	    PCN_CDRXOFF((x)), sizeof(struct lermd), (ops))
    351 
    352 #define	PCN_CDINITSYNC(sc, ops)						\
    353 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    354 	    PCN_CDINITOFF, sizeof(struct leinit), (ops))
    355 
    356 #define	PCN_INIT_RXDESC(sc, x)						\
    357 do {									\
    358 	struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
    359 	struct lermd *__rmd = &(sc)->sc_rxdescs[(x)];			\
    360 	struct mbuf *__m = __rxs->rxs_mbuf;				\
    361 									\
    362 	/*								\
    363 	 * Note: We scoot the packet forward 2 bytes in the buffer	\
    364 	 * so that the payload after the Ethernet header is aligned	\
    365 	 * to a 4-byte boundary.					\
    366 	 */								\
    367 	__m->m_data = __m->m_ext.ext_buf + 2;				\
    368 									\
    369 	if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) {		\
    370 		__rmd->rmd2 =						\
    371 		    htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2);	\
    372 		__rmd->rmd0 = 0;					\
    373 	} else {							\
    374 		__rmd->rmd2 = 0;					\
    375 		__rmd->rmd0 =						\
    376 		    htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2);	\
    377 	}								\
    378 	__rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| 			\
    379 	    (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK));			\
    380 	PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\
    381 } while(/*CONSTCOND*/0)
    382 
    383 static void	pcn_start(struct ifnet *);
    384 static void	pcn_watchdog(struct ifnet *);
    385 static int	pcn_ioctl(struct ifnet *, u_long, void *);
    386 static int	pcn_init(struct ifnet *);
    387 static void	pcn_stop(struct ifnet *, int);
    388 
    389 static bool	pcn_shutdown(device_t, int);
    390 
    391 static void	pcn_reset(struct pcn_softc *);
    392 static void	pcn_rxdrain(struct pcn_softc *);
    393 static int	pcn_add_rxbuf(struct pcn_softc *, int);
    394 static void	pcn_tick(void *);
    395 
    396 static void	pcn_spnd(struct pcn_softc *);
    397 
    398 static void	pcn_set_filter(struct pcn_softc *);
    399 
    400 static int	pcn_intr(void *);
    401 static void	pcn_txintr(struct pcn_softc *);
    402 static int	pcn_rxintr(struct pcn_softc *);
    403 
    404 static int	pcn_mii_readreg(device_t, int, int);
    405 static void	pcn_mii_writereg(device_t, int, int, int);
    406 static void	pcn_mii_statchg(struct ifnet *);
    407 
    408 static void	pcn_79c970_mediainit(struct pcn_softc *);
    409 static int	pcn_79c970_mediachange(struct ifnet *);
    410 static void	pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *);
    411 
    412 static void	pcn_79c971_mediainit(struct pcn_softc *);
    413 
    414 /*
    415  * Description of a PCnet-PCI variant.  Used to select media access
    416  * method, mostly, and to print a nice description of the chip.
    417  */
    418 static const struct pcn_variant {
    419 	const char *pcv_desc;
    420 	void (*pcv_mediainit)(struct pcn_softc *);
    421 	uint16_t pcv_chipid;
    422 } pcn_variants[] = {
    423 	{ "Am79c970 PCnet-PCI",
    424 	  pcn_79c970_mediainit,
    425 	  PARTID_Am79c970 },
    426 
    427 	{ "Am79c970A PCnet-PCI II",
    428 	  pcn_79c970_mediainit,
    429 	  PARTID_Am79c970A },
    430 
    431 	{ "Am79c971 PCnet-FAST",
    432 	  pcn_79c971_mediainit,
    433 	  PARTID_Am79c971 },
    434 
    435 	{ "Am79c972 PCnet-FAST+",
    436 	  pcn_79c971_mediainit,
    437 	  PARTID_Am79c972 },
    438 
    439 	{ "Am79c973 PCnet-FAST III",
    440 	  pcn_79c971_mediainit,
    441 	  PARTID_Am79c973 },
    442 
    443 	{ "Am79c975 PCnet-FAST III",
    444 	  pcn_79c971_mediainit,
    445 	  PARTID_Am79c975 },
    446 
    447 	{ "Unknown PCnet-PCI variant",
    448 	  pcn_79c971_mediainit,
    449 	  0 },
    450 };
    451 
    452 int	pcn_copy_small = 0;
    453 
    454 static int	pcn_match(device_t, cfdata_t, void *);
    455 static void	pcn_attach(device_t, device_t, void *);
    456 
    457 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc),
    458     pcn_match, pcn_attach, NULL, NULL);
    459 
    460 /*
    461  * Routines to read and write the PCnet-PCI CSR/BCR space.
    462  */
    463 
    464 static inline uint32_t
    465 pcn_csr_read(struct pcn_softc *sc, int reg)
    466 {
    467 
    468 	bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
    469 	return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP));
    470 }
    471 
    472 static inline void
    473 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val)
    474 {
    475 
    476 	bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
    477 	bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val);
    478 }
    479 
    480 static inline uint32_t
    481 pcn_bcr_read(struct pcn_softc *sc, int reg)
    482 {
    483 
    484 	bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
    485 	return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP));
    486 }
    487 
    488 static inline void
    489 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val)
    490 {
    491 
    492 	bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
    493 	bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val);
    494 }
    495 
    496 static bool
    497 pcn_is_vmware(const char *enaddr)
    498 {
    499 
    500 	/*
    501 	 * VMware uses the OUI 00:0c:29 for auto-generated MAC
    502 	 * addresses.
    503 	 */
    504 	if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29)
    505 		return (TRUE);
    506 
    507 	/*
    508 	 * VMware uses the OUI 00:50:56 for manually-set MAC
    509 	 * addresses (and some auto-generated ones).
    510 	 */
    511 	if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56)
    512 		return (TRUE);
    513 
    514 	return (FALSE);
    515 }
    516 
    517 static const struct pcn_variant *
    518 pcn_lookup_variant(uint16_t chipid)
    519 {
    520 	const struct pcn_variant *pcv;
    521 
    522 	for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) {
    523 		if (chipid == pcv->pcv_chipid)
    524 			return (pcv);
    525 	}
    526 
    527 	/*
    528 	 * This covers unknown chips, which we simply treat like
    529 	 * a generic PCnet-FAST.
    530 	 */
    531 	return (pcv);
    532 }
    533 
    534 static int
    535 pcn_match(device_t parent, cfdata_t cf, void *aux)
    536 {
    537 	struct pci_attach_args *pa = aux;
    538 
    539 	/*
    540 	 * IBM Makes a PCI variant of this card which shows up as a
    541 	 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25)
    542 	 * this card is truly a pcn card, so we have a special case match for
    543 	 * it
    544 	 */
    545 
    546 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT &&
    547 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX &&
    548 	    PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK)
    549 		return(1);
    550 
    551 	if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
    552 		return (0);
    553 
    554 	switch (PCI_PRODUCT(pa->pa_id)) {
    555 	case PCI_PRODUCT_AMD_PCNET_PCI:
    556 		/* Beat if_le_pci.c */
    557 		return (10);
    558 	}
    559 
    560 	return (0);
    561 }
    562 
    563 static void
    564 pcn_attach(device_t parent, device_t self, void *aux)
    565 {
    566 	struct pcn_softc *sc = device_private(self);
    567 	struct pci_attach_args *pa = aux;
    568 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    569 	pci_chipset_tag_t pc = pa->pa_pc;
    570 	pci_intr_handle_t ih;
    571 	const char *intrstr = NULL;
    572 	bus_space_tag_t iot, memt;
    573 	bus_space_handle_t ioh, memh;
    574 	bus_dma_segment_t seg;
    575 	int ioh_valid, memh_valid;
    576 	int ntxsegs, i, rseg, error;
    577 	uint32_t chipid, reg;
    578 	uint8_t enaddr[ETHER_ADDR_LEN];
    579 	prop_object_t obj;
    580 	bool is_vmware;
    581 	char intrbuf[PCI_INTRSTR_LEN];
    582 
    583 	sc->sc_dev = self;
    584 	callout_init(&sc->sc_tick_ch, 0);
    585 
    586 	aprint_normal(": AMD PCnet-PCI Ethernet\n");
    587 
    588 	/*
    589 	 * Map the device.
    590 	 */
    591 	ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
    592 	    &iot, &ioh, NULL, NULL) == 0);
    593 	memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM,
    594 	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
    595 	    &memt, &memh, NULL, NULL) == 0);
    596 
    597 	if (memh_valid) {
    598 		sc->sc_st = memt;
    599 		sc->sc_sh = memh;
    600 	} else if (ioh_valid) {
    601 		sc->sc_st = iot;
    602 		sc->sc_sh = ioh;
    603 	} else {
    604 		aprint_error_dev(self, "unable to map device registers\n");
    605 		return;
    606 	}
    607 
    608 	sc->sc_dmat = pa->pa_dmat;
    609 
    610 	/* Make sure bus mastering is enabled. */
    611 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
    612 	    pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
    613 	    PCI_COMMAND_MASTER_ENABLE);
    614 
    615 	/* power up chip */
    616 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
    617 	    NULL)) && error != EOPNOTSUPP) {
    618 		aprint_error_dev(self, "cannot activate %d\n", error);
    619 		return;
    620 	}
    621 
    622 	/*
    623 	 * Reset the chip to a known state.  This also puts the
    624 	 * chip into 32-bit mode.
    625 	 */
    626 	pcn_reset(sc);
    627 
    628 	/*
    629 	 * On some systems with the chip is an on-board device, the
    630 	 * EEPROM is not used.  Handle this by reading the MAC address
    631 	 * from the CSRs (assuming that boot firmware has written
    632 	 * it there).
    633 	 */
    634 	obj = prop_dictionary_get(device_properties(sc->sc_dev),
    635 				  "am79c970-no-eeprom");
    636 	if (prop_bool_true(obj)) {
    637 	        for (i = 0; i < 3; i++) {
    638 			uint32_t val;
    639 			val = pcn_csr_read(sc, LE_CSR12 + i);
    640 			enaddr[2 * i] = val & 0xff;
    641 			enaddr[2 * i + 1] = (val >> 8) & 0xff;
    642 		}
    643 	} else {
    644 		for (i = 0; i < ETHER_ADDR_LEN; i++) {
    645 			enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh,
    646 			    PCN32_APROM + i);
    647 		}
    648 	}
    649 
    650 	/* Check to see if this is a VMware emulated network interface. */
    651 	is_vmware = pcn_is_vmware(enaddr);
    652 
    653 	/*
    654 	 * Now that the device is mapped, attempt to figure out what
    655 	 * kind of chip we have.  Note that IDL has all 32 bits of
    656 	 * the chip ID when we're in 32-bit mode.
    657 	 */
    658 	chipid = pcn_csr_read(sc, LE_CSR88);
    659 	sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid));
    660 
    661 	aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n",
    662 	    sc->sc_variant->pcv_desc, CHIPID_VER(chipid),
    663 	    ether_sprintf(enaddr));
    664 
    665 	/*
    666 	 * VMware has a bug in its network interface emulation; we must
    667 	 * limit the number of Tx segments.
    668 	 */
    669 	if (is_vmware) {
    670 		ntxsegs = PCN_NTXSEGS_VMWARE;
    671 		prop_dictionary_set_bool(device_properties(sc->sc_dev),
    672 					 "am79c970-vmware-tx-bug", TRUE);
    673 		aprint_verbose_dev(self,
    674 		    "VMware Tx segment count bug detected\n");
    675 	} else {
    676 		ntxsegs = PCN_NTXSEGS;
    677 	}
    678 
    679 	/*
    680 	 * Map and establish our interrupt.
    681 	 */
    682 	if (pci_intr_map(pa, &ih)) {
    683 		aprint_error_dev(self, "unable to map interrupt\n");
    684 		return;
    685 	}
    686 	intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
    687 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc);
    688 	if (sc->sc_ih == NULL) {
    689 		aprint_error_dev(self, "unable to establish interrupt");
    690 		if (intrstr != NULL)
    691 			aprint_error(" at %s", intrstr);
    692 		aprint_error("\n");
    693 		return;
    694 	}
    695 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
    696 
    697 	/*
    698 	 * Allocate the control data structures, and create and load the
    699 	 * DMA map for it.
    700 	 */
    701 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
    702 	     sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
    703 	     0)) != 0) {
    704 		aprint_error_dev(self, "unable to allocate control data, "
    705 		    "error = %d\n", error);
    706 		goto fail_0;
    707 	}
    708 
    709 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    710 	     sizeof(struct pcn_control_data), (void **)&sc->sc_control_data,
    711 	     BUS_DMA_COHERENT)) != 0) {
    712 		aprint_error_dev(self, "unable to map control data, "
    713 		    "error = %d\n", error);
    714 		goto fail_1;
    715 	}
    716 
    717 	if ((error = bus_dmamap_create(sc->sc_dmat,
    718 	     sizeof(struct pcn_control_data), 1,
    719 	     sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
    720 		aprint_error_dev(self, "unable to create control data DMA map, "
    721 		    "error = %d\n", error);
    722 		goto fail_2;
    723 	}
    724 
    725 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
    726 	     sc->sc_control_data, sizeof(struct pcn_control_data), NULL,
    727 	     0)) != 0) {
    728 		aprint_error_dev(self,
    729 		    "unable to load control data DMA map, error = %d\n", error);
    730 		goto fail_3;
    731 	}
    732 
    733 	/* Create the transmit buffer DMA maps. */
    734 	for (i = 0; i < PCN_TXQUEUELEN; i++) {
    735 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
    736 		     ntxsegs, MCLBYTES, 0, 0,
    737 		     &sc->sc_txsoft[i].txs_dmamap)) != 0) {
    738 			aprint_error_dev(self,
    739 			    "unable to create tx DMA map %d, error = %d\n",
    740 			    i, error);
    741 			goto fail_4;
    742 		}
    743 	}
    744 
    745 	/* Create the receive buffer DMA maps. */
    746 	for (i = 0; i < PCN_NRXDESC; i++) {
    747 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
    748 		     MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
    749 			aprint_error_dev(self,
    750 			    "unable to create rx DMA map %d, error = %d\n",
    751 			    i, error);
    752 			goto fail_5;
    753 		}
    754 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
    755 	}
    756 
    757 	/* Initialize our media structures. */
    758 	(*sc->sc_variant->pcv_mediainit)(sc);
    759 
    760 	/*
    761 	 * Initialize FIFO watermark info.
    762 	 */
    763 	switch (sc->sc_variant->pcv_chipid) {
    764 	case PARTID_Am79c970:
    765 	case PARTID_Am79c970A:
    766 		sc->sc_rcvfw_desc = pcn_79c970_rcvfw;
    767 		sc->sc_xmtsp_desc = pcn_79c970_xmtsp;
    768 		sc->sc_xmtfw_desc = pcn_79c970_xmtfw;
    769 		break;
    770 
    771 	default:
    772 		sc->sc_rcvfw_desc = pcn_79c971_rcvfw;
    773 		/*
    774 		 * Read BCR25 to determine how much SRAM is
    775 		 * on the board.  If > 0, then we the chip
    776 		 * uses different Start Point thresholds.
    777 		 *
    778 		 * Note BCR25 and BCR26 are loaded from the
    779 		 * EEPROM on RST, and unaffected by S_RESET,
    780 		 * so we don't really have to worry about
    781 		 * them except for this.
    782 		 */
    783 		reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff;
    784 		if (reg != 0)
    785 			sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram;
    786 		else
    787 			sc->sc_xmtsp_desc = pcn_79c971_xmtsp;
    788 		sc->sc_xmtfw_desc = pcn_79c971_xmtfw;
    789 		break;
    790 	}
    791 
    792 	/*
    793 	 * Set up defaults -- see the tables above for what these
    794 	 * values mean.
    795 	 *
    796 	 * XXX How should we tune RCVFW and XMTFW?
    797 	 */
    798 	sc->sc_rcvfw = 1;	/* minimum for full-duplex */
    799 	sc->sc_xmtsp = 1;
    800 	sc->sc_xmtfw = 0;
    801 
    802 	ifp = &sc->sc_ethercom.ec_if;
    803 	strcpy(ifp->if_xname, device_xname(self));
    804 	ifp->if_softc = sc;
    805 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
    806 	ifp->if_ioctl = pcn_ioctl;
    807 	ifp->if_start = pcn_start;
    808 	ifp->if_watchdog = pcn_watchdog;
    809 	ifp->if_init = pcn_init;
    810 	ifp->if_stop = pcn_stop;
    811 	IFQ_SET_READY(&ifp->if_snd);
    812 
    813 	/* Attach the interface. */
    814 	if_attach(ifp);
    815 	ether_ifattach(ifp, enaddr);
    816 	rnd_attach_source(&sc->rnd_source, device_xname(self),
    817 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
    818 
    819 #ifdef PCN_EVENT_COUNTERS
    820 	/* Attach event counters. */
    821 	evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
    822 	    NULL, device_xname(self), "txsstall");
    823 	evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
    824 	    NULL, device_xname(self), "txdstall");
    825 	evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR,
    826 	    NULL, device_xname(self), "txintr");
    827 	evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
    828 	    NULL, device_xname(self), "rxintr");
    829 	evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC,
    830 	    NULL, device_xname(self), "babl");
    831 	evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC,
    832 	    NULL, device_xname(self), "miss");
    833 	evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC,
    834 	    NULL, device_xname(self), "merr");
    835 
    836 	evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC,
    837 	    NULL, device_xname(self), "txseg1");
    838 	evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC,
    839 	    NULL, device_xname(self), "txseg2");
    840 	evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC,
    841 	    NULL, device_xname(self), "txseg3");
    842 	evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC,
    843 	    NULL, device_xname(self), "txseg4");
    844 	evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC,
    845 	    NULL, device_xname(self), "txseg5");
    846 	evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC,
    847 	    NULL, device_xname(self), "txsegmore");
    848 	evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC,
    849 	    NULL, device_xname(self), "txcopy");
    850 #endif /* PCN_EVENT_COUNTERS */
    851 
    852 	/*
    853 	 * Establish power handler with shutdown hook, to make sure
    854 	 * the interface is shutdown during reboot.
    855 	 */
    856 	if (pmf_device_register1(self, NULL, NULL, pcn_shutdown))
    857 		pmf_class_network_register(self, ifp);
    858 	else
    859 		aprint_error_dev(self, "couldn't establish power handler\n");
    860 
    861 	return;
    862 
    863 	/*
    864 	 * Free any resources we've allocated during the failed attach
    865 	 * attempt.  Do this in reverse order and fall through.
    866 	 */
    867  fail_5:
    868 	for (i = 0; i < PCN_NRXDESC; i++) {
    869 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
    870 			bus_dmamap_destroy(sc->sc_dmat,
    871 			    sc->sc_rxsoft[i].rxs_dmamap);
    872 	}
    873  fail_4:
    874 	for (i = 0; i < PCN_TXQUEUELEN; i++) {
    875 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
    876 			bus_dmamap_destroy(sc->sc_dmat,
    877 			    sc->sc_txsoft[i].txs_dmamap);
    878 	}
    879 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
    880  fail_3:
    881 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
    882  fail_2:
    883 	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
    884 	    sizeof(struct pcn_control_data));
    885  fail_1:
    886 	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
    887  fail_0:
    888 	return;
    889 }
    890 
    891 /*
    892  * pcn_shutdown:
    893  *
    894  *	Make sure the interface is stopped at reboot time.
    895  */
    896 static bool
    897 pcn_shutdown(device_t self, int howto)
    898 {
    899 	struct pcn_softc *sc = device_private(self);
    900 
    901 	pcn_stop(&sc->sc_ethercom.ec_if, 1);
    902 	/* explicitly reset the chip for some onboard one with lazy firmware */
    903 	pcn_reset(sc);
    904 
    905 	return true;
    906 }
    907 
    908 /*
    909  * pcn_start:		[ifnet interface function]
    910  *
    911  *	Start packet transmission on the interface.
    912  */
    913 static void
    914 pcn_start(struct ifnet *ifp)
    915 {
    916 	struct pcn_softc *sc = ifp->if_softc;
    917 	struct mbuf *m0, *m;
    918 	struct pcn_txsoft *txs;
    919 	bus_dmamap_t dmamap;
    920 	int error, nexttx, lasttx = -1, ofree, seg;
    921 
    922 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
    923 		return;
    924 
    925 	/*
    926 	 * Remember the previous number of free descriptors and
    927 	 * the first descriptor we'll use.
    928 	 */
    929 	ofree = sc->sc_txfree;
    930 
    931 	/*
    932 	 * Loop through the send queue, setting up transmit descriptors
    933 	 * until we drain the queue, or use up all available transmit
    934 	 * descriptors.
    935 	 */
    936 	for (;;) {
    937 		/* Grab a packet off the queue. */
    938 		IFQ_POLL(&ifp->if_snd, m0);
    939 		if (m0 == NULL)
    940 			break;
    941 		m = NULL;
    942 
    943 		/* Get a work queue entry. */
    944 		if (sc->sc_txsfree == 0) {
    945 			PCN_EVCNT_INCR(&sc->sc_ev_txsstall);
    946 			break;
    947 		}
    948 
    949 		txs = &sc->sc_txsoft[sc->sc_txsnext];
    950 		dmamap = txs->txs_dmamap;
    951 
    952 		/*
    953 		 * Load the DMA map.  If this fails, the packet either
    954 		 * didn't fit in the alloted number of segments, or we
    955 		 * were short on resources.  In this case, we'll copy
    956 		 * and try again.
    957 		 */
    958 		if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
    959 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) {
    960 			PCN_EVCNT_INCR(&sc->sc_ev_txcopy);
    961 			MGETHDR(m, M_DONTWAIT, MT_DATA);
    962 			if (m == NULL) {
    963 				printf("%s: unable to allocate Tx mbuf\n",
    964 				    device_xname(sc->sc_dev));
    965 				break;
    966 			}
    967 			if (m0->m_pkthdr.len > MHLEN) {
    968 				MCLGET(m, M_DONTWAIT);
    969 				if ((m->m_flags & M_EXT) == 0) {
    970 					printf("%s: unable to allocate Tx "
    971 					    "cluster\n",
    972 					    device_xname(sc->sc_dev));
    973 					m_freem(m);
    974 					break;
    975 				}
    976 			}
    977 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
    978 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
    979 			error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
    980 			    m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
    981 			if (error) {
    982 				printf("%s: unable to load Tx buffer, "
    983 				    "error = %d\n", device_xname(sc->sc_dev),
    984 				    error);
    985 				break;
    986 			}
    987 		}
    988 
    989 		/*
    990 		 * Ensure we have enough descriptors free to describe
    991 		 * the packet.  Note, we always reserve one descriptor
    992 		 * at the end of the ring as a termination point, to
    993 		 * prevent wrap-around.
    994 		 */
    995 		if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) {
    996 			/*
    997 			 * Not enough free descriptors to transmit this
    998 			 * packet.  We haven't committed anything yet,
    999 			 * so just unload the DMA map, put the packet
   1000 			 * back on the queue, and punt.  Notify the upper
   1001 			 * layer that there are not more slots left.
   1002 			 *
   1003 			 * XXX We could allocate an mbuf and copy, but
   1004 			 * XXX is it worth it?
   1005 			 */
   1006 			ifp->if_flags |= IFF_OACTIVE;
   1007 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   1008 			if (m != NULL)
   1009 				m_freem(m);
   1010 			PCN_EVCNT_INCR(&sc->sc_ev_txdstall);
   1011 			break;
   1012 		}
   1013 
   1014 		IFQ_DEQUEUE(&ifp->if_snd, m0);
   1015 		if (m != NULL) {
   1016 			m_freem(m0);
   1017 			m0 = m;
   1018 		}
   1019 
   1020 		/*
   1021 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
   1022 		 */
   1023 
   1024 		/* Sync the DMA map. */
   1025 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   1026 		    BUS_DMASYNC_PREWRITE);
   1027 
   1028 #ifdef PCN_EVENT_COUNTERS
   1029 		switch (dmamap->dm_nsegs) {
   1030 		case 1:
   1031 			PCN_EVCNT_INCR(&sc->sc_ev_txseg1);
   1032 			break;
   1033 		case 2:
   1034 			PCN_EVCNT_INCR(&sc->sc_ev_txseg2);
   1035 			break;
   1036 		case 3:
   1037 			PCN_EVCNT_INCR(&sc->sc_ev_txseg3);
   1038 			break;
   1039 		case 4:
   1040 			PCN_EVCNT_INCR(&sc->sc_ev_txseg4);
   1041 			break;
   1042 		case 5:
   1043 			PCN_EVCNT_INCR(&sc->sc_ev_txseg5);
   1044 			break;
   1045 		default:
   1046 			PCN_EVCNT_INCR(&sc->sc_ev_txsegmore);
   1047 			break;
   1048 		}
   1049 #endif /* PCN_EVENT_COUNTERS */
   1050 
   1051 		/*
   1052 		 * Initialize the transmit descriptors.
   1053 		 */
   1054 		if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) {
   1055 			for (nexttx = sc->sc_txnext, seg = 0;
   1056 			     seg < dmamap->dm_nsegs;
   1057 			     seg++, nexttx = PCN_NEXTTX(nexttx)) {
   1058 				/*
   1059 				 * If this is the first descriptor we're
   1060 				 * enqueueing, don't set the OWN bit just
   1061 				 * yet.  That could cause a race condition.
   1062 				 * We'll do it below.
   1063 				 */
   1064 				sc->sc_txdescs[nexttx].tmd0 = 0;
   1065 				sc->sc_txdescs[nexttx].tmd2 =
   1066 				    htole32(dmamap->dm_segs[seg].ds_addr);
   1067 				sc->sc_txdescs[nexttx].tmd1 =
   1068 				    htole32(LE_T1_ONES |
   1069 				    (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) |
   1070 				    (LE_BCNT(dmamap->dm_segs[seg].ds_len) &
   1071 				     LE_T1_BCNT_MASK));
   1072 				lasttx = nexttx;
   1073 			}
   1074 		} else {
   1075 			for (nexttx = sc->sc_txnext, seg = 0;
   1076 			     seg < dmamap->dm_nsegs;
   1077 			     seg++, nexttx = PCN_NEXTTX(nexttx)) {
   1078 				/*
   1079 				 * If this is the first descriptor we're
   1080 				 * enqueueing, don't set the OWN bit just
   1081 				 * yet.  That could cause a race condition.
   1082 				 * We'll do it below.
   1083 				 */
   1084 				sc->sc_txdescs[nexttx].tmd0 =
   1085 				    htole32(dmamap->dm_segs[seg].ds_addr);
   1086 				sc->sc_txdescs[nexttx].tmd2 = 0;
   1087 				sc->sc_txdescs[nexttx].tmd1 =
   1088 				    htole32(LE_T1_ONES |
   1089 				    (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) |
   1090 				    (LE_BCNT(dmamap->dm_segs[seg].ds_len) &
   1091 				     LE_T1_BCNT_MASK));
   1092 				lasttx = nexttx;
   1093 			}
   1094 		}
   1095 
   1096 		KASSERT(lasttx != -1);
   1097 		/* Interrupt on the packet, if appropriate. */
   1098 		if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0)
   1099 			sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT);
   1100 
   1101 		/* Set `start of packet' and `end of packet' appropriately. */
   1102 		sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP);
   1103 		sc->sc_txdescs[sc->sc_txnext].tmd1 |=
   1104 		    htole32(LE_T1_OWN|LE_T1_STP);
   1105 
   1106 		/* Sync the descriptors we're using. */
   1107 		PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
   1108 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1109 
   1110 		/* Kick the transmitter. */
   1111 		pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD);
   1112 
   1113 		/*
   1114 		 * Store a pointer to the packet so we can free it later,
   1115 		 * and remember what txdirty will be once the packet is
   1116 		 * done.
   1117 		 */
   1118 		txs->txs_mbuf = m0;
   1119 		txs->txs_firstdesc = sc->sc_txnext;
   1120 		txs->txs_lastdesc = lasttx;
   1121 
   1122 		/* Advance the tx pointer. */
   1123 		sc->sc_txfree -= dmamap->dm_nsegs;
   1124 		sc->sc_txnext = nexttx;
   1125 
   1126 		sc->sc_txsfree--;
   1127 		sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext);
   1128 
   1129 		/* Pass the packet to any BPF listeners. */
   1130 		bpf_mtap(ifp, m0);
   1131 	}
   1132 
   1133 	if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) {
   1134 		/* No more slots left; notify upper layer. */
   1135 		ifp->if_flags |= IFF_OACTIVE;
   1136 	}
   1137 
   1138 	if (sc->sc_txfree != ofree) {
   1139 		/* Set a watchdog timer in case the chip flakes out. */
   1140 		ifp->if_timer = 5;
   1141 	}
   1142 }
   1143 
   1144 /*
   1145  * pcn_watchdog:	[ifnet interface function]
   1146  *
   1147  *	Watchdog timer handler.
   1148  */
   1149 static void
   1150 pcn_watchdog(struct ifnet *ifp)
   1151 {
   1152 	struct pcn_softc *sc = ifp->if_softc;
   1153 
   1154 	/*
   1155 	 * Since we're not interrupting every packet, sweep
   1156 	 * up before we report an error.
   1157 	 */
   1158 	pcn_txintr(sc);
   1159 
   1160 	if (sc->sc_txfree != PCN_NTXDESC) {
   1161 		printf("%s: device timeout (txfree %d txsfree %d)\n",
   1162 		    device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree);
   1163 		ifp->if_oerrors++;
   1164 
   1165 		/* Reset the interface. */
   1166 		(void) pcn_init(ifp);
   1167 	}
   1168 
   1169 	/* Try to get more packets going. */
   1170 	pcn_start(ifp);
   1171 }
   1172 
   1173 /*
   1174  * pcn_ioctl:		[ifnet interface function]
   1175  *
   1176  *	Handle control requests from the operator.
   1177  */
   1178 static int
   1179 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data)
   1180 {
   1181 	struct pcn_softc *sc = ifp->if_softc;
   1182 	struct ifreq *ifr = (struct ifreq *) data;
   1183 	int s, error;
   1184 
   1185 	s = splnet();
   1186 
   1187 	switch (cmd) {
   1188 	case SIOCSIFMEDIA:
   1189 	case SIOCGIFMEDIA:
   1190 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
   1191 		break;
   1192 
   1193 	default:
   1194 		error = ether_ioctl(ifp, cmd, data);
   1195 		if (error == ENETRESET) {
   1196 			/*
   1197 			 * Multicast list has changed; set the hardware filter
   1198 			 * accordingly.
   1199 			 */
   1200 			if (ifp->if_flags & IFF_RUNNING)
   1201 				error = pcn_init(ifp);
   1202 			else
   1203 				error = 0;
   1204 		}
   1205 		break;
   1206 	}
   1207 
   1208 	/* Try to get more packets going. */
   1209 	pcn_start(ifp);
   1210 
   1211 	splx(s);
   1212 	return (error);
   1213 }
   1214 
   1215 /*
   1216  * pcn_intr:
   1217  *
   1218  *	Interrupt service routine.
   1219  */
   1220 static int
   1221 pcn_intr(void *arg)
   1222 {
   1223 	struct pcn_softc *sc = arg;
   1224 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1225 	uint32_t csr0;
   1226 	int wantinit, handled = 0;
   1227 
   1228 	for (wantinit = 0; wantinit == 0;) {
   1229 		csr0 = pcn_csr_read(sc, LE_CSR0);
   1230 		if ((csr0 & LE_C0_INTR) == 0)
   1231 			break;
   1232 
   1233 		rnd_add_uint32(&sc->rnd_source, csr0);
   1234 
   1235 		/* ACK the bits and re-enable interrupts. */
   1236 		pcn_csr_write(sc, LE_CSR0, csr0 &
   1237 		    (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT|
   1238 		     LE_C0_TINT|LE_C0_IDON));
   1239 
   1240 		handled = 1;
   1241 
   1242 		if (csr0 & LE_C0_RINT) {
   1243 			PCN_EVCNT_INCR(&sc->sc_ev_rxintr);
   1244 			wantinit = pcn_rxintr(sc);
   1245 		}
   1246 
   1247 		if (csr0 & LE_C0_TINT) {
   1248 			PCN_EVCNT_INCR(&sc->sc_ev_txintr);
   1249 			pcn_txintr(sc);
   1250 		}
   1251 
   1252 		if (csr0 & LE_C0_ERR) {
   1253 			if (csr0 & LE_C0_BABL) {
   1254 				PCN_EVCNT_INCR(&sc->sc_ev_babl);
   1255 				ifp->if_oerrors++;
   1256 			}
   1257 			if (csr0 & LE_C0_MISS) {
   1258 				PCN_EVCNT_INCR(&sc->sc_ev_miss);
   1259 				ifp->if_ierrors++;
   1260 			}
   1261 			if (csr0 & LE_C0_MERR) {
   1262 				PCN_EVCNT_INCR(&sc->sc_ev_merr);
   1263 				printf("%s: memory error\n",
   1264 				    device_xname(sc->sc_dev));
   1265 				wantinit = 1;
   1266 				break;
   1267 			}
   1268 		}
   1269 
   1270 		if ((csr0 & LE_C0_RXON) == 0) {
   1271 			printf("%s: receiver disabled\n",
   1272 			    device_xname(sc->sc_dev));
   1273 			ifp->if_ierrors++;
   1274 			wantinit = 1;
   1275 		}
   1276 
   1277 		if ((csr0 & LE_C0_TXON) == 0) {
   1278 			printf("%s: transmitter disabled\n",
   1279 			    device_xname(sc->sc_dev));
   1280 			ifp->if_oerrors++;
   1281 			wantinit = 1;
   1282 		}
   1283 	}
   1284 
   1285 	if (handled) {
   1286 		if (wantinit)
   1287 			pcn_init(ifp);
   1288 
   1289 		/* Try to get more packets going. */
   1290 		pcn_start(ifp);
   1291 	}
   1292 
   1293 	return (handled);
   1294 }
   1295 
   1296 /*
   1297  * pcn_spnd:
   1298  *
   1299  *	Suspend the chip.
   1300  */
   1301 static void
   1302 pcn_spnd(struct pcn_softc *sc)
   1303 {
   1304 	int i;
   1305 
   1306 	pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND);
   1307 
   1308 	for (i = 0; i < 10000; i++) {
   1309 		if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND)
   1310 			return;
   1311 		delay(5);
   1312 	}
   1313 
   1314 	printf("%s: WARNING: chip failed to enter suspended state\n",
   1315 	    device_xname(sc->sc_dev));
   1316 }
   1317 
   1318 /*
   1319  * pcn_txintr:
   1320  *
   1321  *	Helper; handle transmit interrupts.
   1322  */
   1323 static void
   1324 pcn_txintr(struct pcn_softc *sc)
   1325 {
   1326 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1327 	struct pcn_txsoft *txs;
   1328 	uint32_t tmd1, tmd2, tmd;
   1329 	int i, j;
   1330 
   1331 	ifp->if_flags &= ~IFF_OACTIVE;
   1332 
   1333 	/*
   1334 	 * Go through our Tx list and free mbufs for those
   1335 	 * frames which have been transmitted.
   1336 	 */
   1337 	for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN;
   1338 	     i = PCN_NEXTTXS(i), sc->sc_txsfree++) {
   1339 		txs = &sc->sc_txsoft[i];
   1340 
   1341 		PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs,
   1342 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   1343 
   1344 		tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1);
   1345 		if (tmd1 & LE_T1_OWN)
   1346 			break;
   1347 
   1348 		/*
   1349 		 * Slightly annoying -- we have to loop through the
   1350 		 * descriptors we've used looking for ERR, since it
   1351 		 * can appear on any descriptor in the chain.
   1352 		 */
   1353 		for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) {
   1354 			tmd = le32toh(sc->sc_txdescs[j].tmd1);
   1355 			if (tmd & LE_T1_ERR) {
   1356 				ifp->if_oerrors++;
   1357 				if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3)
   1358 					tmd2 = le32toh(sc->sc_txdescs[j].tmd0);
   1359 				else
   1360 					tmd2 = le32toh(sc->sc_txdescs[j].tmd2);
   1361 				if (tmd2 & LE_T2_UFLO) {
   1362 					if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) {
   1363 						sc->sc_xmtsp++;
   1364 						printf("%s: transmit "
   1365 						    "underrun; new threshold: "
   1366 						    "%s\n",
   1367 						    device_xname(sc->sc_dev),
   1368 						    sc->sc_xmtsp_desc[
   1369 						    sc->sc_xmtsp]);
   1370 						pcn_spnd(sc);
   1371 						pcn_csr_write(sc, LE_CSR80,
   1372 						    LE_C80_RCVFW(sc->sc_rcvfw) |
   1373 						    LE_C80_XMTSP(sc->sc_xmtsp) |
   1374 						    LE_C80_XMTFW(sc->sc_xmtfw));
   1375 						pcn_csr_write(sc, LE_CSR5,
   1376 						    sc->sc_csr5);
   1377 					} else {
   1378 						printf("%s: transmit "
   1379 						    "underrun\n",
   1380 						    device_xname(sc->sc_dev));
   1381 					}
   1382 				} else if (tmd2 & LE_T2_BUFF) {
   1383 					printf("%s: transmit buffer error\n",
   1384 					    device_xname(sc->sc_dev));
   1385 				}
   1386 				if (tmd2 & LE_T2_LCOL)
   1387 					ifp->if_collisions++;
   1388 				if (tmd2 & LE_T2_RTRY)
   1389 					ifp->if_collisions += 16;
   1390 				goto next_packet;
   1391 			}
   1392 			if (j == txs->txs_lastdesc)
   1393 				break;
   1394 		}
   1395 		if (tmd1 & LE_T1_ONE)
   1396 			ifp->if_collisions++;
   1397 		else if (tmd & LE_T1_MORE) {
   1398 			/* Real number is unknown. */
   1399 			ifp->if_collisions += 2;
   1400 		}
   1401 		ifp->if_opackets++;
   1402  next_packet:
   1403 		sc->sc_txfree += txs->txs_dmamap->dm_nsegs;
   1404 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
   1405 		    0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   1406 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   1407 		m_freem(txs->txs_mbuf);
   1408 		txs->txs_mbuf = NULL;
   1409 	}
   1410 
   1411 	/* Update the dirty transmit buffer pointer. */
   1412 	sc->sc_txsdirty = i;
   1413 
   1414 	/*
   1415 	 * If there are no more pending transmissions, cancel the watchdog
   1416 	 * timer.
   1417 	 */
   1418 	if (sc->sc_txsfree == PCN_TXQUEUELEN)
   1419 		ifp->if_timer = 0;
   1420 }
   1421 
   1422 /*
   1423  * pcn_rxintr:
   1424  *
   1425  *	Helper; handle receive interrupts.
   1426  */
   1427 static int
   1428 pcn_rxintr(struct pcn_softc *sc)
   1429 {
   1430 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1431 	struct pcn_rxsoft *rxs;
   1432 	struct mbuf *m;
   1433 	uint32_t rmd1;
   1434 	int i, len;
   1435 
   1436 	for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) {
   1437 		rxs = &sc->sc_rxsoft[i];
   1438 
   1439 		PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   1440 
   1441 		rmd1 = le32toh(sc->sc_rxdescs[i].rmd1);
   1442 
   1443 		if (rmd1 & LE_R1_OWN)
   1444 			break;
   1445 
   1446 		/*
   1447 		 * Check for errors and make sure the packet fit into
   1448 		 * a single buffer.  We have structured this block of
   1449 		 * code the way it is in order to compress it into
   1450 		 * one test in the common case (no error).
   1451 		 */
   1452 		if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) !=
   1453 		    (LE_R1_STP|LE_R1_ENP))) {
   1454 			/* Make sure the packet is in a single buffer. */
   1455 			if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) !=
   1456 			    (LE_R1_STP|LE_R1_ENP)) {
   1457 				printf("%s: packet spilled into next buffer\n",
   1458 				    device_xname(sc->sc_dev));
   1459 				return (1);	/* pcn_intr() will re-init */
   1460 			}
   1461 
   1462 			/*
   1463 			 * If the packet had an error, simple recycle the
   1464 			 * buffer.
   1465 			 */
   1466 			if (rmd1 & LE_R1_ERR) {
   1467 				ifp->if_ierrors++;
   1468 				/*
   1469 				 * If we got an overflow error, chances
   1470 				 * are there will be a CRC error.  In
   1471 				 * this case, just print the overflow
   1472 				 * error, and skip the others.
   1473 				 */
   1474 				if (rmd1 & LE_R1_OFLO)
   1475 					printf("%s: overflow error\n",
   1476 					    device_xname(sc->sc_dev));
   1477 				else {
   1478 #define	PRINTIT(x, str)							\
   1479 					if (rmd1 & (x))			\
   1480 						printf("%s: %s\n",	\
   1481 						    device_xname(sc->sc_dev), \
   1482 						    str);
   1483 					PRINTIT(LE_R1_FRAM, "framing error");
   1484 					PRINTIT(LE_R1_CRC, "CRC error");
   1485 					PRINTIT(LE_R1_BUFF, "buffer error");
   1486 				}
   1487 #undef PRINTIT
   1488 				PCN_INIT_RXDESC(sc, i);
   1489 				continue;
   1490 			}
   1491 		}
   1492 
   1493 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   1494 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   1495 
   1496 		/*
   1497 		 * No errors; receive the packet.
   1498 		 */
   1499 		if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3)
   1500 			len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK;
   1501 		else
   1502 			len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK;
   1503 
   1504 		/*
   1505 		 * The LANCE family includes the CRC with every packet;
   1506 		 * trim it off here.
   1507 		 */
   1508 		len -= ETHER_CRC_LEN;
   1509 
   1510 		/*
   1511 		 * If the packet is small enough to fit in a
   1512 		 * single header mbuf, allocate one and copy
   1513 		 * the data into it.  This greatly reduces
   1514 		 * memory consumption when we receive lots
   1515 		 * of small packets.
   1516 		 *
   1517 		 * Otherwise, we add a new buffer to the receive
   1518 		 * chain.  If this fails, we drop the packet and
   1519 		 * recycle the old buffer.
   1520 		 */
   1521 		if (pcn_copy_small != 0 && len <= (MHLEN - 2)) {
   1522 			MGETHDR(m, M_DONTWAIT, MT_DATA);
   1523 			if (m == NULL)
   1524 				goto dropit;
   1525 			m->m_data += 2;
   1526 			memcpy(mtod(m, void *),
   1527 			    mtod(rxs->rxs_mbuf, void *), len);
   1528 			PCN_INIT_RXDESC(sc, i);
   1529 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   1530 			    rxs->rxs_dmamap->dm_mapsize,
   1531 			    BUS_DMASYNC_PREREAD);
   1532 		} else {
   1533 			m = rxs->rxs_mbuf;
   1534 			if (pcn_add_rxbuf(sc, i) != 0) {
   1535  dropit:
   1536 				ifp->if_ierrors++;
   1537 				PCN_INIT_RXDESC(sc, i);
   1538 				bus_dmamap_sync(sc->sc_dmat,
   1539 				    rxs->rxs_dmamap, 0,
   1540 				    rxs->rxs_dmamap->dm_mapsize,
   1541 				    BUS_DMASYNC_PREREAD);
   1542 				continue;
   1543 			}
   1544 		}
   1545 
   1546 		m->m_pkthdr.rcvif = ifp;
   1547 		m->m_pkthdr.len = m->m_len = len;
   1548 
   1549 		/* Pass this up to any BPF listeners. */
   1550 		bpf_mtap(ifp, m);
   1551 
   1552 		/* Pass it on. */
   1553 		(*ifp->if_input)(ifp, m);
   1554 		ifp->if_ipackets++;
   1555 	}
   1556 
   1557 	/* Update the receive pointer. */
   1558 	sc->sc_rxptr = i;
   1559 	return (0);
   1560 }
   1561 
   1562 /*
   1563  * pcn_tick:
   1564  *
   1565  *	One second timer, used to tick the MII.
   1566  */
   1567 static void
   1568 pcn_tick(void *arg)
   1569 {
   1570 	struct pcn_softc *sc = arg;
   1571 	int s;
   1572 
   1573 	s = splnet();
   1574 	mii_tick(&sc->sc_mii);
   1575 	splx(s);
   1576 
   1577 	callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc);
   1578 }
   1579 
   1580 /*
   1581  * pcn_reset:
   1582  *
   1583  *	Perform a soft reset on the PCnet-PCI.
   1584  */
   1585 static void
   1586 pcn_reset(struct pcn_softc *sc)
   1587 {
   1588 
   1589 	/*
   1590 	 * The PCnet-PCI chip is reset by reading from the
   1591 	 * RESET register.  Note that while the NE2100 LANCE
   1592 	 * boards require a write after the read, the PCnet-PCI
   1593 	 * chips do not require this.
   1594 	 *
   1595 	 * Since we don't know if we're in 16-bit or 32-bit
   1596 	 * mode right now, issue both (it's safe) in the
   1597 	 * hopes that one will succeed.
   1598 	 */
   1599 	(void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET);
   1600 	(void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET);
   1601 
   1602 	/* Wait 1ms for it to finish. */
   1603 	delay(1000);
   1604 
   1605 	/*
   1606 	 * Select 32-bit I/O mode by issuing a 32-bit write to the
   1607 	 * RDP.  Since the RAP is 0 after a reset, writing a 0
   1608 	 * to RDP is safe (since it simply clears CSR0).
   1609 	 */
   1610 	bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0);
   1611 }
   1612 
   1613 /*
   1614  * pcn_init:		[ifnet interface function]
   1615  *
   1616  *	Initialize the interface.  Must be called at splnet().
   1617  */
   1618 static int
   1619 pcn_init(struct ifnet *ifp)
   1620 {
   1621 	struct pcn_softc *sc = ifp->if_softc;
   1622 	struct pcn_rxsoft *rxs;
   1623 	const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
   1624 	int i, error = 0;
   1625 	uint32_t reg;
   1626 
   1627 	/* Cancel any pending I/O. */
   1628 	pcn_stop(ifp, 0);
   1629 
   1630 	/* Reset the chip to a known state. */
   1631 	pcn_reset(sc);
   1632 
   1633 	/*
   1634 	 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything
   1635 	 * else.
   1636 	 *
   1637 	 * XXX It'd be really nice to use SSTYLE 2 on all the chips,
   1638 	 * because the structure layout is compatible with ILACC,
   1639 	 * but the burst mode is only available in SSTYLE 3, and
   1640 	 * burst mode should provide some performance enhancement.
   1641 	 */
   1642 	if (sc->sc_variant->pcv_chipid == PARTID_Am79c970)
   1643 		sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2;
   1644 	else
   1645 		sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3;
   1646 	pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle);
   1647 
   1648 	/* Initialize the transmit descriptor ring. */
   1649 	memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
   1650 	PCN_CDTXSYNC(sc, 0, PCN_NTXDESC,
   1651 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1652 	sc->sc_txfree = PCN_NTXDESC;
   1653 	sc->sc_txnext = 0;
   1654 
   1655 	/* Initialize the transmit job descriptors. */
   1656 	for (i = 0; i < PCN_TXQUEUELEN; i++)
   1657 		sc->sc_txsoft[i].txs_mbuf = NULL;
   1658 	sc->sc_txsfree = PCN_TXQUEUELEN;
   1659 	sc->sc_txsnext = 0;
   1660 	sc->sc_txsdirty = 0;
   1661 
   1662 	/*
   1663 	 * Initialize the receive descriptor and receive job
   1664 	 * descriptor rings.
   1665 	 */
   1666 	for (i = 0; i < PCN_NRXDESC; i++) {
   1667 		rxs = &sc->sc_rxsoft[i];
   1668 		if (rxs->rxs_mbuf == NULL) {
   1669 			if ((error = pcn_add_rxbuf(sc, i)) != 0) {
   1670 				printf("%s: unable to allocate or map rx "
   1671 				    "buffer %d, error = %d\n",
   1672 				    device_xname(sc->sc_dev), i, error);
   1673 				/*
   1674 				 * XXX Should attempt to run with fewer receive
   1675 				 * XXX buffers instead of just failing.
   1676 				 */
   1677 				pcn_rxdrain(sc);
   1678 				goto out;
   1679 			}
   1680 		} else
   1681 			PCN_INIT_RXDESC(sc, i);
   1682 	}
   1683 	sc->sc_rxptr = 0;
   1684 
   1685 	/* Initialize MODE for the initialization block. */
   1686 	sc->sc_mode = 0;
   1687 	if (ifp->if_flags & IFF_PROMISC)
   1688 		sc->sc_mode |= LE_C15_PROM;
   1689 	if ((ifp->if_flags & IFF_BROADCAST) == 0)
   1690 		sc->sc_mode |= LE_C15_DRCVBC;
   1691 
   1692 	/*
   1693 	 * If we have MII, simply select MII in the MODE register,
   1694 	 * and clear ASEL.  Otherwise, let ASEL stand (for now),
   1695 	 * and leave PORTSEL alone (it is ignored with ASEL is set).
   1696 	 */
   1697 	if (sc->sc_flags & PCN_F_HAS_MII) {
   1698 		pcn_bcr_write(sc, LE_BCR2,
   1699 		    pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL);
   1700 		sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII);
   1701 
   1702 		/*
   1703 		 * Disable MII auto-negotiation.  We handle that in
   1704 		 * our own MII layer.
   1705 		 */
   1706 		pcn_bcr_write(sc, LE_BCR32,
   1707 		    pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS);
   1708 	}
   1709 
   1710 	/*
   1711 	 * Set the Tx and Rx descriptor ring addresses in the init
   1712 	 * block, the TLEN and RLEN other fields of the init block
   1713 	 * MODE register.
   1714 	 */
   1715 	sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0));
   1716 	sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0));
   1717 	sc->sc_initblock.init_mode = htole32(sc->sc_mode |
   1718 	    ((ffs(PCN_NTXDESC) - 1) << 28) |
   1719 	    ((ffs(PCN_NRXDESC) - 1) << 20));
   1720 
   1721 	/* Set the station address in the init block. */
   1722 	sc->sc_initblock.init_padr[0] = htole32(enaddr[0] |
   1723 	    (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24));
   1724 	sc->sc_initblock.init_padr[1] = htole32(enaddr[4] |
   1725 	    (enaddr[5] << 8));
   1726 
   1727 	/* Set the multicast filter in the init block. */
   1728 	pcn_set_filter(sc);
   1729 
   1730 	/* Initialize CSR3. */
   1731 	pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO);
   1732 
   1733 	/* Initialize CSR4. */
   1734 	pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT|
   1735 	    LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM);
   1736 
   1737 	/* Initialize CSR5. */
   1738 	sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE;
   1739 	pcn_csr_write(sc, LE_CSR5, sc->sc_csr5);
   1740 
   1741 	/*
   1742 	 * If we have an Am79c971 or greater, initialize CSR7.
   1743 	 *
   1744 	 * XXX Might be nice to use the MII auto-poll interrupt someday.
   1745 	 */
   1746 	switch (sc->sc_variant->pcv_chipid) {
   1747 	case PARTID_Am79c970:
   1748 	case PARTID_Am79c970A:
   1749 		/* Not available on these chips. */
   1750 		break;
   1751 
   1752 	default:
   1753 		pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE);
   1754 		break;
   1755 	}
   1756 
   1757 	/*
   1758 	 * On the Am79c970A and greater, initialize BCR18 to
   1759 	 * enable burst mode.
   1760 	 *
   1761 	 * Also enable the "no underflow" option on the Am79c971 and
   1762 	 * higher, which prevents the chip from generating transmit
   1763 	 * underflows, yet sill provides decent performance.  Note if
   1764 	 * chip is not connected to external SRAM, then we still have
   1765 	 * to handle underflow errors (the NOUFLO bit is ignored in
   1766 	 * that case).
   1767 	 */
   1768 	reg = pcn_bcr_read(sc, LE_BCR18);
   1769 	switch (sc->sc_variant->pcv_chipid) {
   1770 	case PARTID_Am79c970:
   1771 		break;
   1772 
   1773 	case PARTID_Am79c970A:
   1774 		reg |= LE_B18_BREADE|LE_B18_BWRITE;
   1775 		break;
   1776 
   1777 	default:
   1778 		reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO;
   1779 		break;
   1780 	}
   1781 	pcn_bcr_write(sc, LE_BCR18, reg);
   1782 
   1783 	/*
   1784 	 * Initialize CSR80 (FIFO thresholds for Tx and Rx).
   1785 	 */
   1786 	pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) |
   1787 	    LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw));
   1788 
   1789 	/*
   1790 	 * Send the init block to the chip, and wait for it
   1791 	 * to be processed.
   1792 	 */
   1793 	PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE);
   1794 	pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff);
   1795 	pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff);
   1796 	pcn_csr_write(sc, LE_CSR0, LE_C0_INIT);
   1797 	delay(100);
   1798 	for (i = 0; i < 10000; i++) {
   1799 		if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON)
   1800 			break;
   1801 		delay(10);
   1802 	}
   1803 	PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE);
   1804 	if (i == 10000) {
   1805 		printf("%s: timeout processing init block\n",
   1806 		    device_xname(sc->sc_dev));
   1807 		error = EIO;
   1808 		goto out;
   1809 	}
   1810 
   1811 	/* Set the media. */
   1812 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
   1813 		goto out;
   1814 
   1815 	/* Enable interrupts and external activity (and ACK IDON). */
   1816 	pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON);
   1817 
   1818 	if (sc->sc_flags & PCN_F_HAS_MII) {
   1819 		/* Start the one second MII clock. */
   1820 		callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc);
   1821 	}
   1822 
   1823 	/* ...all done! */
   1824 	ifp->if_flags |= IFF_RUNNING;
   1825 	ifp->if_flags &= ~IFF_OACTIVE;
   1826 
   1827  out:
   1828 	if (error)
   1829 		printf("%s: interface not running\n", device_xname(sc->sc_dev));
   1830 	return (error);
   1831 }
   1832 
   1833 /*
   1834  * pcn_rxdrain:
   1835  *
   1836  *	Drain the receive queue.
   1837  */
   1838 static void
   1839 pcn_rxdrain(struct pcn_softc *sc)
   1840 {
   1841 	struct pcn_rxsoft *rxs;
   1842 	int i;
   1843 
   1844 	for (i = 0; i < PCN_NRXDESC; i++) {
   1845 		rxs = &sc->sc_rxsoft[i];
   1846 		if (rxs->rxs_mbuf != NULL) {
   1847 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   1848 			m_freem(rxs->rxs_mbuf);
   1849 			rxs->rxs_mbuf = NULL;
   1850 		}
   1851 	}
   1852 }
   1853 
   1854 /*
   1855  * pcn_stop:		[ifnet interface function]
   1856  *
   1857  *	Stop transmission on the interface.
   1858  */
   1859 static void
   1860 pcn_stop(struct ifnet *ifp, int disable)
   1861 {
   1862 	struct pcn_softc *sc = ifp->if_softc;
   1863 	struct pcn_txsoft *txs;
   1864 	int i;
   1865 
   1866 	if (sc->sc_flags & PCN_F_HAS_MII) {
   1867 		/* Stop the one second clock. */
   1868 		callout_stop(&sc->sc_tick_ch);
   1869 
   1870 		/* Down the MII. */
   1871 		mii_down(&sc->sc_mii);
   1872 	}
   1873 
   1874 	/* Stop the chip. */
   1875 	pcn_csr_write(sc, LE_CSR0, LE_C0_STOP);
   1876 
   1877 	/* Release any queued transmit buffers. */
   1878 	for (i = 0; i < PCN_TXQUEUELEN; i++) {
   1879 		txs = &sc->sc_txsoft[i];
   1880 		if (txs->txs_mbuf != NULL) {
   1881 			bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   1882 			m_freem(txs->txs_mbuf);
   1883 			txs->txs_mbuf = NULL;
   1884 		}
   1885 	}
   1886 
   1887 	/* Mark the interface as down and cancel the watchdog timer. */
   1888 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   1889 	ifp->if_timer = 0;
   1890 
   1891 	if (disable)
   1892 		pcn_rxdrain(sc);
   1893 }
   1894 
   1895 /*
   1896  * pcn_add_rxbuf:
   1897  *
   1898  *	Add a receive buffer to the indicated descriptor.
   1899  */
   1900 static int
   1901 pcn_add_rxbuf(struct pcn_softc *sc, int idx)
   1902 {
   1903 	struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx];
   1904 	struct mbuf *m;
   1905 	int error;
   1906 
   1907 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   1908 	if (m == NULL)
   1909 		return (ENOBUFS);
   1910 
   1911 	MCLGET(m, M_DONTWAIT);
   1912 	if ((m->m_flags & M_EXT) == 0) {
   1913 		m_freem(m);
   1914 		return (ENOBUFS);
   1915 	}
   1916 
   1917 	if (rxs->rxs_mbuf != NULL)
   1918 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   1919 
   1920 	rxs->rxs_mbuf = m;
   1921 
   1922 	error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
   1923 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
   1924 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
   1925 	if (error) {
   1926 		printf("%s: can't load rx DMA map %d, error = %d\n",
   1927 		    device_xname(sc->sc_dev), idx, error);
   1928 		panic("pcn_add_rxbuf");
   1929 	}
   1930 
   1931 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   1932 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   1933 
   1934 	PCN_INIT_RXDESC(sc, idx);
   1935 
   1936 	return (0);
   1937 }
   1938 
   1939 /*
   1940  * pcn_set_filter:
   1941  *
   1942  *	Set up the receive filter.
   1943  */
   1944 static void
   1945 pcn_set_filter(struct pcn_softc *sc)
   1946 {
   1947 	struct ethercom *ec = &sc->sc_ethercom;
   1948 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1949 	struct ether_multi *enm;
   1950 	struct ether_multistep step;
   1951 	uint32_t crc;
   1952 
   1953 	/*
   1954 	 * Set up the multicast address filter by passing all multicast
   1955 	 * addresses through a CRC generator, and then using the high
   1956 	 * order 6 bits as an index into the 64-bit logical address
   1957 	 * filter.  The high order bits select the word, while the rest
   1958 	 * of the bits select the bit within the word.
   1959 	 */
   1960 
   1961 	if (ifp->if_flags & IFF_PROMISC)
   1962 		goto allmulti;
   1963 
   1964 	sc->sc_initblock.init_ladrf[0] =
   1965 	    sc->sc_initblock.init_ladrf[1] =
   1966 	    sc->sc_initblock.init_ladrf[2] =
   1967 	    sc->sc_initblock.init_ladrf[3] = 0;
   1968 
   1969 	ETHER_FIRST_MULTI(step, ec, enm);
   1970 	while (enm != NULL) {
   1971 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   1972 			/*
   1973 			 * We must listen to a range of multicast addresses.
   1974 			 * For now, just accept all multicasts, rather than
   1975 			 * trying to set only those filter bits needed to match
   1976 			 * the range.  (At this time, the only use of address
   1977 			 * ranges is for IP multicast routing, for which the
   1978 			 * range is big enough to require all bits set.)
   1979 			 */
   1980 			goto allmulti;
   1981 		}
   1982 
   1983 		crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
   1984 
   1985 		/* Just want the 6 most significant bits. */
   1986 		crc >>= 26;
   1987 
   1988 		/* Set the corresponding bit in the filter. */
   1989 		sc->sc_initblock.init_ladrf[crc >> 4] |=
   1990 		    htole16(1 << (crc & 0xf));
   1991 
   1992 		ETHER_NEXT_MULTI(step, enm);
   1993 	}
   1994 
   1995 	ifp->if_flags &= ~IFF_ALLMULTI;
   1996 	return;
   1997 
   1998  allmulti:
   1999 	ifp->if_flags |= IFF_ALLMULTI;
   2000 	sc->sc_initblock.init_ladrf[0] =
   2001 	    sc->sc_initblock.init_ladrf[1] =
   2002 	    sc->sc_initblock.init_ladrf[2] =
   2003 	    sc->sc_initblock.init_ladrf[3] = 0xffff;
   2004 }
   2005 
   2006 /*
   2007  * pcn_79c970_mediainit:
   2008  *
   2009  *	Initialize media for the Am79c970.
   2010  */
   2011 static void
   2012 pcn_79c970_mediainit(struct pcn_softc *sc)
   2013 {
   2014 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2015 	const char *sep = "";
   2016 
   2017 	sc->sc_mii.mii_ifp = ifp;
   2018 
   2019 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange,
   2020 	    pcn_79c970_mediastatus);
   2021 
   2022 #define	ADD(str, m, d)							\
   2023 do {									\
   2024 	aprint_normal("%s%s", sep, str);					\
   2025 	ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL);	\
   2026 	sep = ", ";							\
   2027 } while (/*CONSTCOND*/0)
   2028 
   2029 	aprint_normal("%s: ", device_xname(sc->sc_dev));
   2030 	ADD("10base5", IFM_10_5, PORTSEL_AUI);
   2031 	if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A)
   2032 		ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI);
   2033 	ADD("10baseT", IFM_10_T, PORTSEL_10T);
   2034 	if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A)
   2035 		ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T);
   2036 	ADD("auto", IFM_AUTO, 0);
   2037 	if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A)
   2038 		ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0);
   2039 	aprint_normal("\n");
   2040 
   2041 	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
   2042 }
   2043 
   2044 /*
   2045  * pcn_79c970_mediastatus:	[ifmedia interface function]
   2046  *
   2047  *	Get the current interface media status (Am79c970 version).
   2048  */
   2049 static void
   2050 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   2051 {
   2052 	struct pcn_softc *sc = ifp->if_softc;
   2053 
   2054 	/*
   2055 	 * The currently selected media is always the active media.
   2056 	 * Note: We have no way to determine what media the AUTO
   2057 	 * process picked.
   2058 	 */
   2059 	ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media;
   2060 }
   2061 
   2062 /*
   2063  * pcn_79c970_mediachange:	[ifmedia interface function]
   2064  *
   2065  *	Set hardware to newly-selected media (Am79c970 version).
   2066  */
   2067 static int
   2068 pcn_79c970_mediachange(struct ifnet *ifp)
   2069 {
   2070 	struct pcn_softc *sc = ifp->if_softc;
   2071 	uint32_t reg;
   2072 
   2073 	if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) {
   2074 		/*
   2075 		 * CSR15:PORTSEL doesn't matter.  Just set BCR2:ASEL.
   2076 		 */
   2077 		reg = pcn_bcr_read(sc, LE_BCR2);
   2078 		reg |= LE_B2_ASEL;
   2079 		pcn_bcr_write(sc, LE_BCR2, reg);
   2080 	} else {
   2081 		/*
   2082 		 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value.
   2083 		 */
   2084 		reg = pcn_bcr_read(sc, LE_BCR2);
   2085 		reg &= ~LE_B2_ASEL;
   2086 		pcn_bcr_write(sc, LE_BCR2, reg);
   2087 
   2088 		reg = pcn_csr_read(sc, LE_CSR15);
   2089 		reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) |
   2090 		    LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data);
   2091 		pcn_csr_write(sc, LE_CSR15, reg);
   2092 	}
   2093 
   2094 	if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) {
   2095 		reg = LE_B9_FDEN;
   2096 		if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5)
   2097 			reg |= LE_B9_AUIFD;
   2098 		pcn_bcr_write(sc, LE_BCR9, reg);
   2099 	} else
   2100 		pcn_bcr_write(sc, LE_BCR9, 0);
   2101 
   2102 	return (0);
   2103 }
   2104 
   2105 /*
   2106  * pcn_79c971_mediainit:
   2107  *
   2108  *	Initialize media for the Am79c971.
   2109  */
   2110 static void
   2111 pcn_79c971_mediainit(struct pcn_softc *sc)
   2112 {
   2113 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2114 
   2115 	/* We have MII. */
   2116 	sc->sc_flags |= PCN_F_HAS_MII;
   2117 
   2118 	/*
   2119 	 * The built-in 10BASE-T interface is mapped to the MII
   2120 	 * on the PCNet-FAST.  Unfortunately, there's no EEPROM
   2121 	 * word that tells us which PHY to use.
   2122 	 * This driver used to ignore all but the first PHY to
   2123 	 * answer, but this code was removed to support multiple
   2124 	 * external PHYs. As the default instance will be the first
   2125 	 * one to answer, no harm is done by letting the possibly
   2126 	 * non-connected internal PHY show up.
   2127 	 */
   2128 
   2129 	/* Initialize our media structures and probe the MII. */
   2130 	sc->sc_mii.mii_ifp = ifp;
   2131 	sc->sc_mii.mii_readreg = pcn_mii_readreg;
   2132 	sc->sc_mii.mii_writereg = pcn_mii_writereg;
   2133 	sc->sc_mii.mii_statchg = pcn_mii_statchg;
   2134 
   2135 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   2136 	ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange,
   2137 	    ether_mediastatus);
   2138 
   2139 	mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   2140 	    MII_OFFSET_ANY, 0);
   2141 	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
   2142 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
   2143 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
   2144 	} else
   2145 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
   2146 }
   2147 
   2148 /*
   2149  * pcn_mii_readreg:	[mii interface function]
   2150  *
   2151  *	Read a PHY register on the MII.
   2152  */
   2153 static int
   2154 pcn_mii_readreg(device_t self, int phy, int reg)
   2155 {
   2156 	struct pcn_softc *sc = device_private(self);
   2157 	uint32_t rv;
   2158 
   2159 	pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));
   2160 	rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD;
   2161 	if (rv == 0xffff)
   2162 		return (0);
   2163 
   2164 	return (rv);
   2165 }
   2166 
   2167 /*
   2168  * pcn_mii_writereg:	[mii interface function]
   2169  *
   2170  *	Write a PHY register on the MII.
   2171  */
   2172 static void
   2173 pcn_mii_writereg(device_t self, int phy, int reg, int val)
   2174 {
   2175 	struct pcn_softc *sc = device_private(self);
   2176 
   2177 	pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));
   2178 	pcn_bcr_write(sc, LE_BCR34, val);
   2179 }
   2180 
   2181 /*
   2182  * pcn_mii_statchg:	[mii interface function]
   2183  *
   2184  *	Callback from MII layer when media changes.
   2185  */
   2186 static void
   2187 pcn_mii_statchg(struct ifnet *ifp)
   2188 {
   2189 	struct pcn_softc *sc = ifp->if_softc;
   2190 
   2191 	if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0)
   2192 		pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN);
   2193 	else
   2194 		pcn_bcr_write(sc, LE_BCR9, 0);
   2195 }
   2196