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if_ti.c revision 1.93
      1 /* $NetBSD: if_ti.c,v 1.92 2014/02/27 01:30:42 joerg Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1997, 1998, 1999
      5  *	Bill Paul <wpaul (at) ctr.columbia.edu>.  All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Bill Paul.
     18  * 4. Neither the name of the author nor the names of any co-contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
     26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
     32  * THE POSSIBILITY OF SUCH DAMAGE.
     33  *
     34  *	FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp
     35  */
     36 
     37 /*
     38  * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
     39  * Manuals, sample driver and firmware source kits are available
     40  * from http://www.alteon.com/support/openkits.
     41  *
     42  * Written by Bill Paul <wpaul (at) ctr.columbia.edu>
     43  * Electrical Engineering Department
     44  * Columbia University, New York City
     45  */
     46 
     47 /*
     48  * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
     49  * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
     50  * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
     51  * Tigon supports hardware IP, TCP and UCP checksumming, multicast
     52  * filtering and jumbo (9014 byte) frames. The hardware is largely
     53  * controlled by firmware, which must be loaded into the NIC during
     54  * initialization.
     55  *
     56  * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
     57  * revision, which supports new features such as extended commands,
     58  * extended jumbo receive ring desciptors and a mini receive ring.
     59  *
     60  * Alteon Networks is to be commended for releasing such a vast amount
     61  * of development material for the Tigon NIC without requiring an NDA
     62  * (although they really should have done it a long time ago). With
     63  * any luck, the other vendors will finally wise up and follow Alteon's
     64  * stellar example.
     65  *
     66  * The firmware for the Tigon 1 and 2 NICs is compiled directly into
     67  * this driver by #including it as a C header file. This bloats the
     68  * driver somewhat, but it's the easiest method considering that the
     69  * driver code and firmware code need to be kept in sync. The source
     70  * for the firmware is not provided with the FreeBSD distribution since
     71  * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
     72  *
     73  * The following people deserve special thanks:
     74  * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
     75  *   for testing
     76  * - Raymond Lee of Netgear, for providing a pair of Netgear
     77  *   GA620 Tigon 2 boards for testing
     78  * - Ulf Zimmermann, for bringing the GA620 to my attention and
     79  *   convincing me to write this driver.
     80  * - Andrew Gallatin for providing FreeBSD/Alpha support.
     81  */
     82 
     83 #include <sys/cdefs.h>
     84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.92 2014/02/27 01:30:42 joerg Exp $");
     85 
     86 #include "opt_inet.h"
     87 
     88 #include <sys/param.h>
     89 #include <sys/systm.h>
     90 #include <sys/sockio.h>
     91 #include <sys/mbuf.h>
     92 #include <sys/malloc.h>
     93 #include <sys/kernel.h>
     94 #include <sys/socket.h>
     95 #include <sys/queue.h>
     96 #include <sys/device.h>
     97 #include <sys/reboot.h>
     98 
     99 #include <net/if.h>
    100 #include <net/if_arp.h>
    101 #include <net/if_ether.h>
    102 #include <net/if_dl.h>
    103 #include <net/if_media.h>
    104 
    105 #include <net/bpf.h>
    106 
    107 #ifdef INET
    108 #include <netinet/in.h>
    109 #include <netinet/if_inarp.h>
    110 #include <netinet/in_systm.h>
    111 #include <netinet/ip.h>
    112 #endif
    113 
    114 
    115 #include <sys/bus.h>
    116 
    117 #include <dev/pci/pcireg.h>
    118 #include <dev/pci/pcivar.h>
    119 #include <dev/pci/pcidevs.h>
    120 
    121 #include <dev/pci/if_tireg.h>
    122 
    123 #include <dev/microcode/tigon/ti_fw.h>
    124 #include <dev/microcode/tigon/ti_fw2.h>
    125 
    126 /*
    127  * Various supported device vendors/types and their names.
    128  */
    129 
    130 static const struct ti_type ti_devs[] = {
    131 	{ PCI_VENDOR_ALTEON,	PCI_PRODUCT_ALTEON_ACENIC,
    132 		"Alteon AceNIC 1000BASE-SX Ethernet" },
    133 	{ PCI_VENDOR_ALTEON,	PCI_PRODUCT_ALTEON_ACENIC_COPPER,
    134 		"Alteon AceNIC 1000BASE-T Ethernet" },
    135 	{ PCI_VENDOR_3COM,	PCI_PRODUCT_3COM_3C985,
    136 		"3Com 3c985-SX Gigabit Ethernet" },
    137 	{ PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620,
    138 		"Netgear GA620 1000BASE-SX Ethernet" },
    139 	{ PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T,
    140 		"Netgear GA620 1000BASE-T Ethernet" },
    141 	{ PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON,
    142 		"Silicon Graphics Gigabit Ethernet" },
    143 	{ 0, 0, NULL }
    144 };
    145 
    146 static const struct ti_type *ti_type_match(struct pci_attach_args *);
    147 static int ti_probe(device_t, cfdata_t, void *);
    148 static void ti_attach(device_t, device_t, void *);
    149 static bool ti_shutdown(device_t, int);
    150 static void ti_txeof_tigon1(struct ti_softc *);
    151 static void ti_txeof_tigon2(struct ti_softc *);
    152 static void ti_rxeof(struct ti_softc *);
    153 
    154 static void ti_stats_update(struct ti_softc *);
    155 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *);
    156 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *);
    157 
    158 static int ti_intr(void *);
    159 static void ti_start(struct ifnet *);
    160 static int ti_ioctl(struct ifnet *, u_long, void *);
    161 static void ti_init(void *);
    162 static void ti_init2(struct ti_softc *);
    163 static void ti_stop(struct ti_softc *);
    164 static void ti_watchdog(struct ifnet *);
    165 static int ti_ifmedia_upd(struct ifnet *);
    166 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
    167 
    168 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
    169 static u_int8_t	ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
    170 static int ti_read_eeprom(struct ti_softc *, void *, int, int);
    171 
    172 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
    173 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
    174 static void ti_setmulti(struct ti_softc *);
    175 
    176 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, const void *);
    177 static void ti_loadfw(struct ti_softc *);
    178 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
    179 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int);
    180 static void ti_handle_events(struct ti_softc *);
    181 static int ti_alloc_jumbo_mem(struct ti_softc *);
    182 static void *ti_jalloc(struct ti_softc *);
    183 static void ti_jfree(struct mbuf *, void *, size_t, void *);
    184 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t);
    185 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t);
    186 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
    187 static int ti_init_rx_ring_std(struct ti_softc *);
    188 static void ti_free_rx_ring_std(struct ti_softc *);
    189 static int ti_init_rx_ring_jumbo(struct ti_softc *);
    190 static void ti_free_rx_ring_jumbo(struct ti_softc *);
    191 static int ti_init_rx_ring_mini(struct ti_softc *);
    192 static void ti_free_rx_ring_mini(struct ti_softc *);
    193 static void ti_free_tx_ring(struct ti_softc *);
    194 static int ti_init_tx_ring(struct ti_softc *);
    195 
    196 static int ti_64bitslot_war(struct ti_softc *);
    197 static int ti_chipinit(struct ti_softc *);
    198 static int ti_gibinit(struct ti_softc *);
    199 
    200 static int ti_ether_ioctl(struct ifnet *, u_long, void *);
    201 
    202 CFATTACH_DECL_NEW(ti, sizeof(struct ti_softc),
    203     ti_probe, ti_attach, NULL, NULL);
    204 
    205 /*
    206  * Send an instruction or address to the EEPROM, check for ACK.
    207  */
    208 static u_int32_t
    209 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
    210 {
    211 	int i, ack = 0;
    212 
    213 	/*
    214 	 * Make sure we're in TX mode.
    215 	 */
    216 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
    217 
    218 	/*
    219 	 * Feed in each bit and stobe the clock.
    220 	 */
    221 	for (i = 0x80; i; i >>= 1) {
    222 		if (byte & i) {
    223 			TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
    224 		} else {
    225 			TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
    226 		}
    227 		DELAY(1);
    228 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
    229 		DELAY(1);
    230 		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
    231 	}
    232 
    233 	/*
    234 	 * Turn off TX mode.
    235 	 */
    236 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
    237 
    238 	/*
    239 	 * Check for ack.
    240 	 */
    241 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
    242 	ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
    243 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
    244 
    245 	return (ack);
    246 }
    247 
    248 /*
    249  * Read a byte of data stored in the EEPROM at address 'addr.'
    250  * We have to send two address bytes since the EEPROM can hold
    251  * more than 256 bytes of data.
    252  */
    253 static u_int8_t
    254 ti_eeprom_getbyte(struct ti_softc *sc, int addr, u_int8_t *dest)
    255 {
    256 	int		i;
    257 	u_int8_t		byte = 0;
    258 
    259 	EEPROM_START();
    260 
    261 	/*
    262 	 * Send write control code to EEPROM.
    263 	 */
    264 	if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
    265 		printf("%s: failed to send write command, status: %x\n",
    266 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
    267 		return (1);
    268 	}
    269 
    270 	/*
    271 	 * Send first byte of address of byte we want to read.
    272 	 */
    273 	if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
    274 		printf("%s: failed to send address, status: %x\n",
    275 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
    276 		return (1);
    277 	}
    278 	/*
    279 	 * Send second byte address of byte we want to read.
    280 	 */
    281 	if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
    282 		printf("%s: failed to send address, status: %x\n",
    283 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
    284 		return (1);
    285 	}
    286 
    287 	EEPROM_STOP();
    288 	EEPROM_START();
    289 	/*
    290 	 * Send read control code to EEPROM.
    291 	 */
    292 	if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
    293 		printf("%s: failed to send read command, status: %x\n",
    294 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
    295 		return (1);
    296 	}
    297 
    298 	/*
    299 	 * Start reading bits from EEPROM.
    300 	 */
    301 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
    302 	for (i = 0x80; i; i >>= 1) {
    303 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
    304 		DELAY(1);
    305 		if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
    306 			byte |= i;
    307 		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
    308 		DELAY(1);
    309 	}
    310 
    311 	EEPROM_STOP();
    312 
    313 	/*
    314 	 * No ACK generated for read, so just return byte.
    315 	 */
    316 
    317 	*dest = byte;
    318 
    319 	return (0);
    320 }
    321 
    322 /*
    323  * Read a sequence of bytes from the EEPROM.
    324  */
    325 static int
    326 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt)
    327 {
    328 	char *dest = destv;
    329 	int err = 0, i;
    330 	u_int8_t byte = 0;
    331 
    332 	for (i = 0; i < cnt; i++) {
    333 		err = ti_eeprom_getbyte(sc, off + i, &byte);
    334 		if (err)
    335 			break;
    336 		*(dest + i) = byte;
    337 	}
    338 
    339 	return (err ? 1 : 0);
    340 }
    341 
    342 /*
    343  * NIC memory access function. Can be used to either clear a section
    344  * of NIC local memory or (if tbuf is non-NULL) copy data into it.
    345  */
    346 static void
    347 ti_mem(struct ti_softc *sc, u_int32_t addr, u_int32_t len, const void *xbuf)
    348 {
    349 	int			segptr, segsize, cnt;
    350 	const void		*ptr;
    351 
    352 	segptr = addr;
    353 	cnt = len;
    354 	ptr = xbuf;
    355 
    356 	while (cnt) {
    357 		if (cnt < TI_WINLEN)
    358 			segsize = cnt;
    359 		else
    360 			segsize = TI_WINLEN - (segptr % TI_WINLEN);
    361 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
    362 		if (xbuf == NULL) {
    363 			bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
    364 			    TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0,
    365 			    segsize / 4);
    366 		} else {
    367 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
    368 			bus_space_write_region_stream_4(sc->ti_btag,
    369 			    sc->ti_bhandle,
    370 			    TI_WINDOW + (segptr & (TI_WINLEN - 1)),
    371 			    (const u_int32_t *)ptr, segsize / 4);
    372 #else
    373 			bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
    374 			    TI_WINDOW + (segptr & (TI_WINLEN - 1)),
    375 			    (const u_int32_t *)ptr, segsize / 4);
    376 #endif
    377 			ptr = (const char *)ptr + segsize;
    378 		}
    379 		segptr += segsize;
    380 		cnt -= segsize;
    381 	}
    382 
    383 	return;
    384 }
    385 
    386 /*
    387  * Load firmware image into the NIC. Check that the firmware revision
    388  * is acceptable and see if we want the firmware for the Tigon 1 or
    389  * Tigon 2.
    390  */
    391 static void
    392 ti_loadfw(struct ti_softc *sc)
    393 {
    394 	switch (sc->ti_hwrev) {
    395 	case TI_HWREV_TIGON:
    396 		if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
    397 		    tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
    398 		    tigonFwReleaseFix != TI_FIRMWARE_FIX) {
    399 			printf("%s: firmware revision mismatch; want "
    400 			    "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev),
    401 			    TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
    402 			    TI_FIRMWARE_FIX, tigonFwReleaseMajor,
    403 			    tigonFwReleaseMinor, tigonFwReleaseFix);
    404 			return;
    405 		}
    406 		ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
    407 		ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
    408 		ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata);
    409 		ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
    410 		ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
    411 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
    412 		break;
    413 	case TI_HWREV_TIGON_II:
    414 		if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
    415 		    tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
    416 		    tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
    417 			printf("%s: firmware revision mismatch; want "
    418 			    "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev),
    419 			    TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
    420 			    TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
    421 			    tigon2FwReleaseMinor, tigon2FwReleaseFix);
    422 			return;
    423 		}
    424 		ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText);
    425 		ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData);
    426 		ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
    427 		    tigon2FwRodata);
    428 		ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
    429 		ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
    430 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
    431 		break;
    432 	default:
    433 		printf("%s: can't load firmware: unknown hardware rev\n",
    434 		    device_xname(sc->sc_dev));
    435 		break;
    436 	}
    437 
    438 	return;
    439 }
    440 
    441 /*
    442  * Send the NIC a command via the command ring.
    443  */
    444 static void
    445 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
    446 {
    447 	u_int32_t		index;
    448 
    449 	index = sc->ti_cmd_saved_prodidx;
    450 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
    451 	TI_INC(index, TI_CMD_RING_CNT);
    452 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
    453 	sc->ti_cmd_saved_prodidx = index;
    454 }
    455 
    456 /*
    457  * Send the NIC an extended command. The 'len' parameter specifies the
    458  * number of command slots to include after the initial command.
    459  */
    460 static void
    461 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len)
    462 {
    463 	char *arg = argv;
    464 	u_int32_t		index;
    465 	int		i;
    466 
    467 	index = sc->ti_cmd_saved_prodidx;
    468 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
    469 	TI_INC(index, TI_CMD_RING_CNT);
    470 	for (i = 0; i < len; i++) {
    471 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
    472 		    *(u_int32_t *)(&arg[i * 4]));
    473 		TI_INC(index, TI_CMD_RING_CNT);
    474 	}
    475 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
    476 	sc->ti_cmd_saved_prodidx = index;
    477 }
    478 
    479 /*
    480  * Handle events that have triggered interrupts.
    481  */
    482 static void
    483 ti_handle_events(struct ti_softc *sc)
    484 {
    485 	struct ti_event_desc	*e;
    486 
    487 	while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
    488 		e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
    489 		switch (TI_EVENT_EVENT(e)) {
    490 		case TI_EV_LINKSTAT_CHANGED:
    491 			sc->ti_linkstat = TI_EVENT_CODE(e);
    492 			if (sc->ti_linkstat == TI_EV_CODE_LINK_UP)
    493 				printf("%s: 10/100 link up\n",
    494 				       device_xname(sc->sc_dev));
    495 			else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
    496 				printf("%s: gigabit link up\n",
    497 				       device_xname(sc->sc_dev));
    498 			else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
    499 				printf("%s: link down\n",
    500 				       device_xname(sc->sc_dev));
    501 			break;
    502 		case TI_EV_ERROR:
    503 			if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
    504 				printf("%s: invalid command\n",
    505 				       device_xname(sc->sc_dev));
    506 			else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
    507 				printf("%s: unknown command\n",
    508 				       device_xname(sc->sc_dev));
    509 			else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
    510 				printf("%s: bad config data\n",
    511 				       device_xname(sc->sc_dev));
    512 			break;
    513 		case TI_EV_FIRMWARE_UP:
    514 			ti_init2(sc);
    515 			break;
    516 		case TI_EV_STATS_UPDATED:
    517 			ti_stats_update(sc);
    518 			break;
    519 		case TI_EV_RESET_JUMBO_RING:
    520 		case TI_EV_MCAST_UPDATED:
    521 			/* Who cares. */
    522 			break;
    523 		default:
    524 			printf("%s: unknown event: %d\n",
    525 			    device_xname(sc->sc_dev), TI_EVENT_EVENT(e));
    526 			break;
    527 		}
    528 		/* Advance the consumer index. */
    529 		TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
    530 		CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
    531 	}
    532 
    533 	return;
    534 }
    535 
    536 /*
    537  * Memory management for the jumbo receive ring is a pain in the
    538  * butt. We need to allocate at least 9018 bytes of space per frame,
    539  * _and_ it has to be contiguous (unless you use the extended
    540  * jumbo descriptor format). Using malloc() all the time won't
    541  * work: malloc() allocates memory in powers of two, which means we
    542  * would end up wasting a considerable amount of space by allocating
    543  * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
    544  * to do our own memory management.
    545  *
    546  * The driver needs to allocate a contiguous chunk of memory at boot
    547  * time. We then chop this up ourselves into 9K pieces and use them
    548  * as external mbuf storage.
    549  *
    550  * One issue here is how much memory to allocate. The jumbo ring has
    551  * 256 slots in it, but at 9K per slot than can consume over 2MB of
    552  * RAM. This is a bit much, especially considering we also need
    553  * RAM for the standard ring and mini ring (on the Tigon 2). To
    554  * save space, we only actually allocate enough memory for 64 slots
    555  * by default, which works out to between 500 and 600K. This can
    556  * be tuned by changing a #define in if_tireg.h.
    557  */
    558 
    559 static int
    560 ti_alloc_jumbo_mem(struct ti_softc *sc)
    561 {
    562 	char *ptr;
    563 	int i;
    564 	struct ti_jpool_entry   *entry;
    565 	bus_dma_segment_t dmaseg;
    566 	int error, dmanseg;
    567 
    568 	/* Grab a big chunk o' storage. */
    569 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
    570 	    TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg,
    571 	    BUS_DMA_NOWAIT)) != 0) {
    572 		aprint_error_dev(sc->sc_dev, "can't allocate jumbo buffer, error = %d\n",
    573 		       error);
    574 		return (error);
    575 	}
    576 
    577 	if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg,
    578 	    TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf,
    579 	    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
    580 		aprint_error_dev(sc->sc_dev, "can't map jumbo buffer, error = %d\n",
    581 		       error);
    582 		return (error);
    583 	}
    584 
    585 	if ((error = bus_dmamap_create(sc->sc_dmat,
    586 	    TI_JMEM, 1,
    587 	    TI_JMEM, 0, BUS_DMA_NOWAIT,
    588 	    &sc->jumbo_dmamap)) != 0) {
    589 		aprint_error_dev(sc->sc_dev, "can't create jumbo buffer DMA map, error = %d\n",
    590 		       error);
    591 		return (error);
    592 	}
    593 
    594 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap,
    595 	    sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL,
    596 	    BUS_DMA_NOWAIT)) != 0) {
    597 		aprint_error_dev(sc->sc_dev, "can't load jumbo buffer DMA map, error = %d\n",
    598 		       error);
    599 		return (error);
    600 	}
    601 	sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr;
    602 
    603 	SIMPLEQ_INIT(&sc->ti_jfree_listhead);
    604 	SIMPLEQ_INIT(&sc->ti_jinuse_listhead);
    605 
    606 	/*
    607 	 * Now divide it up into 9K pieces and save the addresses
    608 	 * in an array.
    609 	 */
    610 	ptr = sc->ti_cdata.ti_jumbo_buf;
    611 	for (i = 0; i < TI_JSLOTS; i++) {
    612 		sc->ti_cdata.ti_jslots[i] = ptr;
    613 		ptr += TI_JLEN;
    614 		entry = malloc(sizeof(struct ti_jpool_entry),
    615 			       M_DEVBUF, M_NOWAIT);
    616 		if (entry == NULL) {
    617 			free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF);
    618 			sc->ti_cdata.ti_jumbo_buf = NULL;
    619 			printf("%s: no memory for jumbo "
    620 			    "buffer queue!\n", device_xname(sc->sc_dev));
    621 			return (ENOBUFS);
    622 		}
    623 		entry->slot = i;
    624 		SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry,
    625 				    jpool_entries);
    626 	}
    627 
    628 	return (0);
    629 }
    630 
    631 /*
    632  * Allocate a jumbo buffer.
    633  */
    634 static void *
    635 ti_jalloc(struct ti_softc *sc)
    636 {
    637 	struct ti_jpool_entry   *entry;
    638 
    639 	entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead);
    640 
    641 	if (entry == NULL) {
    642 		printf("%s: no free jumbo buffers\n", device_xname(sc->sc_dev));
    643 		return (NULL);
    644 	}
    645 
    646 	SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
    647 	SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
    648 
    649 	return (sc->ti_cdata.ti_jslots[entry->slot]);
    650 }
    651 
    652 /*
    653  * Release a jumbo buffer.
    654  */
    655 static void
    656 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg)
    657 {
    658 	struct ti_softc		*sc;
    659 	int		        i, s;
    660 	struct ti_jpool_entry   *entry;
    661 
    662 	/* Extract the softc struct pointer. */
    663 	sc = (struct ti_softc *)arg;
    664 
    665 	if (sc == NULL)
    666 		panic("ti_jfree: didn't get softc pointer!");
    667 
    668 	/* calculate the slot this buffer belongs to */
    669 
    670 	i = ((char *)tbuf
    671 	     - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
    672 
    673 	if ((i < 0) || (i >= TI_JSLOTS))
    674 		panic("ti_jfree: asked to free buffer that we don't manage!");
    675 
    676 	s = splvm();
    677 	entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead);
    678 	if (entry == NULL)
    679 		panic("ti_jfree: buffer not in use!");
    680 	entry->slot = i;
    681 	SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
    682 	SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
    683 
    684 	if (__predict_true(m != NULL))
    685 		pool_cache_put(mb_cache, m);
    686 	splx(s);
    687 }
    688 
    689 
    690 /*
    691  * Intialize a standard receive ring descriptor.
    692  */
    693 static int
    694 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap)
    695 {
    696 	struct mbuf		*m_new = NULL;
    697 	struct ti_rx_desc	*r;
    698 	int error;
    699 
    700 	if (dmamap == NULL) {
    701 		/* if (m) panic() */
    702 
    703 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
    704 					       MCLBYTES, 0, BUS_DMA_NOWAIT,
    705 					       &dmamap)) != 0) {
    706 			aprint_error_dev(sc->sc_dev, "can't create recv map, error = %d\n",
    707 			       error);
    708 			return (ENOMEM);
    709 		}
    710 	}
    711 	sc->std_dmamap[i] = dmamap;
    712 
    713 	if (m == NULL) {
    714 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
    715 		if (m_new == NULL) {
    716 			aprint_error_dev(sc->sc_dev, "mbuf allocation failed "
    717 			    "-- packet dropped!\n");
    718 			return (ENOBUFS);
    719 		}
    720 
    721 		MCLGET(m_new, M_DONTWAIT);
    722 		if (!(m_new->m_flags & M_EXT)) {
    723 			aprint_error_dev(sc->sc_dev, "cluster allocation failed "
    724 			    "-- packet dropped!\n");
    725 			m_freem(m_new);
    726 			return (ENOBUFS);
    727 		}
    728 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
    729 		m_adj(m_new, ETHER_ALIGN);
    730 
    731 		if ((error = bus_dmamap_load(sc->sc_dmat, dmamap,
    732 				mtod(m_new, void *), m_new->m_len, NULL,
    733 				BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) {
    734 			aprint_error_dev(sc->sc_dev, "can't load recv map, error = %d\n",
    735 			       error);
    736 			return (ENOMEM);
    737 		}
    738 	} else {
    739 		m_new = m;
    740 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
    741 		m_new->m_data = m_new->m_ext.ext_buf;
    742 		m_adj(m_new, ETHER_ALIGN);
    743 
    744 		/* reuse the dmamap */
    745 	}
    746 
    747 	sc->ti_cdata.ti_rx_std_chain[i] = m_new;
    748 	r = &sc->ti_rdata->ti_rx_std_ring[i];
    749 	TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr;
    750 	r->ti_type = TI_BDTYPE_RECV_BD;
    751 	r->ti_flags = 0;
    752 	if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
    753 		r->ti_flags |= TI_BDFLAG_IP_CKSUM;
    754 	if (sc->ethercom.ec_if.if_capenable &
    755 	    (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
    756 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
    757 	r->ti_len = m_new->m_len; /* == ds_len */
    758 	r->ti_idx = i;
    759 
    760 	return (0);
    761 }
    762 
    763 /*
    764  * Intialize a mini receive ring descriptor. This only applies to
    765  * the Tigon 2.
    766  */
    767 static int
    768 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap)
    769 {
    770 	struct mbuf		*m_new = NULL;
    771 	struct ti_rx_desc	*r;
    772 	int error;
    773 
    774 	if (dmamap == NULL) {
    775 		/* if (m) panic() */
    776 
    777 		if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1,
    778 					       MHLEN, 0, BUS_DMA_NOWAIT,
    779 					       &dmamap)) != 0) {
    780 			aprint_error_dev(sc->sc_dev, "can't create recv map, error = %d\n",
    781 			       error);
    782 			return (ENOMEM);
    783 		}
    784 	}
    785 	sc->mini_dmamap[i] = dmamap;
    786 
    787 	if (m == NULL) {
    788 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
    789 		if (m_new == NULL) {
    790 			aprint_error_dev(sc->sc_dev, "mbuf allocation failed "
    791 			    "-- packet dropped!\n");
    792 			return (ENOBUFS);
    793 		}
    794 		m_new->m_len = m_new->m_pkthdr.len = MHLEN;
    795 		m_adj(m_new, ETHER_ALIGN);
    796 
    797 		if ((error = bus_dmamap_load(sc->sc_dmat, dmamap,
    798 				mtod(m_new, void *), m_new->m_len, NULL,
    799 				BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) {
    800 			aprint_error_dev(sc->sc_dev, "can't load recv map, error = %d\n",
    801 			       error);
    802 			return (ENOMEM);
    803 		}
    804 	} else {
    805 		m_new = m;
    806 		m_new->m_data = m_new->m_pktdat;
    807 		m_new->m_len = m_new->m_pkthdr.len = MHLEN;
    808 		m_adj(m_new, ETHER_ALIGN);
    809 
    810 		/* reuse the dmamap */
    811 	}
    812 
    813 	r = &sc->ti_rdata->ti_rx_mini_ring[i];
    814 	sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
    815 	TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr;
    816 	r->ti_type = TI_BDTYPE_RECV_BD;
    817 	r->ti_flags = TI_BDFLAG_MINI_RING;
    818 	if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
    819 		r->ti_flags |= TI_BDFLAG_IP_CKSUM;
    820 	if (sc->ethercom.ec_if.if_capenable &
    821 	    (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
    822 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
    823 	r->ti_len = m_new->m_len; /* == ds_len */
    824 	r->ti_idx = i;
    825 
    826 	return (0);
    827 }
    828 
    829 /*
    830  * Initialize a jumbo receive ring descriptor. This allocates
    831  * a jumbo buffer from the pool managed internally by the driver.
    832  */
    833 static int
    834 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
    835 {
    836 	struct mbuf		*m_new = NULL;
    837 	struct ti_rx_desc	*r;
    838 
    839 	if (m == NULL) {
    840 		void *			tbuf = NULL;
    841 
    842 		/* Allocate the mbuf. */
    843 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
    844 		if (m_new == NULL) {
    845 			aprint_error_dev(sc->sc_dev, "mbuf allocation failed "
    846 			    "-- packet dropped!\n");
    847 			return (ENOBUFS);
    848 		}
    849 
    850 		/* Allocate the jumbo buffer */
    851 		tbuf = ti_jalloc(sc);
    852 		if (tbuf == NULL) {
    853 			m_freem(m_new);
    854 			aprint_error_dev(sc->sc_dev, "jumbo allocation failed "
    855 			    "-- packet dropped!\n");
    856 			return (ENOBUFS);
    857 		}
    858 
    859 		/* Attach the buffer to the mbuf. */
    860 		MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO,
    861 		    M_DEVBUF, ti_jfree, sc);
    862 		m_new->m_flags |= M_EXT_RW;
    863 		m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO;
    864 	} else {
    865 		m_new = m;
    866 		m_new->m_data = m_new->m_ext.ext_buf;
    867 		m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO;
    868 	}
    869 
    870 	m_adj(m_new, ETHER_ALIGN);
    871 	/* Set up the descriptor. */
    872 	r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
    873 	sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
    874 	TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr +
    875 		(mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf);
    876 	r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
    877 	r->ti_flags = TI_BDFLAG_JUMBO_RING;
    878 	if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
    879 		r->ti_flags |= TI_BDFLAG_IP_CKSUM;
    880 	if (sc->ethercom.ec_if.if_capenable &
    881 	    (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
    882 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
    883 	r->ti_len = m_new->m_len;
    884 	r->ti_idx = i;
    885 
    886 	return (0);
    887 }
    888 
    889 /*
    890  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
    891  * that's 1MB or memory, which is a lot. For now, we fill only the first
    892  * 256 ring entries and hope that our CPU is fast enough to keep up with
    893  * the NIC.
    894  */
    895 static int
    896 ti_init_rx_ring_std(struct ti_softc *sc)
    897 {
    898 	int		i;
    899 	struct ti_cmd_desc	cmd;
    900 
    901 	for (i = 0; i < TI_SSLOTS; i++) {
    902 		if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
    903 			return (ENOBUFS);
    904 	};
    905 
    906 	TI_UPDATE_STDPROD(sc, i - 1);
    907 	sc->ti_std = i - 1;
    908 
    909 	return (0);
    910 }
    911 
    912 static void
    913 ti_free_rx_ring_std(struct ti_softc *sc)
    914 {
    915 	int		i;
    916 
    917 	for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
    918 		if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
    919 			m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
    920 			sc->ti_cdata.ti_rx_std_chain[i] = NULL;
    921 
    922 			/* if (sc->std_dmamap[i] == 0) panic() */
    923 			bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]);
    924 			sc->std_dmamap[i] = 0;
    925 		}
    926 		memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0,
    927 		    sizeof(struct ti_rx_desc));
    928 	}
    929 
    930 	return;
    931 }
    932 
    933 static int
    934 ti_init_rx_ring_jumbo(struct ti_softc *sc)
    935 {
    936 	int		i;
    937 	struct ti_cmd_desc	cmd;
    938 
    939 	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
    940 		if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
    941 			return (ENOBUFS);
    942 	};
    943 
    944 	TI_UPDATE_JUMBOPROD(sc, i - 1);
    945 	sc->ti_jumbo = i - 1;
    946 
    947 	return (0);
    948 }
    949 
    950 static void
    951 ti_free_rx_ring_jumbo(struct ti_softc *sc)
    952 {
    953 	int		i;
    954 
    955 	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
    956 		if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
    957 			m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
    958 			sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
    959 		}
    960 		memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0,
    961 		    sizeof(struct ti_rx_desc));
    962 	}
    963 
    964 	return;
    965 }
    966 
    967 static int
    968 ti_init_rx_ring_mini(struct ti_softc *sc)
    969 {
    970 	int		i;
    971 
    972 	for (i = 0; i < TI_MSLOTS; i++) {
    973 		if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS)
    974 			return (ENOBUFS);
    975 	};
    976 
    977 	TI_UPDATE_MINIPROD(sc, i - 1);
    978 	sc->ti_mini = i - 1;
    979 
    980 	return (0);
    981 }
    982 
    983 static void
    984 ti_free_rx_ring_mini(struct ti_softc *sc)
    985 {
    986 	int		i;
    987 
    988 	for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
    989 		if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
    990 			m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
    991 			sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
    992 
    993 			/* if (sc->mini_dmamap[i] == 0) panic() */
    994 			bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]);
    995 			sc->mini_dmamap[i] = 0;
    996 		}
    997 		memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0,
    998 		    sizeof(struct ti_rx_desc));
    999 	}
   1000 
   1001 	return;
   1002 }
   1003 
   1004 static void
   1005 ti_free_tx_ring(struct ti_softc *sc)
   1006 {
   1007 	int		i;
   1008 	struct txdmamap_pool_entry *dma;
   1009 
   1010 	for (i = 0; i < TI_TX_RING_CNT; i++) {
   1011 		if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
   1012 			m_freem(sc->ti_cdata.ti_tx_chain[i]);
   1013 			sc->ti_cdata.ti_tx_chain[i] = NULL;
   1014 
   1015 			/* if (sc->txdma[i] == 0) panic() */
   1016 			SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
   1017 					    link);
   1018 			sc->txdma[i] = 0;
   1019 		}
   1020 		memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0,
   1021 		    sizeof(struct ti_tx_desc));
   1022 	}
   1023 
   1024 	while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) {
   1025 		SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link);
   1026 		bus_dmamap_destroy(sc->sc_dmat, dma->dmamap);
   1027 		free(dma, M_DEVBUF);
   1028 	}
   1029 
   1030 	return;
   1031 }
   1032 
   1033 static int
   1034 ti_init_tx_ring(struct ti_softc *sc)
   1035 {
   1036 	int i, error;
   1037 	bus_dmamap_t dmamap;
   1038 	struct txdmamap_pool_entry *dma;
   1039 
   1040 	sc->ti_txcnt = 0;
   1041 	sc->ti_tx_saved_considx = 0;
   1042 	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
   1043 
   1044 	SIMPLEQ_INIT(&sc->txdma_list);
   1045 	for (i = 0; i < TI_RSLOTS; i++) {
   1046 		/* I've seen mbufs with 30 fragments. */
   1047 		if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO,
   1048 					       40, ETHER_MAX_LEN_JUMBO, 0,
   1049 					       BUS_DMA_NOWAIT, &dmamap)) != 0) {
   1050 			aprint_error_dev(sc->sc_dev, "can't create tx map, error = %d\n",
   1051 			       error);
   1052 			return (ENOMEM);
   1053 		}
   1054 		dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
   1055 		if (!dma) {
   1056 			aprint_error_dev(sc->sc_dev, "can't alloc txdmamap_pool_entry\n");
   1057 			bus_dmamap_destroy(sc->sc_dmat, dmamap);
   1058 			return (ENOMEM);
   1059 		}
   1060 		dma->dmamap = dmamap;
   1061 		SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link);
   1062 	}
   1063 
   1064 	return (0);
   1065 }
   1066 
   1067 /*
   1068  * The Tigon 2 firmware has a new way to add/delete multicast addresses,
   1069  * but we have to support the old way too so that Tigon 1 cards will
   1070  * work.
   1071  */
   1072 static void
   1073 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
   1074 {
   1075 	struct ti_cmd_desc	cmd;
   1076 	u_int16_t		*m;
   1077 	u_int32_t		ext[2] = {0, 0};
   1078 
   1079 	m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */
   1080 
   1081 	switch (sc->ti_hwrev) {
   1082 	case TI_HWREV_TIGON:
   1083 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
   1084 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
   1085 		TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
   1086 		break;
   1087 	case TI_HWREV_TIGON_II:
   1088 		ext[0] = htons(m[0]);
   1089 		ext[1] = (htons(m[1]) << 16) | htons(m[2]);
   1090 		TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2);
   1091 		break;
   1092 	default:
   1093 		printf("%s: unknown hwrev\n", device_xname(sc->sc_dev));
   1094 		break;
   1095 	}
   1096 
   1097 	return;
   1098 }
   1099 
   1100 static void
   1101 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
   1102 {
   1103 	struct ti_cmd_desc	cmd;
   1104 	u_int16_t		*m;
   1105 	u_int32_t		ext[2] = {0, 0};
   1106 
   1107 	m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */
   1108 
   1109 	switch (sc->ti_hwrev) {
   1110 	case TI_HWREV_TIGON:
   1111 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
   1112 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
   1113 		TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
   1114 		break;
   1115 	case TI_HWREV_TIGON_II:
   1116 		ext[0] = htons(m[0]);
   1117 		ext[1] = (htons(m[1]) << 16) | htons(m[2]);
   1118 		TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2);
   1119 		break;
   1120 	default:
   1121 		printf("%s: unknown hwrev\n", device_xname(sc->sc_dev));
   1122 		break;
   1123 	}
   1124 
   1125 	return;
   1126 }
   1127 
   1128 /*
   1129  * Configure the Tigon's multicast address filter.
   1130  *
   1131  * The actual multicast table management is a bit of a pain, thanks to
   1132  * slight brain damage on the part of both Alteon and us. With our
   1133  * multicast code, we are only alerted when the multicast address table
   1134  * changes and at that point we only have the current list of addresses:
   1135  * we only know the current state, not the previous state, so we don't
   1136  * actually know what addresses were removed or added. The firmware has
   1137  * state, but we can't get our grubby mits on it, and there is no 'delete
   1138  * all multicast addresses' command. Hence, we have to maintain our own
   1139  * state so we know what addresses have been programmed into the NIC at
   1140  * any given time.
   1141  */
   1142 static void
   1143 ti_setmulti(struct ti_softc *sc)
   1144 {
   1145 	struct ifnet		*ifp;
   1146 	struct ti_cmd_desc	cmd;
   1147 	struct ti_mc_entry	*mc;
   1148 	u_int32_t		intrs;
   1149 	struct ether_multi *enm;
   1150 	struct ether_multistep step;
   1151 
   1152 	ifp = &sc->ethercom.ec_if;
   1153 
   1154 	/* Disable interrupts. */
   1155 	intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
   1156 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
   1157 
   1158 	/* First, zot all the existing filters. */
   1159 	while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) {
   1160 		ti_del_mcast(sc, &mc->mc_addr);
   1161 		SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
   1162 		free(mc, M_DEVBUF);
   1163 	}
   1164 
   1165 	/*
   1166 	 * Remember all multicast addresses so that we can delete them
   1167 	 * later.  Punt if there is a range of addresses or memory shortage.
   1168 	 */
   1169 	ETHER_FIRST_MULTI(step, &sc->ethercom, enm);
   1170 	while (enm != NULL) {
   1171 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
   1172 		    ETHER_ADDR_LEN) != 0)
   1173 			goto allmulti;
   1174 		if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF,
   1175 		    M_NOWAIT)) == NULL)
   1176 			goto allmulti;
   1177 		memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN);
   1178 		SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
   1179 		ETHER_NEXT_MULTI(step, enm);
   1180 	}
   1181 
   1182 	/* Accept only programmed multicast addresses */
   1183 	ifp->if_flags &= ~IFF_ALLMULTI;
   1184 	TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
   1185 
   1186 	/* Now program new ones. */
   1187 	SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries)
   1188 		ti_add_mcast(sc, &mc->mc_addr);
   1189 
   1190 	/* Re-enable interrupts. */
   1191 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
   1192 
   1193 	return;
   1194 
   1195 allmulti:
   1196 	/* No need to keep individual multicast addresses */
   1197 	while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) {
   1198 		SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
   1199 		free(mc, M_DEVBUF);
   1200 	}
   1201 
   1202 	/* Accept all multicast addresses */
   1203 	ifp->if_flags |= IFF_ALLMULTI;
   1204 	TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
   1205 
   1206 	/* Re-enable interrupts. */
   1207 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
   1208 }
   1209 
   1210 /*
   1211  * Check to see if the BIOS has configured us for a 64 bit slot when
   1212  * we aren't actually in one. If we detect this condition, we can work
   1213  * around it on the Tigon 2 by setting a bit in the PCI state register,
   1214  * but for the Tigon 1 we must give up and abort the interface attach.
   1215  */
   1216 static int
   1217 ti_64bitslot_war(struct ti_softc *sc)
   1218 {
   1219 	if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
   1220 		CSR_WRITE_4(sc, 0x600, 0);
   1221 		CSR_WRITE_4(sc, 0x604, 0);
   1222 		CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
   1223 		if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
   1224 			if (sc->ti_hwrev == TI_HWREV_TIGON)
   1225 				return (EINVAL);
   1226 			else {
   1227 				TI_SETBIT(sc, TI_PCI_STATE,
   1228 				    TI_PCISTATE_32BIT_BUS);
   1229 				return (0);
   1230 			}
   1231 		}
   1232 	}
   1233 
   1234 	return (0);
   1235 }
   1236 
   1237 /*
   1238  * Do endian, PCI and DMA initialization. Also check the on-board ROM
   1239  * self-test results.
   1240  */
   1241 static int
   1242 ti_chipinit(struct ti_softc *sc)
   1243 {
   1244 	u_int32_t		cacheline;
   1245 	u_int32_t		pci_writemax = 0;
   1246 	u_int32_t		rev;
   1247 
   1248 	/* Initialize link to down state. */
   1249 	sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
   1250 
   1251 	/* Set endianness before we access any non-PCI registers. */
   1252 #if BYTE_ORDER == BIG_ENDIAN
   1253 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
   1254 	    TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
   1255 #else
   1256 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
   1257 	    TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
   1258 #endif
   1259 
   1260 	/* Check the ROM failed bit to see if self-tests passed. */
   1261 	if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
   1262 		printf("%s: board self-diagnostics failed!\n",
   1263 		       device_xname(sc->sc_dev));
   1264 		return (ENODEV);
   1265 	}
   1266 
   1267 	/* Halt the CPU. */
   1268 	TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
   1269 
   1270 	/* Figure out the hardware revision. */
   1271 	rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK;
   1272 	switch (rev) {
   1273 	case TI_REV_TIGON_I:
   1274 		sc->ti_hwrev = TI_HWREV_TIGON;
   1275 		break;
   1276 	case TI_REV_TIGON_II:
   1277 		sc->ti_hwrev = TI_HWREV_TIGON_II;
   1278 		break;
   1279 	default:
   1280 		printf("%s: unsupported chip revision 0x%x\n",
   1281 		    device_xname(sc->sc_dev), rev);
   1282 		return (ENODEV);
   1283 	}
   1284 
   1285 	/* Do special setup for Tigon 2. */
   1286 	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
   1287 		TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
   1288 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
   1289 		TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
   1290 	}
   1291 
   1292 	/* Set up the PCI state register. */
   1293 	CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
   1294 	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
   1295 		TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
   1296 	}
   1297 
   1298 	/* Clear the read/write max DMA parameters. */
   1299 	TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
   1300 	    TI_PCISTATE_READ_MAXDMA));
   1301 
   1302 	/* Get cache line size. */
   1303 	cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG));
   1304 
   1305 	/*
   1306 	 * If the system has set enabled the PCI memory write
   1307 	 * and invalidate command in the command register, set
   1308 	 * the write max parameter accordingly. This is necessary
   1309 	 * to use MWI with the Tigon 2.
   1310 	 */
   1311 	if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)
   1312 	    & PCI_COMMAND_INVALIDATE_ENABLE) {
   1313 		switch (cacheline) {
   1314 		case 1:
   1315 		case 4:
   1316 		case 8:
   1317 		case 16:
   1318 		case 32:
   1319 		case 64:
   1320 			break;
   1321 		default:
   1322 		/* Disable PCI memory write and invalidate. */
   1323 			if (bootverbose)
   1324 				printf("%s: cache line size %d not "
   1325 				    "supported; disabling PCI MWI\n",
   1326 				    device_xname(sc->sc_dev), cacheline);
   1327 			CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG,
   1328 				    CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)
   1329 				    & ~PCI_COMMAND_INVALIDATE_ENABLE);
   1330 			break;
   1331 		}
   1332 	}
   1333 
   1334 #ifdef __brokenalpha__
   1335 	/*
   1336 	 * From the Alteon sample driver:
   1337 	 * Must insure that we do not cross an 8K (bytes) boundary
   1338 	 * for DMA reads.  Our highest limit is 1K bytes.  This is a
   1339 	 * restriction on some ALPHA platforms with early revision
   1340 	 * 21174 PCI chipsets, such as the AlphaPC 164lx
   1341 	 */
   1342 	TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
   1343 #else
   1344 	TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
   1345 #endif
   1346 
   1347 	/* This sets the min dma param all the way up (0xff). */
   1348 	TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
   1349 
   1350 	/* Configure DMA variables. */
   1351 #if BYTE_ORDER == BIG_ENDIAN
   1352 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
   1353 	    TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
   1354 	    TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
   1355 	    TI_OPMODE_DONT_FRAG_JUMBO);
   1356 #else
   1357 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
   1358 	    TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
   1359 	    TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
   1360 #endif
   1361 
   1362 	/*
   1363 	 * Only allow 1 DMA channel to be active at a time.
   1364 	 * I don't think this is a good idea, but without it
   1365 	 * the firmware racks up lots of nicDmaReadRingFull
   1366 	 * errors.
   1367 	 * Incompatible with hardware assisted checksums.
   1368 	 */
   1369 	if ((sc->ethercom.ec_if.if_capenable &
   1370 	    (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   1371 	     IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
   1372 	     IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0)
   1373 		TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
   1374 
   1375 	/* Recommended settings from Tigon manual. */
   1376 	CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
   1377 	CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
   1378 
   1379 	if (ti_64bitslot_war(sc)) {
   1380 		printf("%s: bios thinks we're in a 64 bit slot, "
   1381 		    "but we aren't", device_xname(sc->sc_dev));
   1382 		return (EINVAL);
   1383 	}
   1384 
   1385 	return (0);
   1386 }
   1387 
   1388 /*
   1389  * Initialize the general information block and firmware, and
   1390  * start the CPU(s) running.
   1391  */
   1392 static int
   1393 ti_gibinit(struct ti_softc *sc)
   1394 {
   1395 	struct ti_rcb		*rcb;
   1396 	int			i;
   1397 	struct ifnet		*ifp;
   1398 
   1399 	ifp = &sc->ethercom.ec_if;
   1400 
   1401 	/* Disable interrupts for now. */
   1402 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
   1403 
   1404 	/* Tell the chip where to find the general information block. */
   1405 	CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
   1406 	CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc));
   1407 
   1408 	/* Load the firmware into SRAM. */
   1409 	ti_loadfw(sc);
   1410 
   1411 	/* Set up the contents of the general info and ring control blocks. */
   1412 
   1413 	/* Set up the event ring and producer pointer. */
   1414 	rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
   1415 
   1416 	TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0);
   1417 	rcb->ti_flags = 0;
   1418 	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
   1419 	    TI_CDEVPRODADDR(sc);
   1420 
   1421 	sc->ti_ev_prodidx.ti_idx = 0;
   1422 	CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
   1423 	sc->ti_ev_saved_considx = 0;
   1424 
   1425 	/* Set up the command ring and producer mailbox. */
   1426 	rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
   1427 
   1428 	TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
   1429 	rcb->ti_flags = 0;
   1430 	rcb->ti_max_len = 0;
   1431 	for (i = 0; i < TI_CMD_RING_CNT; i++) {
   1432 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
   1433 	}
   1434 	CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
   1435 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
   1436 	sc->ti_cmd_saved_prodidx = 0;
   1437 
   1438 	/*
   1439 	 * Assign the address of the stats refresh buffer.
   1440 	 * We re-use the current stats buffer for this to
   1441 	 * conserve memory.
   1442 	 */
   1443 	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
   1444 	    TI_CDSTATSADDR(sc);
   1445 
   1446 	/* Set up the standard receive ring. */
   1447 	rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
   1448 	TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0);
   1449 	rcb->ti_max_len = ETHER_MAX_LEN;
   1450 	rcb->ti_flags = 0;
   1451 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
   1452 		rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
   1453 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx))
   1454 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
   1455 	if (VLAN_ATTACHED(&sc->ethercom))
   1456 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
   1457 
   1458 	/* Set up the jumbo receive ring. */
   1459 	rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
   1460 	TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0);
   1461 	rcb->ti_max_len = ETHER_MAX_LEN_JUMBO;
   1462 	rcb->ti_flags = 0;
   1463 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
   1464 		rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
   1465 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx))
   1466 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
   1467 	if (VLAN_ATTACHED(&sc->ethercom))
   1468 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
   1469 
   1470 	/*
   1471 	 * Set up the mini ring. Only activated on the
   1472 	 * Tigon 2 but the slot in the config block is
   1473 	 * still there on the Tigon 1.
   1474 	 */
   1475 	rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
   1476 	TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0);
   1477 	rcb->ti_max_len = MHLEN - ETHER_ALIGN;
   1478 	if (sc->ti_hwrev == TI_HWREV_TIGON)
   1479 		rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
   1480 	else
   1481 		rcb->ti_flags = 0;
   1482 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
   1483 		rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
   1484 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx))
   1485 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
   1486 	if (VLAN_ATTACHED(&sc->ethercom))
   1487 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
   1488 
   1489 	/*
   1490 	 * Set up the receive return ring.
   1491 	 */
   1492 	rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
   1493 	TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0);
   1494 	rcb->ti_flags = 0;
   1495 	rcb->ti_max_len = TI_RETURN_RING_CNT;
   1496 	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
   1497 	    TI_CDRTNPRODADDR(sc);
   1498 
   1499 	/*
   1500 	 * Set up the tx ring. Note: for the Tigon 2, we have the option
   1501 	 * of putting the transmit ring in the host's address space and
   1502 	 * letting the chip DMA it instead of leaving the ring in the NIC's
   1503 	 * memory and accessing it through the shared memory region. We
   1504 	 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
   1505 	 * so we have to revert to the shared memory scheme if we detect
   1506 	 * a Tigon 1 chip.
   1507 	 */
   1508 	CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
   1509 	if (sc->ti_hwrev == TI_HWREV_TIGON) {
   1510 		sc->ti_tx_ring_nic =
   1511 		    (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
   1512 	}
   1513 	memset((char *)sc->ti_rdata->ti_tx_ring, 0,
   1514 	    TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
   1515 	rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
   1516 	if (sc->ti_hwrev == TI_HWREV_TIGON)
   1517 		rcb->ti_flags = 0;
   1518 	else
   1519 		rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
   1520 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx)
   1521 		rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
   1522 	/*
   1523 	 * When we get the packet, there is a pseudo-header seed already
   1524 	 * in the th_sum or uh_sum field.  Make sure the firmware doesn't
   1525 	 * compute the pseudo-header checksum again!
   1526 	 */
   1527 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx))
   1528 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|
   1529 		    TI_RCB_FLAG_NO_PHDR_CKSUM;
   1530 	if (VLAN_ATTACHED(&sc->ethercom))
   1531 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
   1532 	rcb->ti_max_len = TI_TX_RING_CNT;
   1533 	if (sc->ti_hwrev == TI_HWREV_TIGON)
   1534 		TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
   1535 	else
   1536 		TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0);
   1537 	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
   1538 	    TI_CDTXCONSADDR(sc);
   1539 
   1540 	/*
   1541 	 * We're done frobbing the General Information Block.  Sync
   1542 	 * it.  Note we take care of the first stats sync here, as
   1543 	 * well.
   1544 	 */
   1545 	TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1546 
   1547 	/* Set up tuneables */
   1548 	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) ||
   1549 	    (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU))
   1550 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
   1551 		    (sc->ti_rx_coal_ticks / 10));
   1552 	else
   1553 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
   1554 	CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
   1555 	CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
   1556 	CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
   1557 	CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
   1558 	CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
   1559 
   1560 	/* Turn interrupts on. */
   1561 	CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
   1562 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
   1563 
   1564 	/* Start CPU. */
   1565 	TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
   1566 
   1567 	return (0);
   1568 }
   1569 
   1570 /*
   1571  * look for id in the device list, returning the first match
   1572  */
   1573 static const struct ti_type *
   1574 ti_type_match(struct pci_attach_args *pa)
   1575 {
   1576 	const struct ti_type          *t;
   1577 
   1578 	t = ti_devs;
   1579 	while (t->ti_name != NULL) {
   1580 		if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) &&
   1581 		    (PCI_PRODUCT(pa->pa_id) == t->ti_did)) {
   1582 			return (t);
   1583 		}
   1584 		t++;
   1585 	}
   1586 
   1587 	return (NULL);
   1588 }
   1589 
   1590 /*
   1591  * Probe for a Tigon chip. Check the PCI vendor and device IDs
   1592  * against our list and return its name if we find a match.
   1593  */
   1594 static int
   1595 ti_probe(device_t parent, cfdata_t match, void *aux)
   1596 {
   1597 	struct pci_attach_args *pa = aux;
   1598 	const struct ti_type		*t;
   1599 
   1600 	t = ti_type_match(pa);
   1601 
   1602 	return ((t == NULL) ? 0 : 1);
   1603 }
   1604 
   1605 static void
   1606 ti_attach(device_t parent, device_t self, void *aux)
   1607 {
   1608 	u_int32_t		command;
   1609 	struct ifnet		*ifp;
   1610 	struct ti_softc		*sc;
   1611 	u_int8_t eaddr[ETHER_ADDR_LEN];
   1612 	struct pci_attach_args *pa = aux;
   1613 	pci_chipset_tag_t pc = pa->pa_pc;
   1614 	pci_intr_handle_t ih;
   1615 	const char *intrstr = NULL;
   1616 	bus_dma_segment_t dmaseg;
   1617 	int error, dmanseg, nolinear;
   1618 	const struct ti_type		*t;
   1619 	char intrbuf[PCI_INTRSTR_LEN];
   1620 
   1621 	t = ti_type_match(pa);
   1622 	if (t == NULL) {
   1623 		printf("ti_attach: were did the card go ?\n");
   1624 		return;
   1625 	}
   1626 
   1627 	printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class));
   1628 
   1629 	sc = device_private(self);
   1630 	sc->sc_dev = self;
   1631 
   1632 	/*
   1633 	 * Map control/status registers.
   1634 	 */
   1635 	nolinear = 0;
   1636 	if (pci_mapreg_map(pa, 0x10,
   1637 	    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
   1638 	    BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle,
   1639 	    NULL, NULL)) {
   1640 		nolinear = 1;
   1641 		if (pci_mapreg_map(pa, 0x10,
   1642 		    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
   1643 		    0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) {
   1644 			printf(": can't map memory space\n");
   1645 			return;
   1646 		}
   1647 	}
   1648 	if (nolinear == 0)
   1649 		sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle);
   1650 	else
   1651 		sc->ti_vhandle = NULL;
   1652 
   1653 	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
   1654 	command |= PCI_COMMAND_MASTER_ENABLE;
   1655 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
   1656 
   1657 	/* Allocate interrupt */
   1658 	if (pci_intr_map(pa, &ih)) {
   1659 		aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n");
   1660 		return;
   1661 	}
   1662 	intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
   1663 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc);
   1664 	if (sc->sc_ih == NULL) {
   1665 		aprint_error_dev(sc->sc_dev, "couldn't establish interrupt");
   1666 		if (intrstr != NULL)
   1667 			aprint_error(" at %s", intrstr);
   1668 		aprint_error("\n");
   1669 		return;
   1670 	}
   1671 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
   1672 
   1673 	if (ti_chipinit(sc)) {
   1674 		aprint_error_dev(self, "chip initialization failed\n");
   1675 		goto fail2;
   1676 	}
   1677 
   1678 	/*
   1679 	 * Deal with some chip diffrences.
   1680 	 */
   1681 	switch (sc->ti_hwrev) {
   1682 	case TI_HWREV_TIGON:
   1683 		sc->sc_tx_encap = ti_encap_tigon1;
   1684 		sc->sc_tx_eof = ti_txeof_tigon1;
   1685 		if (nolinear == 1)
   1686 			aprint_error_dev(self, "memory space not mapped linear\n");
   1687 		break;
   1688 
   1689 	case TI_HWREV_TIGON_II:
   1690 		sc->sc_tx_encap = ti_encap_tigon2;
   1691 		sc->sc_tx_eof = ti_txeof_tigon2;
   1692 		break;
   1693 
   1694 	default:
   1695 		printf("%s: Unknown chip version: %d\n", device_xname(self),
   1696 		    sc->ti_hwrev);
   1697 		goto fail2;
   1698 	}
   1699 
   1700 	/* Zero out the NIC's on-board SRAM. */
   1701 	ti_mem(sc, 0x2000, 0x100000 - 0x2000,  NULL);
   1702 
   1703 	/* Init again -- zeroing memory may have clobbered some registers. */
   1704 	if (ti_chipinit(sc)) {
   1705 		aprint_error_dev(self, "chip initialization failed\n");
   1706 		goto fail2;
   1707 	}
   1708 
   1709 	/*
   1710 	 * Get station address from the EEPROM. Note: the manual states
   1711 	 * that the MAC address is at offset 0x8c, however the data is
   1712 	 * stored as two longwords (since that's how it's loaded into
   1713 	 * the NIC). This means the MAC address is actually preceded
   1714 	 * by two zero bytes. We need to skip over those.
   1715 	 */
   1716 	if (ti_read_eeprom(sc, (void *)&eaddr,
   1717 				TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
   1718 		aprint_error_dev(self, "failed to read station address\n");
   1719 		goto fail2;
   1720 	}
   1721 
   1722 	/*
   1723 	 * A Tigon chip was detected. Inform the world.
   1724 	 */
   1725 	aprint_error_dev(self, "Ethernet address: %s\n",
   1726 				ether_sprintf(eaddr));
   1727 
   1728 	sc->sc_dmat = pa->pa_dmat;
   1729 
   1730 	/* Allocate the general information block and ring buffers. */
   1731 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
   1732 	    sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg,
   1733 	    BUS_DMA_NOWAIT)) != 0) {
   1734 		aprint_error_dev(sc->sc_dev, "can't allocate ring buffer, error = %d\n",
   1735 		       error);
   1736 		goto fail2;
   1737 	}
   1738 
   1739 	if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg,
   1740 	    sizeof(struct ti_ring_data), (void **)&sc->ti_rdata,
   1741 	    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
   1742 		aprint_error_dev(sc->sc_dev, "can't map ring buffer, error = %d\n",
   1743 		       error);
   1744 		goto fail2;
   1745 	}
   1746 
   1747 	if ((error = bus_dmamap_create(sc->sc_dmat,
   1748 	    sizeof(struct ti_ring_data), 1,
   1749 	    sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT,
   1750 	    &sc->info_dmamap)) != 0) {
   1751 		aprint_error_dev(sc->sc_dev, "can't create ring buffer DMA map, error = %d\n",
   1752 		       error);
   1753 		goto fail2;
   1754 	}
   1755 
   1756 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap,
   1757 	    sc->ti_rdata, sizeof(struct ti_ring_data), NULL,
   1758 	    BUS_DMA_NOWAIT)) != 0) {
   1759 		aprint_error_dev(sc->sc_dev, "can't load ring buffer DMA map, error = %d\n",
   1760 		       error);
   1761 		goto fail2;
   1762 	}
   1763 
   1764 	sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr;
   1765 
   1766 	memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data));
   1767 
   1768 	/* Try to allocate memory for jumbo buffers. */
   1769 	if (ti_alloc_jumbo_mem(sc)) {
   1770 		aprint_error_dev(self, "jumbo buffer allocation failed\n");
   1771 		goto fail2;
   1772 	}
   1773 
   1774 	SIMPLEQ_INIT(&sc->ti_mc_listhead);
   1775 
   1776 	/*
   1777 	 * We really need a better way to tell a 1000baseT card
   1778 	 * from a 1000baseSX one, since in theory there could be
   1779 	 * OEMed 1000baseT cards from lame vendors who aren't
   1780 	 * clever enough to change the PCI ID. For the moment
   1781 	 * though, the AceNIC is the only copper card available.
   1782 	 */
   1783 	if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON &&
   1784 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) ||
   1785 	    (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR &&
   1786 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T))
   1787 		sc->ti_copper = 1;
   1788 	else
   1789 		sc->ti_copper = 0;
   1790 
   1791 	/* Set default tuneable values. */
   1792 	sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
   1793 	sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
   1794 	sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
   1795 	sc->ti_rx_max_coal_bds = 64;
   1796 	sc->ti_tx_max_coal_bds = 128;
   1797 	sc->ti_tx_buf_ratio = 21;
   1798 
   1799 	/* Set up ifnet structure */
   1800 	ifp = &sc->ethercom.ec_if;
   1801 	ifp->if_softc = sc;
   1802 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
   1803 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   1804 	ifp->if_ioctl = ti_ioctl;
   1805 	ifp->if_start = ti_start;
   1806 	ifp->if_watchdog = ti_watchdog;
   1807 	IFQ_SET_READY(&ifp->if_snd);
   1808 
   1809 #if 0
   1810 	/*
   1811 	 * XXX This is not really correct -- we don't necessarily
   1812 	 * XXX want to queue up as many as we can transmit at the
   1813 	 * XXX upper layer like that.  Someone with a board should
   1814 	 * XXX check to see how this affects performance.
   1815 	 */
   1816 	ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
   1817 #endif
   1818 
   1819 	/*
   1820 	 * We can support 802.1Q VLAN-sized frames.
   1821 	 */
   1822 	sc->ethercom.ec_capabilities |=
   1823 	    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
   1824 
   1825 	/*
   1826 	 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware.
   1827 	 */
   1828 	ifp->if_capabilities |=
   1829 	    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
   1830 	    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   1831 	    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
   1832 
   1833 	/* Set up ifmedia support. */
   1834 	ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
   1835 	if (sc->ti_copper) {
   1836                 /*
   1837                  * Copper cards allow manual 10/100 mode selection,
   1838                  * but not manual 1000baseT mode selection. Why?
   1839                  * Because currently there's no way to specify the
   1840                  * master/slave setting through the firmware interface,
   1841                  * so Alteon decided to just bag it and handle it
   1842                  * via autonegotiation.
   1843                  */
   1844                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
   1845                 ifmedia_add(&sc->ifmedia,
   1846                     IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
   1847                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
   1848                 ifmedia_add(&sc->ifmedia,
   1849                     IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
   1850                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
   1851                 ifmedia_add(&sc->ifmedia,
   1852                     IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
   1853 	} else {
   1854 		/* Fiber cards don't support 10/100 modes. */
   1855 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
   1856 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
   1857 	}
   1858 	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
   1859 	ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
   1860 
   1861 	/*
   1862 	 * Call MI attach routines.
   1863 	 */
   1864 	if_attach(ifp);
   1865 	ether_ifattach(ifp, eaddr);
   1866 
   1867 	/*
   1868 	 * Add shutdown hook so that DMA is disabled prior to reboot. Not
   1869 	 * doing do could allow DMA to corrupt kernel memory during the
   1870 	 * reboot before the driver initializes.
   1871 	 */
   1872 	if (pmf_device_register1(self, NULL, NULL, ti_shutdown))
   1873 		pmf_class_network_register(self, ifp);
   1874 	else
   1875 		aprint_error_dev(self, "couldn't establish power handler\n");
   1876 
   1877 	return;
   1878 fail2:
   1879 	pci_intr_disestablish(pc, sc->sc_ih);
   1880 	return;
   1881 }
   1882 
   1883 /*
   1884  * Frame reception handling. This is called if there's a frame
   1885  * on the receive return list.
   1886  *
   1887  * Note: we have to be able to handle three possibilities here:
   1888  * 1) the frame is from the mini receive ring (can only happen)
   1889  *    on Tigon 2 boards)
   1890  * 2) the frame is from the jumbo receive ring
   1891  * 3) the frame is from the standard receive ring
   1892  */
   1893 
   1894 static void
   1895 ti_rxeof(struct ti_softc *sc)
   1896 {
   1897 	struct ifnet		*ifp;
   1898 	struct ti_cmd_desc	cmd;
   1899 
   1900 	ifp = &sc->ethercom.ec_if;
   1901 
   1902 	while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
   1903 		struct ti_rx_desc	*cur_rx;
   1904 		u_int32_t		rxidx;
   1905 		struct mbuf		*m = NULL;
   1906 		struct ether_header	*eh;
   1907 		bus_dmamap_t dmamap;
   1908 
   1909 		cur_rx =
   1910 		    &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
   1911 		rxidx = cur_rx->ti_idx;
   1912 		TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
   1913 
   1914 		if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
   1915 			TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
   1916 			m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
   1917 			sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
   1918 			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
   1919 				ifp->if_ierrors++;
   1920 				ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
   1921 				continue;
   1922 			}
   1923 			if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL)
   1924 			    == ENOBUFS) {
   1925 				ifp->if_ierrors++;
   1926 				ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
   1927 				continue;
   1928 			}
   1929 		} else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
   1930 			TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
   1931 			m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
   1932 			sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
   1933 			dmamap = sc->mini_dmamap[rxidx];
   1934 			sc->mini_dmamap[rxidx] = 0;
   1935 			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
   1936 				ifp->if_ierrors++;
   1937 				ti_newbuf_mini(sc, sc->ti_mini, m, dmamap);
   1938 				continue;
   1939 			}
   1940 			if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap)
   1941 			    == ENOBUFS) {
   1942 				ifp->if_ierrors++;
   1943 				ti_newbuf_mini(sc, sc->ti_mini, m, dmamap);
   1944 				continue;
   1945 			}
   1946 		} else {
   1947 			TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
   1948 			m = sc->ti_cdata.ti_rx_std_chain[rxidx];
   1949 			sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
   1950 			dmamap = sc->std_dmamap[rxidx];
   1951 			sc->std_dmamap[rxidx] = 0;
   1952 			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
   1953 				ifp->if_ierrors++;
   1954 				ti_newbuf_std(sc, sc->ti_std, m, dmamap);
   1955 				continue;
   1956 			}
   1957 			if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap)
   1958 			    == ENOBUFS) {
   1959 				ifp->if_ierrors++;
   1960 				ti_newbuf_std(sc, sc->ti_std, m, dmamap);
   1961 				continue;
   1962 			}
   1963 		}
   1964 
   1965 		m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
   1966 		ifp->if_ipackets++;
   1967 		m->m_pkthdr.rcvif = ifp;
   1968 
   1969 		/*
   1970 	 	 * Handle BPF listeners. Let the BPF user see the packet, but
   1971 	 	 * don't pass it up to the ether_input() layer unless it's
   1972 	 	 * a broadcast packet, multicast packet, matches our ethernet
   1973 	 	 * address or the interface is in promiscuous mode.
   1974 	 	 */
   1975 		bpf_mtap(ifp, m);
   1976 
   1977 		eh = mtod(m, struct ether_header *);
   1978 		switch (ntohs(eh->ether_type)) {
   1979 #ifdef INET
   1980 		case ETHERTYPE_IP:
   1981 		    {
   1982 			struct ip *ip = (struct ip *) (eh + 1);
   1983 
   1984 			/*
   1985 			 * Note the Tigon firmware does not invert
   1986 			 * the checksum for us, hence the XOR.
   1987 			 */
   1988 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
   1989 			if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0)
   1990 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
   1991 			/*
   1992 			 * ntohs() the constant so the compiler can
   1993 			 * optimize...
   1994 			 *
   1995 			 * XXX Figure out a sane way to deal with
   1996 			 * fragmented packets.
   1997 			 */
   1998 			if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) {
   1999 				switch (ip->ip_p) {
   2000 				case IPPROTO_TCP:
   2001 					m->m_pkthdr.csum_data =
   2002 					    cur_rx->ti_tcp_udp_cksum;
   2003 					m->m_pkthdr.csum_flags |=
   2004 					    M_CSUM_TCPv4|M_CSUM_DATA;
   2005 					break;
   2006 				case IPPROTO_UDP:
   2007 					m->m_pkthdr.csum_data =
   2008 					    cur_rx->ti_tcp_udp_cksum;
   2009 					m->m_pkthdr.csum_flags |=
   2010 					    M_CSUM_UDPv4|M_CSUM_DATA;
   2011 					break;
   2012 				default:
   2013 					/* Nothing */;
   2014 				}
   2015 			}
   2016 			break;
   2017 		    }
   2018 #endif
   2019 		default:
   2020 			/* Nothing. */
   2021 			break;
   2022 		}
   2023 
   2024 		if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
   2025 			VLAN_INPUT_TAG(ifp, m,
   2026 			    /* ti_vlan_tag also has the priority, trim it */
   2027 			    cur_rx->ti_vlan_tag & 4095,
   2028 			    continue);
   2029 		}
   2030 
   2031 		(*ifp->if_input)(ifp, m);
   2032 	}
   2033 
   2034 	/* Only necessary on the Tigon 1. */
   2035 	if (sc->ti_hwrev == TI_HWREV_TIGON)
   2036 		CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
   2037 		    sc->ti_rx_saved_considx);
   2038 
   2039 	TI_UPDATE_STDPROD(sc, sc->ti_std);
   2040 	TI_UPDATE_MINIPROD(sc, sc->ti_mini);
   2041 	TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
   2042 }
   2043 
   2044 static void
   2045 ti_txeof_tigon1(struct ti_softc *sc)
   2046 {
   2047 	struct ti_tx_desc	*cur_tx = NULL;
   2048 	struct ifnet		*ifp;
   2049 	struct txdmamap_pool_entry *dma;
   2050 
   2051 	ifp = &sc->ethercom.ec_if;
   2052 
   2053 	/*
   2054 	 * Go through our tx ring and free mbufs for those
   2055 	 * frames that have been sent.
   2056 	 */
   2057 	while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
   2058 		u_int32_t		idx = 0;
   2059 
   2060 		idx = sc->ti_tx_saved_considx;
   2061 		if (idx > 383)
   2062 			CSR_WRITE_4(sc, TI_WINBASE,
   2063 			    TI_TX_RING_BASE + 6144);
   2064 		else if (idx > 255)
   2065 			CSR_WRITE_4(sc, TI_WINBASE,
   2066 			    TI_TX_RING_BASE + 4096);
   2067 		else if (idx > 127)
   2068 			CSR_WRITE_4(sc, TI_WINBASE,
   2069 			    TI_TX_RING_BASE + 2048);
   2070 		else
   2071 			CSR_WRITE_4(sc, TI_WINBASE,
   2072 			    TI_TX_RING_BASE);
   2073 		cur_tx = &sc->ti_tx_ring_nic[idx % 128];
   2074 		if (cur_tx->ti_flags & TI_BDFLAG_END)
   2075 			ifp->if_opackets++;
   2076 		if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
   2077 			m_freem(sc->ti_cdata.ti_tx_chain[idx]);
   2078 			sc->ti_cdata.ti_tx_chain[idx] = NULL;
   2079 
   2080 			dma = sc->txdma[idx];
   2081 			KDASSERT(dma != NULL);
   2082 			bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0,
   2083 			    dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   2084 			bus_dmamap_unload(sc->sc_dmat, dma->dmamap);
   2085 
   2086 			SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link);
   2087 			sc->txdma[idx] = NULL;
   2088 		}
   2089 		sc->ti_txcnt--;
   2090 		TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
   2091 		ifp->if_timer = 0;
   2092 	}
   2093 
   2094 	if (cur_tx != NULL)
   2095 		ifp->if_flags &= ~IFF_OACTIVE;
   2096 }
   2097 
   2098 static void
   2099 ti_txeof_tigon2(struct ti_softc *sc)
   2100 {
   2101 	struct ti_tx_desc	*cur_tx = NULL;
   2102 	struct ifnet		*ifp;
   2103 	struct txdmamap_pool_entry *dma;
   2104 	int firstidx, cnt;
   2105 
   2106 	ifp = &sc->ethercom.ec_if;
   2107 
   2108 	/*
   2109 	 * Go through our tx ring and free mbufs for those
   2110 	 * frames that have been sent.
   2111 	 */
   2112 	firstidx = sc->ti_tx_saved_considx;
   2113 	cnt = 0;
   2114 	while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
   2115 		u_int32_t		idx = 0;
   2116 
   2117 		idx = sc->ti_tx_saved_considx;
   2118 		cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
   2119 		if (cur_tx->ti_flags & TI_BDFLAG_END)
   2120 			ifp->if_opackets++;
   2121 		if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
   2122 			m_freem(sc->ti_cdata.ti_tx_chain[idx]);
   2123 			sc->ti_cdata.ti_tx_chain[idx] = NULL;
   2124 
   2125 			dma = sc->txdma[idx];
   2126 			KDASSERT(dma != NULL);
   2127 			bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0,
   2128 			    dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   2129 			bus_dmamap_unload(sc->sc_dmat, dma->dmamap);
   2130 
   2131 			SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link);
   2132 			sc->txdma[idx] = NULL;
   2133 		}
   2134 		cnt++;
   2135 		sc->ti_txcnt--;
   2136 		TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
   2137 		ifp->if_timer = 0;
   2138 	}
   2139 
   2140 	if (cnt != 0)
   2141 		TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE);
   2142 
   2143 	if (cur_tx != NULL)
   2144 		ifp->if_flags &= ~IFF_OACTIVE;
   2145 }
   2146 
   2147 static int
   2148 ti_intr(void *xsc)
   2149 {
   2150 	struct ti_softc		*sc;
   2151 	struct ifnet		*ifp;
   2152 
   2153 	sc = xsc;
   2154 	ifp = &sc->ethercom.ec_if;
   2155 
   2156 #ifdef notdef
   2157 	/* Avoid this for now -- checking this register is expensive. */
   2158 	/* Make sure this is really our interrupt. */
   2159 	if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
   2160 		return (0);
   2161 #endif
   2162 
   2163 	/* Ack interrupt and stop others from occuring. */
   2164 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
   2165 
   2166 	if (ifp->if_flags & IFF_RUNNING) {
   2167 		/* Check RX return ring producer/consumer */
   2168 		ti_rxeof(sc);
   2169 
   2170 		/* Check TX ring producer/consumer */
   2171 		(*sc->sc_tx_eof)(sc);
   2172 	}
   2173 
   2174 	ti_handle_events(sc);
   2175 
   2176 	/* Re-enable interrupts. */
   2177 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
   2178 
   2179 	if ((ifp->if_flags & IFF_RUNNING) != 0 &&
   2180 	    IFQ_IS_EMPTY(&ifp->if_snd) == 0)
   2181 		ti_start(ifp);
   2182 
   2183 	return (1);
   2184 }
   2185 
   2186 static void
   2187 ti_stats_update(struct ti_softc *sc)
   2188 {
   2189 	struct ifnet		*ifp;
   2190 
   2191 	ifp = &sc->ethercom.ec_if;
   2192 
   2193 	TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD);
   2194 
   2195 	ifp->if_collisions +=
   2196 	   (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
   2197 	   sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
   2198 	   sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
   2199 	   sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
   2200 	   ifp->if_collisions;
   2201 
   2202 	TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD);
   2203 }
   2204 
   2205 /*
   2206  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
   2207  * pointers to descriptors.
   2208  */
   2209 static int
   2210 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
   2211 {
   2212 	struct ti_tx_desc	*f = NULL;
   2213 	u_int32_t		frag, cur, cnt = 0;
   2214 	struct txdmamap_pool_entry *dma;
   2215 	bus_dmamap_t dmamap;
   2216 	int error, i;
   2217 	struct m_tag *mtag;
   2218 	u_int16_t csum_flags = 0;
   2219 
   2220 	dma = SIMPLEQ_FIRST(&sc->txdma_list);
   2221 	if (dma == NULL) {
   2222 		return ENOMEM;
   2223 	}
   2224 	dmamap = dma->dmamap;
   2225 
   2226 	error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head,
   2227 	    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
   2228 	if (error) {
   2229 		struct mbuf *m;
   2230 		int j = 0;
   2231 		for (m = m_head; m; m = m->m_next)
   2232 			j++;
   2233 		printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) "
   2234 		       "error %d\n", m_head->m_pkthdr.len, j, error);
   2235 		return (ENOMEM);
   2236 	}
   2237 
   2238 	cur = frag = *txidx;
   2239 
   2240 	if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) {
   2241 		/* IP header checksum field must be 0! */
   2242 		csum_flags |= TI_BDFLAG_IP_CKSUM;
   2243 	}
   2244 	if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4))
   2245 		csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
   2246 
   2247 	/* XXX fragmented packet checksum capability? */
   2248 
   2249 	/*
   2250  	 * Start packing the mbufs in this chain into
   2251 	 * the fragment pointers. Stop when we run out
   2252  	 * of fragments or hit the end of the mbuf chain.
   2253 	 */
   2254 	for (i = 0; i < dmamap->dm_nsegs; i++) {
   2255 		if (frag > 383)
   2256 			CSR_WRITE_4(sc, TI_WINBASE,
   2257 			    TI_TX_RING_BASE + 6144);
   2258 		else if (frag > 255)
   2259 			CSR_WRITE_4(sc, TI_WINBASE,
   2260 			    TI_TX_RING_BASE + 4096);
   2261 		else if (frag > 127)
   2262 			CSR_WRITE_4(sc, TI_WINBASE,
   2263 			    TI_TX_RING_BASE + 2048);
   2264 		else
   2265 			CSR_WRITE_4(sc, TI_WINBASE,
   2266 			    TI_TX_RING_BASE);
   2267 		f = &sc->ti_tx_ring_nic[frag % 128];
   2268 		if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
   2269 			break;
   2270 		TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr;
   2271 		f->ti_len = dmamap->dm_segs[i].ds_len;
   2272 		f->ti_flags = csum_flags;
   2273 		if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) {
   2274 			f->ti_flags |= TI_BDFLAG_VLAN_TAG;
   2275 			f->ti_vlan_tag = VLAN_TAG_VALUE(mtag);
   2276 		} else {
   2277 			f->ti_vlan_tag = 0;
   2278 		}
   2279 		/*
   2280 		 * Sanity check: avoid coming within 16 descriptors
   2281 		 * of the end of the ring.
   2282 		 */
   2283 		if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
   2284 			return (ENOBUFS);
   2285 		cur = frag;
   2286 		TI_INC(frag, TI_TX_RING_CNT);
   2287 		cnt++;
   2288 	}
   2289 
   2290 	if (i < dmamap->dm_nsegs)
   2291 		return (ENOBUFS);
   2292 
   2293 	if (frag == sc->ti_tx_saved_considx)
   2294 		return (ENOBUFS);
   2295 
   2296 	sc->ti_tx_ring_nic[cur % 128].ti_flags |=
   2297 	    TI_BDFLAG_END;
   2298 
   2299 	/* Sync the packet's DMA map. */
   2300 	bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   2301 	    BUS_DMASYNC_PREWRITE);
   2302 
   2303 	sc->ti_cdata.ti_tx_chain[cur] = m_head;
   2304 	SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link);
   2305 	sc->txdma[cur] = dma;
   2306 	sc->ti_txcnt += cnt;
   2307 
   2308 	*txidx = frag;
   2309 
   2310 	return (0);
   2311 }
   2312 
   2313 static int
   2314 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
   2315 {
   2316 	struct ti_tx_desc	*f = NULL;
   2317 	u_int32_t		frag, firstfrag, cur, cnt = 0;
   2318 	struct txdmamap_pool_entry *dma;
   2319 	bus_dmamap_t dmamap;
   2320 	int error, i;
   2321 	struct m_tag *mtag;
   2322 	u_int16_t csum_flags = 0;
   2323 
   2324 	dma = SIMPLEQ_FIRST(&sc->txdma_list);
   2325 	if (dma == NULL) {
   2326 		return ENOMEM;
   2327 	}
   2328 	dmamap = dma->dmamap;
   2329 
   2330 	error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head,
   2331 	    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
   2332 	if (error) {
   2333 		struct mbuf *m;
   2334 		int j = 0;
   2335 		for (m = m_head; m; m = m->m_next)
   2336 			j++;
   2337 		printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) "
   2338 		       "error %d\n", m_head->m_pkthdr.len, j, error);
   2339 		return (ENOMEM);
   2340 	}
   2341 
   2342 	cur = firstfrag = frag = *txidx;
   2343 
   2344 	if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) {
   2345 		/* IP header checksum field must be 0! */
   2346 		csum_flags |= TI_BDFLAG_IP_CKSUM;
   2347 	}
   2348 	if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4))
   2349 		csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
   2350 
   2351 	/* XXX fragmented packet checksum capability? */
   2352 
   2353 	/*
   2354  	 * Start packing the mbufs in this chain into
   2355 	 * the fragment pointers. Stop when we run out
   2356  	 * of fragments or hit the end of the mbuf chain.
   2357 	 */
   2358 	for (i = 0; i < dmamap->dm_nsegs; i++) {
   2359 		f = &sc->ti_rdata->ti_tx_ring[frag];
   2360 		if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
   2361 			break;
   2362 		TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr;
   2363 		f->ti_len = dmamap->dm_segs[i].ds_len;
   2364 		f->ti_flags = csum_flags;
   2365 		if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) {
   2366 			f->ti_flags |= TI_BDFLAG_VLAN_TAG;
   2367 			f->ti_vlan_tag = VLAN_TAG_VALUE(mtag);
   2368 		} else {
   2369 			f->ti_vlan_tag = 0;
   2370 		}
   2371 		/*
   2372 		 * Sanity check: avoid coming within 16 descriptors
   2373 		 * of the end of the ring.
   2374 		 */
   2375 		if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
   2376 			return (ENOBUFS);
   2377 		cur = frag;
   2378 		TI_INC(frag, TI_TX_RING_CNT);
   2379 		cnt++;
   2380 	}
   2381 
   2382 	if (i < dmamap->dm_nsegs)
   2383 		return (ENOBUFS);
   2384 
   2385 	if (frag == sc->ti_tx_saved_considx)
   2386 		return (ENOBUFS);
   2387 
   2388 	sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
   2389 
   2390 	/* Sync the packet's DMA map. */
   2391 	bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   2392 	    BUS_DMASYNC_PREWRITE);
   2393 
   2394 	/* Sync the descriptors we are using. */
   2395 	TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE);
   2396 
   2397 	sc->ti_cdata.ti_tx_chain[cur] = m_head;
   2398 	SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link);
   2399 	sc->txdma[cur] = dma;
   2400 	sc->ti_txcnt += cnt;
   2401 
   2402 	*txidx = frag;
   2403 
   2404 	return (0);
   2405 }
   2406 
   2407 /*
   2408  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
   2409  * to the mbuf data regions directly in the transmit descriptors.
   2410  */
   2411 static void
   2412 ti_start(struct ifnet *ifp)
   2413 {
   2414 	struct ti_softc		*sc;
   2415 	struct mbuf		*m_head = NULL;
   2416 	u_int32_t		prodidx = 0;
   2417 
   2418 	sc = ifp->if_softc;
   2419 
   2420 	prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
   2421 
   2422 	while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
   2423 		IFQ_POLL(&ifp->if_snd, m_head);
   2424 		if (m_head == NULL)
   2425 			break;
   2426 
   2427 		/*
   2428 		 * Pack the data into the transmit ring. If we
   2429 		 * don't have room, set the OACTIVE flag and wait
   2430 		 * for the NIC to drain the ring.
   2431 		 */
   2432 		if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) {
   2433 			ifp->if_flags |= IFF_OACTIVE;
   2434 			break;
   2435 		}
   2436 
   2437 		IFQ_DEQUEUE(&ifp->if_snd, m_head);
   2438 
   2439 		/*
   2440 		 * If there's a BPF listener, bounce a copy of this frame
   2441 		 * to him.
   2442 		 */
   2443 		bpf_mtap(ifp, m_head);
   2444 	}
   2445 
   2446 	/* Transmit */
   2447 	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
   2448 
   2449 	/*
   2450 	 * Set a timeout in case the chip goes out to lunch.
   2451 	 */
   2452 	ifp->if_timer = 5;
   2453 }
   2454 
   2455 static void
   2456 ti_init(void *xsc)
   2457 {
   2458 	struct ti_softc		*sc = xsc;
   2459         int			s;
   2460 
   2461 	s = splnet();
   2462 
   2463 	/* Cancel pending I/O and flush buffers. */
   2464 	ti_stop(sc);
   2465 
   2466 	/* Init the gen info block, ring control blocks and firmware. */
   2467 	if (ti_gibinit(sc)) {
   2468 		aprint_error_dev(sc->sc_dev, "initialization failure\n");
   2469 		splx(s);
   2470 		return;
   2471 	}
   2472 
   2473 	splx(s);
   2474 }
   2475 
   2476 static void
   2477 ti_init2(struct ti_softc *sc)
   2478 {
   2479 	struct ti_cmd_desc	cmd;
   2480 	struct ifnet		*ifp;
   2481 	const u_int8_t		*m;
   2482 	struct ifmedia		*ifm;
   2483 	int			tmp;
   2484 
   2485 	ifp = &sc->ethercom.ec_if;
   2486 
   2487 	/* Specify MTU and interface index. */
   2488 	CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(sc->sc_dev)); /* ??? */
   2489 
   2490 	tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
   2491 	if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
   2492 		tmp += ETHER_VLAN_ENCAP_LEN;
   2493 	CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp);
   2494 
   2495 	TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
   2496 
   2497 	/* Load our MAC address. */
   2498 	m = (const u_int8_t *)CLLADDR(ifp->if_sadl);
   2499 	CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]);
   2500 	CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16)
   2501 		    | (m[4] << 8) | m[5]);
   2502 	TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
   2503 
   2504 	/* Enable or disable promiscuous mode as needed. */
   2505 	if (ifp->if_flags & IFF_PROMISC) {
   2506 		TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
   2507 	} else {
   2508 		TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
   2509 	}
   2510 
   2511 	/* Program multicast filter. */
   2512 	ti_setmulti(sc);
   2513 
   2514 	/*
   2515 	 * If this is a Tigon 1, we should tell the
   2516 	 * firmware to use software packet filtering.
   2517 	 */
   2518 	if (sc->ti_hwrev == TI_HWREV_TIGON) {
   2519 		TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
   2520 	}
   2521 
   2522 	/* Init RX ring. */
   2523 	ti_init_rx_ring_std(sc);
   2524 
   2525 	/* Init jumbo RX ring. */
   2526 	if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN))
   2527 		ti_init_rx_ring_jumbo(sc);
   2528 
   2529 	/*
   2530 	 * If this is a Tigon 2, we can also configure the
   2531 	 * mini ring.
   2532 	 */
   2533 	if (sc->ti_hwrev == TI_HWREV_TIGON_II)
   2534 		ti_init_rx_ring_mini(sc);
   2535 
   2536 	CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
   2537 	sc->ti_rx_saved_considx = 0;
   2538 
   2539 	/* Init TX ring. */
   2540 	ti_init_tx_ring(sc);
   2541 
   2542 	/* Tell firmware we're alive. */
   2543 	TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
   2544 
   2545 	/* Enable host interrupts. */
   2546 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
   2547 
   2548 	ifp->if_flags |= IFF_RUNNING;
   2549 	ifp->if_flags &= ~IFF_OACTIVE;
   2550 
   2551 	/*
   2552 	 * Make sure to set media properly. We have to do this
   2553 	 * here since we have to issue commands in order to set
   2554 	 * the link negotiation and we can't issue commands until
   2555 	 * the firmware is running.
   2556 	 */
   2557 	ifm = &sc->ifmedia;
   2558 	tmp = ifm->ifm_media;
   2559 	ifm->ifm_media = ifm->ifm_cur->ifm_media;
   2560 	ti_ifmedia_upd(ifp);
   2561 	ifm->ifm_media = tmp;
   2562 }
   2563 
   2564 /*
   2565  * Set media options.
   2566  */
   2567 static int
   2568 ti_ifmedia_upd(struct ifnet *ifp)
   2569 {
   2570 	struct ti_softc		*sc;
   2571 	struct ifmedia		*ifm;
   2572 	struct ti_cmd_desc	cmd;
   2573 
   2574 	sc = ifp->if_softc;
   2575 	ifm = &sc->ifmedia;
   2576 
   2577 	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
   2578 		return (EINVAL);
   2579 
   2580 	switch (IFM_SUBTYPE(ifm->ifm_media)) {
   2581 	case IFM_AUTO:
   2582 		CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
   2583 		    TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
   2584 		    TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
   2585 		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
   2586 		    TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
   2587 		    TI_LNK_AUTONEGENB|TI_LNK_ENB);
   2588 		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
   2589 		    TI_CMD_CODE_NEGOTIATE_BOTH, 0);
   2590 		break;
   2591 	case IFM_1000_SX:
   2592 	case IFM_1000_T:
   2593 		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
   2594 			CSR_WRITE_4(sc, TI_GCR_GLINK,
   2595 			    TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX|
   2596 			    TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
   2597 		} else {
   2598 			CSR_WRITE_4(sc, TI_GCR_GLINK,
   2599 			    TI_GLNK_PREF|TI_GLNK_1000MB|
   2600 			    TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
   2601 		}
   2602 		CSR_WRITE_4(sc, TI_GCR_LINK, 0);
   2603 		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
   2604 		    TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
   2605 		break;
   2606 	case IFM_100_FX:
   2607 	case IFM_10_FL:
   2608 	case IFM_100_TX:
   2609 	case IFM_10_T:
   2610 		CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
   2611 		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
   2612 		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
   2613 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
   2614 			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
   2615 		} else {
   2616 			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
   2617 		}
   2618 		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
   2619 			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
   2620 		} else {
   2621 			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
   2622 		}
   2623 		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
   2624 		    TI_CMD_CODE_NEGOTIATE_10_100, 0);
   2625 		break;
   2626 	}
   2627 
   2628 	sc->ethercom.ec_if.if_baudrate =
   2629 	    ifmedia_baudrate(ifm->ifm_media);
   2630 
   2631 	return (0);
   2632 }
   2633 
   2634 /*
   2635  * Report current media status.
   2636  */
   2637 static void
   2638 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
   2639 {
   2640 	struct ti_softc		*sc;
   2641 	u_int32_t               media = 0;
   2642 
   2643 	sc = ifp->if_softc;
   2644 
   2645 	ifmr->ifm_status = IFM_AVALID;
   2646 	ifmr->ifm_active = IFM_ETHER;
   2647 
   2648 	if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
   2649 		return;
   2650 
   2651 	ifmr->ifm_status |= IFM_ACTIVE;
   2652 
   2653 	if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
   2654 		media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
   2655 		if (sc->ti_copper)
   2656 			ifmr->ifm_active |= IFM_1000_T;
   2657 		else
   2658 			ifmr->ifm_active |= IFM_1000_SX;
   2659 		if (media & TI_GLNK_FULL_DUPLEX)
   2660 			ifmr->ifm_active |= IFM_FDX;
   2661 		else
   2662 			ifmr->ifm_active |= IFM_HDX;
   2663 	} else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
   2664 		media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
   2665 		if (sc->ti_copper) {
   2666 			if (media & TI_LNK_100MB)
   2667 				ifmr->ifm_active |= IFM_100_TX;
   2668 			if (media & TI_LNK_10MB)
   2669 				ifmr->ifm_active |= IFM_10_T;
   2670 		} else {
   2671 			if (media & TI_LNK_100MB)
   2672 				ifmr->ifm_active |= IFM_100_FX;
   2673 			if (media & TI_LNK_10MB)
   2674 				ifmr->ifm_active |= IFM_10_FL;
   2675 		}
   2676 		if (media & TI_LNK_FULL_DUPLEX)
   2677 			ifmr->ifm_active |= IFM_FDX;
   2678 		if (media & TI_LNK_HALF_DUPLEX)
   2679 			ifmr->ifm_active |= IFM_HDX;
   2680 	}
   2681 
   2682 	sc->ethercom.ec_if.if_baudrate =
   2683 	    ifmedia_baudrate(sc->ifmedia.ifm_media);
   2684 }
   2685 
   2686 static int
   2687 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data)
   2688 {
   2689 	struct ifaddr *ifa = (struct ifaddr *) data;
   2690 	struct ti_softc *sc = ifp->if_softc;
   2691 
   2692 	if ((ifp->if_flags & IFF_UP) == 0) {
   2693 		ifp->if_flags |= IFF_UP;
   2694 		ti_init(sc);
   2695 	}
   2696 
   2697 	switch (cmd) {
   2698 	case SIOCINITIFADDR:
   2699 
   2700 		switch (ifa->ifa_addr->sa_family) {
   2701 #ifdef INET
   2702 		case AF_INET:
   2703 			arp_ifinit(ifp, ifa);
   2704 			break;
   2705 #endif
   2706 		default:
   2707 			break;
   2708 		}
   2709 		break;
   2710 
   2711 	default:
   2712 		return (EINVAL);
   2713 	}
   2714 
   2715 	return (0);
   2716 }
   2717 
   2718 static int
   2719 ti_ioctl(struct ifnet *ifp, u_long command, void *data)
   2720 {
   2721 	struct ti_softc		*sc = ifp->if_softc;
   2722 	struct ifreq		*ifr = (struct ifreq *) data;
   2723 	int			s, error = 0;
   2724 	struct ti_cmd_desc	cmd;
   2725 
   2726 	s = splnet();
   2727 
   2728 	switch (command) {
   2729 	case SIOCINITIFADDR:
   2730 		error = ti_ether_ioctl(ifp, command, data);
   2731 		break;
   2732 	case SIOCSIFMTU:
   2733 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO)
   2734 			error = EINVAL;
   2735 		else if ((error = ifioctl_common(ifp, command, data)) == ENETRESET){
   2736 			ti_init(sc);
   2737 			error = 0;
   2738 		}
   2739 		break;
   2740 	case SIOCSIFFLAGS:
   2741 		if ((error = ifioctl_common(ifp, command, data)) != 0)
   2742 			break;
   2743 		if (ifp->if_flags & IFF_UP) {
   2744 			/*
   2745 			 * If only the state of the PROMISC flag changed,
   2746 			 * then just use the 'set promisc mode' command
   2747 			 * instead of reinitializing the entire NIC. Doing
   2748 			 * a full re-init means reloading the firmware and
   2749 			 * waiting for it to start up, which may take a
   2750 			 * second or two.
   2751 			 */
   2752 			if (ifp->if_flags & IFF_RUNNING &&
   2753 			    ifp->if_flags & IFF_PROMISC &&
   2754 			    !(sc->ti_if_flags & IFF_PROMISC)) {
   2755 				TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
   2756 				    TI_CMD_CODE_PROMISC_ENB, 0);
   2757 			} else if (ifp->if_flags & IFF_RUNNING &&
   2758 			    !(ifp->if_flags & IFF_PROMISC) &&
   2759 			    sc->ti_if_flags & IFF_PROMISC) {
   2760 				TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
   2761 				    TI_CMD_CODE_PROMISC_DIS, 0);
   2762 			} else
   2763 				ti_init(sc);
   2764 		} else {
   2765 			if (ifp->if_flags & IFF_RUNNING) {
   2766 				ti_stop(sc);
   2767 			}
   2768 		}
   2769 		sc->ti_if_flags = ifp->if_flags;
   2770 		error = 0;
   2771 		break;
   2772 	case SIOCSIFMEDIA:
   2773 	case SIOCGIFMEDIA:
   2774 		error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
   2775 		break;
   2776 	default:
   2777 		if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
   2778 			break;
   2779 
   2780 		error = 0;
   2781 
   2782 		if (command == SIOCSIFCAP)
   2783 			ti_init(sc);
   2784 		else if (command != SIOCADDMULTI && command != SIOCDELMULTI)
   2785 			;
   2786 		else if (ifp->if_flags & IFF_RUNNING)
   2787 			ti_setmulti(sc);
   2788 		break;
   2789 	}
   2790 
   2791 	(void)splx(s);
   2792 
   2793 	return (error);
   2794 }
   2795 
   2796 static void
   2797 ti_watchdog(struct ifnet *ifp)
   2798 {
   2799 	struct ti_softc		*sc;
   2800 
   2801 	sc = ifp->if_softc;
   2802 
   2803 	aprint_error_dev(sc->sc_dev, "watchdog timeout -- resetting\n");
   2804 	ti_stop(sc);
   2805 	ti_init(sc);
   2806 
   2807 	ifp->if_oerrors++;
   2808 }
   2809 
   2810 /*
   2811  * Stop the adapter and free any mbufs allocated to the
   2812  * RX and TX lists.
   2813  */
   2814 static void
   2815 ti_stop(struct ti_softc *sc)
   2816 {
   2817 	struct ifnet		*ifp;
   2818 	struct ti_cmd_desc	cmd;
   2819 
   2820 	ifp = &sc->ethercom.ec_if;
   2821 
   2822 	/* Disable host interrupts. */
   2823 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
   2824 	/*
   2825 	 * Tell firmware we're shutting down.
   2826 	 */
   2827 	TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
   2828 
   2829 	/* Halt and reinitialize. */
   2830 	ti_chipinit(sc);
   2831 	ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
   2832 	ti_chipinit(sc);
   2833 
   2834 	/* Free the RX lists. */
   2835 	ti_free_rx_ring_std(sc);
   2836 
   2837 	/* Free jumbo RX list. */
   2838 	ti_free_rx_ring_jumbo(sc);
   2839 
   2840 	/* Free mini RX list. */
   2841 	ti_free_rx_ring_mini(sc);
   2842 
   2843 	/* Free TX buffers. */
   2844 	ti_free_tx_ring(sc);
   2845 
   2846 	sc->ti_ev_prodidx.ti_idx = 0;
   2847 	sc->ti_return_prodidx.ti_idx = 0;
   2848 	sc->ti_tx_considx.ti_idx = 0;
   2849 	sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
   2850 
   2851 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   2852 }
   2853 
   2854 /*
   2855  * Stop all chip I/O so that the kernel's probe routines don't
   2856  * get confused by errant DMAs when rebooting.
   2857  */
   2858 static bool
   2859 ti_shutdown(device_t self, int howto)
   2860 {
   2861 	struct ti_softc *sc;
   2862 
   2863 	sc = device_private(self);
   2864 	ti_chipinit(sc);
   2865 
   2866 	return true;
   2867 }
   2868