siisata_pci.c revision 1.8
1/* $NetBSD: siisata_pci.c,v 1.8 2010/02/24 22:38:01 dyoung Exp $ */ 2 3/* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28/* 29 * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch. 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53#include <sys/cdefs.h> 54__KERNEL_RCSID(0, "$NetBSD: siisata_pci.c,v 1.8 2010/02/24 22:38:01 dyoung Exp $"); 55 56#include <sys/types.h> 57#include <sys/malloc.h> 58#include <sys/param.h> 59#include <sys/kernel.h> 60#include <sys/systm.h> 61 62#include <uvm/uvm_extern.h> 63 64#include <dev/pci/pcivar.h> 65#include <dev/pci/pcidevs.h> 66#include <dev/ic/siisatavar.h> 67 68struct siisata_pci_softc { 69 struct siisata_softc si_sc; 70 pci_chipset_tag_t sc_pc; 71 pcitag_t sc_pcitag; 72 void * sc_ih; 73}; 74 75static int siisata_pci_match(device_t, cfdata_t, void *); 76static void siisata_pci_attach(device_t, device_t, void *); 77static int siisata_pci_detach(device_t, int); 78static bool siisata_pci_resume(device_t, const pmf_qual_t *); 79 80struct siisata_pci_board { 81 pci_vendor_id_t spb_vend; 82 pci_product_id_t spb_prod; 83 uint16_t spb_port; 84 uint16_t spb_chip; 85}; 86 87static const struct siisata_pci_board siisata_pci_boards[] = { 88 { 89 .spb_vend = PCI_VENDOR_CMDTECH, 90 .spb_prod = PCI_PRODUCT_CMDTECH_3124, 91 .spb_port = 4, 92 .spb_chip = 3124, 93 }, 94 { 95 .spb_vend = PCI_VENDOR_CMDTECH, 96 .spb_prod = PCI_PRODUCT_CMDTECH_3132, 97 .spb_port = 2, 98 .spb_chip = 3132, 99 }, 100 { 101 .spb_vend = PCI_VENDOR_CMDTECH, 102 .spb_prod = PCI_PRODUCT_CMDTECH_3531, 103 .spb_port = 1, 104 .spb_chip = 3531, 105 }, 106}; 107 108CFATTACH_DECL_NEW(siisata_pci, sizeof(struct siisata_pci_softc), 109 siisata_pci_match, siisata_pci_attach, siisata_pci_detach, NULL); 110 111static const struct siisata_pci_board * 112siisata_pci_lookup(const struct pci_attach_args * pa) 113{ 114 int i; 115 116 for (i = 0; i < __arraycount(siisata_pci_boards); i++) { 117 if (siisata_pci_boards[i].spb_vend != PCI_VENDOR(pa->pa_id)) 118 continue; 119 if (siisata_pci_boards[i].spb_prod == PCI_PRODUCT(pa->pa_id)) 120 return &siisata_pci_boards[i]; 121 } 122 123 return NULL; 124} 125 126static int 127siisata_pci_match(device_t parent, cfdata_t match, void *aux) 128{ 129 struct pci_attach_args *pa = aux; 130 131 if (siisata_pci_lookup(pa) != NULL) 132 return 3; 133 134 return 0; 135} 136 137static void 138siisata_pci_attach(device_t parent, device_t self, void *aux) 139{ 140 struct pci_attach_args *pa = aux; 141 struct siisata_pci_softc *psc = device_private(self); 142 struct siisata_softc *sc = &psc->si_sc; 143 char devinfo[256]; 144 const char *intrstr; 145 pcireg_t csr, memtype; 146 const struct siisata_pci_board *spbp; 147 pci_intr_handle_t intrhandle; 148 bus_space_tag_t memt; 149 bus_space_handle_t memh; 150 uint32_t gcreg; 151 int memh_valid; 152 bus_size_t grsize, prsize; 153 154 sc->sc_atac.atac_dev = self; 155 156 psc->sc_pc = pa->pa_pc; 157 psc->sc_pcitag = pa->pa_tag; 158 159 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 160 aprint_naive(": SATA-II HBA\n"); 161 aprint_normal(": %s\n", devinfo); 162 163 /* map BAR 0, global registers */ 164 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR0); 165 switch (memtype) { 166 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 167 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 168 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR0, 169 memtype, 0, &memt, &memh, NULL, &grsize) == 0); 170 break; 171 default: 172 memh_valid = 0; 173 } 174 if (memh_valid) { 175 sc->sc_grt = memt; 176 sc->sc_grh = memh; 177 sc->sc_grs = grsize; 178 } else { 179 aprint_error_dev(self, "couldn't map global registers\n"); 180 return; 181 } 182 183 /* map BAR 1, port registers */ 184 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR1); 185 switch (memtype) { 186 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 187 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 188 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR1, 189 memtype, 0, &memt, &memh, NULL, &prsize) == 0); 190 break; 191 default: 192 memh_valid = 0; 193 } 194 if (memh_valid) { 195 sc->sc_prt = memt; 196 sc->sc_prh = memh; 197 sc->sc_prs = prsize; 198 } else { 199 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 200 aprint_error_dev(self, "couldn't map port registers\n"); 201 return; 202 } 203 204 if (pci_dma64_available(pa)) 205 sc->sc_dmat = pa->pa_dmat64; 206 else 207 sc->sc_dmat = pa->pa_dmat; 208 209 /* map interrupt */ 210 if (pci_intr_map(pa, &intrhandle) != 0) { 211 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 212 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 213 aprint_error_dev(self, "couldn't map interrupt\n"); 214 return; 215 } 216 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 217 psc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, 218 IPL_BIO, siisata_intr, sc); 219 if (psc->sc_ih == NULL) { 220 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 221 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 222 aprint_error_dev(self, "couldn't establish interrupt at %s\n", 223 intrstr); 224 return; 225 } 226 aprint_normal_dev(self, "interrupting at %s\n", 227 intrstr ? intrstr : "unknown interrupt"); 228 229 /* fill in number of ports on this device */ 230 spbp = siisata_pci_lookup(pa); 231 KASSERT(spbp != NULL); 232 sc->sc_atac.atac_nchannels = spbp->spb_port; 233 234 /* set the necessary bits in case the firmware didn't */ 235 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 236 csr |= PCI_COMMAND_MASTER_ENABLE; 237 csr |= PCI_COMMAND_MEM_ENABLE; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 239 240 gcreg = GRREAD(sc, GR_GC); 241 242 aprint_verbose_dev(self, "SiI%d, %sGb/s\n", 243 spbp->spb_chip, (gcreg & GR_GC_3GBPS) ? "3.0" : "1.5" ); 244 if (spbp->spb_chip == 3124) { 245 short width; 246 short speed; 247 char pcix = 1; 248 249 width = (gcreg & GR_GC_REQ64) ? 64 : 32; 250 251 switch (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) { 252 case 0: 253 speed = (gcreg & GR_GC_M66EN) ? 66 : 33; 254 pcix = 0; 255 break; 256 case GR_GC_TRDY: 257 speed = 66; 258 break; 259 case GR_GC_STOP: 260 speed = 100; 261 break; 262 case GR_GC_STOP | GR_GC_TRDY: 263 speed = 133; 264 break; 265 default: 266 speed = -1; 267 break; 268 } 269 aprint_verbose_dev(self, "%hd-bit %hdMHz PCI%s\n", 270 width, speed, pcix ? "-X" : ""); 271 } 272 273 siisata_attach(sc); 274 275 if (!pmf_device_register(self, NULL, siisata_pci_resume)) 276 aprint_error_dev(self, "couldn't establish power handler\n"); 277} 278 279static int 280siisata_pci_detach(device_t dv, int flags) 281{ 282 struct siisata_pci_softc *psc = device_private(dv); 283 struct siisata_softc *sc = &psc->si_sc; 284 int rv; 285 286 rv = siisata_detach(sc, flags); 287 if (rv) 288 return rv; 289 290 if (psc->sc_ih != NULL) { 291 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 292 } 293 294 bus_space_unmap(sc->sc_prt, sc->sc_prh, sc->sc_prs); 295 bus_space_unmap(sc->sc_grt, sc->sc_grh, sc->sc_grs); 296 297 return 0; 298} 299 300static bool 301siisata_pci_resume(device_t dv, const pmf_qual_t *qual) 302{ 303 struct siisata_pci_softc *psc = device_private(dv); 304 struct siisata_softc *sc = &psc->si_sc; 305 int s; 306 307 s = splbio(); 308 siisata_resume(sc); 309 splx(s); 310 311 return true; 312} 313