amdgpu_atombios.h revision 1.1 
1/*	$NetBSD: amdgpu_atombios.h,v 1.1 2018/08/27 01:34:43 riastradh Exp $	*/
2
3/*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef __AMDGPU_ATOMBIOS_H__
27#define __AMDGPU_ATOMBIOS_H__
28
29struct atom_clock_dividers {
30	u32 post_div;
31	union {
32		struct {
33#ifdef __BIG_ENDIAN
34			u32 reserved : 6;
35			u32 whole_fb_div : 12;
36			u32 frac_fb_div : 14;
37#else
38			u32 frac_fb_div : 14;
39			u32 whole_fb_div : 12;
40			u32 reserved : 6;
41#endif
42		};
43		u32 fb_div;
44	};
45	u32 ref_div;
46	bool enable_post_div;
47	bool enable_dithen;
48	u32 vco_mode;
49	u32 real_clock;
50	/* added for CI */
51	u32 post_divider;
52	u32 flags;
53};
54
55struct atom_mpll_param {
56	union {
57		struct {
58#ifdef __BIG_ENDIAN
59			u32 reserved : 8;
60			u32 clkfrac : 12;
61			u32 clkf : 12;
62#else
63			u32 clkf : 12;
64			u32 clkfrac : 12;
65			u32 reserved : 8;
66#endif
67		};
68		u32 fb_div;
69	};
70	u32 post_div;
71	u32 bwcntl;
72	u32 dll_speed;
73	u32 vco_mode;
74	u32 yclk_sel;
75	u32 qdr;
76	u32 half_rate;
77};
78
79#define MEM_TYPE_GDDR5  0x50
80#define MEM_TYPE_GDDR4  0x40
81#define MEM_TYPE_GDDR3  0x30
82#define MEM_TYPE_DDR2   0x20
83#define MEM_TYPE_GDDR1  0x10
84#define MEM_TYPE_DDR3   0xb0
85#define MEM_TYPE_MASK   0xf0
86
87struct atom_memory_info {
88	u8 mem_vendor;
89	u8 mem_type;
90};
91
92#define MAX_AC_TIMING_ENTRIES 16
93
94struct atom_memory_clock_range_table
95{
96	u8 num_entries;
97	u8 rsv[3];
98	u32 mclk[MAX_AC_TIMING_ENTRIES];
99};
100
101#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
102#define VBIOS_MAX_AC_TIMING_ENTRIES 20
103
104struct atom_mc_reg_entry {
105	u32 mclk_max;
106	u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
107};
108
109struct atom_mc_register_address {
110	u16 s1;
111	u8 pre_reg_data;
112};
113
114struct atom_mc_reg_table {
115	u8 last;
116	u8 num_entries;
117	struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
118	struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
119};
120
121#define MAX_VOLTAGE_ENTRIES 32
122
123struct atom_voltage_table_entry
124{
125	u16 value;
126	u32 smio_low;
127};
128
129struct atom_voltage_table
130{
131	u32 count;
132	u32 mask_low;
133	u32 phase_delay;
134	struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
135};
136
137struct amdgpu_gpio_rec
138amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
139			    u8 id);
140
141struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
142							  uint8_t id);
143void amdgpu_atombios_i2c_init(struct amdgpu_device *adev);
144
145bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev);
146
147int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev);
148
149bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
150				      struct amdgpu_atom_ss *ss,
151				      int id, u32 clock);
152
153int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
154				       u8 clock_type,
155				       u32 clock,
156				       bool strobe_mode,
157				       struct atom_clock_dividers *dividers);
158
159int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
160					    u32 clock,
161					    bool strobe_mode,
162					    struct atom_mpll_param *mpll_param);
163
164uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev);
165uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev);
166void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
167				      uint32_t eng_clock);
168void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
169				      uint32_t mem_clock);
170void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
171				 u16 voltage_level,
172				 u8 voltage_type);
173
174void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
175					     u32 eng_clock, u32 mem_clock);
176
177int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
178					      u16 *leakage_id);
179
180int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
181							     u16 *vddc, u16 *vddci,
182							     u16 virtual_voltage_id,
183							     u16 vbios_voltage_id);
184
185int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
186				    u16 virtual_voltage_id,
187				    u16 *voltage);
188
189bool
190amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
191				u8 voltage_type, u8 voltage_mode);
192
193int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
194				      u8 voltage_type, u8 voltage_mode,
195				      struct atom_voltage_table *voltage_table);
196
197int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
198				      u8 module_index,
199				      struct atom_mc_reg_table *reg_table);
200
201void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
202void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev);
203void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev);
204void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev);
205
206void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
207
208#endif
209