11.1Sjmcneill#include "bcm283x.dtsi"
21.1.1.4Sskrll#include "bcm2835-common.dtsi"
31.1.1.5Sjmcneill#include "bcm2835-rpi-common.dtsi"
41.1Sjmcneill
51.1Sjmcneill/ {
61.1Sjmcneill	compatible = "brcm,bcm2837";
71.1Sjmcneill
81.1Sjmcneill	soc {
91.1Sjmcneill		ranges = <0x7e000000 0x3f000000 0x1000000>,
101.1Sjmcneill			 <0x40000000 0x40000000 0x00001000>;
111.1Sjmcneill		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
121.1Sjmcneill
131.1.1.2Sjmcneill		local_intc: local_intc@40000000 {
141.1Sjmcneill			compatible = "brcm,bcm2836-l1-intc";
151.1Sjmcneill			reg = <0x40000000 0x100>;
161.1Sjmcneill			interrupt-controller;
171.1.1.2Sjmcneill			#interrupt-cells = <2>;
181.1Sjmcneill			interrupt-parent = <&local_intc>;
191.1Sjmcneill		};
201.1Sjmcneill	};
211.1Sjmcneill
221.1.1.3Sjmcneill	arm-pmu {
231.1.1.3Sjmcneill		compatible = "arm,cortex-a53-pmu";
241.1.1.3Sjmcneill		interrupt-parent = <&local_intc>;
251.1.1.3Sjmcneill		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
261.1.1.3Sjmcneill	};
271.1.1.3Sjmcneill
281.1Sjmcneill	timer {
291.1Sjmcneill		compatible = "arm,armv7-timer";
301.1Sjmcneill		interrupt-parent = <&local_intc>;
311.1.1.2Sjmcneill		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
321.1.1.2Sjmcneill			     <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
331.1.1.2Sjmcneill			     <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
341.1.1.2Sjmcneill			     <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
351.1Sjmcneill		always-on;
361.1Sjmcneill	};
371.1Sjmcneill
381.1Sjmcneill	cpus: cpus {
391.1Sjmcneill		#address-cells = <1>;
401.1Sjmcneill		#size-cells = <0>;
411.1Sjmcneill		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
421.1Sjmcneill
431.1Sjmcneill		cpu0: cpu@0 {
441.1Sjmcneill			device_type = "cpu";
451.1Sjmcneill			compatible = "arm,cortex-a53";
461.1Sjmcneill			reg = <0>;
471.1Sjmcneill			enable-method = "spin-table";
481.1Sjmcneill			cpu-release-addr = <0x0 0x000000d8>;
491.1Sjmcneill		};
501.1Sjmcneill
511.1Sjmcneill		cpu1: cpu@1 {
521.1Sjmcneill			device_type = "cpu";
531.1Sjmcneill			compatible = "arm,cortex-a53";
541.1Sjmcneill			reg = <1>;
551.1Sjmcneill			enable-method = "spin-table";
561.1Sjmcneill			cpu-release-addr = <0x0 0x000000e0>;
571.1Sjmcneill		};
581.1Sjmcneill
591.1Sjmcneill		cpu2: cpu@2 {
601.1Sjmcneill			device_type = "cpu";
611.1Sjmcneill			compatible = "arm,cortex-a53";
621.1Sjmcneill			reg = <2>;
631.1Sjmcneill			enable-method = "spin-table";
641.1Sjmcneill			cpu-release-addr = <0x0 0x000000e8>;
651.1Sjmcneill		};
661.1Sjmcneill
671.1Sjmcneill		cpu3: cpu@3 {
681.1Sjmcneill			device_type = "cpu";
691.1Sjmcneill			compatible = "arm,cortex-a53";
701.1Sjmcneill			reg = <3>;
711.1Sjmcneill			enable-method = "spin-table";
721.1Sjmcneill			cpu-release-addr = <0x0 0x000000f0>;
731.1Sjmcneill		};
741.1Sjmcneill	};
751.1Sjmcneill};
761.1Sjmcneill
771.1Sjmcneill/* Make the BCM2835-style global interrupt controller be a child of the
781.1Sjmcneill * CPU-local interrupt controller.
791.1Sjmcneill */
801.1Sjmcneill&intc {
811.1Sjmcneill	compatible = "brcm,bcm2836-armctrl-ic";
821.1Sjmcneill	reg = <0x7e00b200 0x200>;
831.1Sjmcneill	interrupt-parent = <&local_intc>;
841.1.1.2Sjmcneill	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
851.1Sjmcneill};
861.1Sjmcneill
871.1Sjmcneill&cpu_thermal {
881.1Sjmcneill	coefficients = <(-538)	412000>;
891.1Sjmcneill};
901.1Sjmcneill
911.1Sjmcneill/* enable thermal sensor with the correct compatible property set */
921.1Sjmcneill&thermal {
931.1Sjmcneill	compatible = "brcm,bcm2837-thermal";
941.1Sjmcneill	status = "okay";
951.1Sjmcneill};
96