11.1Sjmcneill/* $NetBSD: axis,artpec6-clkctrl.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 21.1Sjmcneill 31.1.1.2Sskrll/* SPDX-License-Identifier: GPL-2.0-only */ 41.1Sjmcneill/* 51.1Sjmcneill * ARTPEC-6 clock controller indexes 61.1Sjmcneill * 71.1Sjmcneill * Copyright 2016 Axis Comunications AB. 81.1Sjmcneill */ 91.1Sjmcneill 101.1Sjmcneill#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H 111.1Sjmcneill#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H 121.1Sjmcneill 131.1Sjmcneill#define ARTPEC6_CLK_CPU 0 141.1Sjmcneill#define ARTPEC6_CLK_CPU_PERIPH 1 151.1Sjmcneill#define ARTPEC6_CLK_NAND_CLKA 2 161.1Sjmcneill#define ARTPEC6_CLK_NAND_CLKB 3 171.1Sjmcneill#define ARTPEC6_CLK_ETH_ACLK 4 181.1Sjmcneill#define ARTPEC6_CLK_DMA_ACLK 5 191.1Sjmcneill#define ARTPEC6_CLK_PTP_REF 6 201.1Sjmcneill#define ARTPEC6_CLK_SD_PCLK 7 211.1Sjmcneill#define ARTPEC6_CLK_SD_IMCLK 8 221.1Sjmcneill#define ARTPEC6_CLK_I2S_HST 9 231.1Sjmcneill#define ARTPEC6_CLK_I2S0_CLK 10 241.1Sjmcneill#define ARTPEC6_CLK_I2S1_CLK 11 251.1Sjmcneill#define ARTPEC6_CLK_UART_PCLK 12 261.1Sjmcneill#define ARTPEC6_CLK_UART_REFCLK 13 271.1Sjmcneill#define ARTPEC6_CLK_I2C 14 281.1Sjmcneill#define ARTPEC6_CLK_SPI_PCLK 15 291.1Sjmcneill#define ARTPEC6_CLK_SPI_SSPCLK 16 301.1Sjmcneill#define ARTPEC6_CLK_SYS_TIMER 17 311.1Sjmcneill#define ARTPEC6_CLK_FRACDIV_IN 18 321.1Sjmcneill#define ARTPEC6_CLK_DBG_PCLK 19 331.1Sjmcneill 341.1Sjmcneill/* This must be the highest clock index plus one. */ 351.1Sjmcneill#define ARTPEC6_CLK_NUMCLOCKS 20 361.1Sjmcneill 371.1Sjmcneill#endif 38