11.1Sjmcneill/* $NetBSD: hi3516cv300-clock.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 21.1Sjmcneill 31.1.1.2Sskrll/* SPDX-License-Identifier: GPL-2.0-or-later */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef __DTS_HI3516CV300_CLOCK_H 91.1Sjmcneill#define __DTS_HI3516CV300_CLOCK_H 101.1Sjmcneill 111.1Sjmcneill/* hi3516CV300 core CRG */ 121.1Sjmcneill#define HI3516CV300_APB_CLK 0 131.1Sjmcneill#define HI3516CV300_UART0_CLK 1 141.1Sjmcneill#define HI3516CV300_UART1_CLK 2 151.1Sjmcneill#define HI3516CV300_UART2_CLK 3 161.1Sjmcneill#define HI3516CV300_SPI0_CLK 4 171.1Sjmcneill#define HI3516CV300_SPI1_CLK 5 181.1Sjmcneill#define HI3516CV300_FMC_CLK 6 191.1Sjmcneill#define HI3516CV300_MMC0_CLK 7 201.1Sjmcneill#define HI3516CV300_MMC1_CLK 8 211.1Sjmcneill#define HI3516CV300_MMC2_CLK 9 221.1Sjmcneill#define HI3516CV300_MMC3_CLK 10 231.1Sjmcneill#define HI3516CV300_ETH_CLK 11 241.1Sjmcneill#define HI3516CV300_ETH_MACIF_CLK 12 251.1Sjmcneill#define HI3516CV300_DMAC_CLK 13 261.1Sjmcneill#define HI3516CV300_PWM_CLK 14 271.1Sjmcneill#define HI3516CV300_USB2_BUS_CLK 15 281.1Sjmcneill#define HI3516CV300_USB2_OHCI48M_CLK 16 291.1Sjmcneill#define HI3516CV300_USB2_OHCI12M_CLK 17 301.1Sjmcneill#define HI3516CV300_USB2_OTG_UTMI_CLK 18 311.1Sjmcneill#define HI3516CV300_USB2_HST_PHY_CLK 19 321.1Sjmcneill#define HI3516CV300_USB2_UTMI0_CLK 20 331.1Sjmcneill#define HI3516CV300_USB2_PHY_CLK 21 341.1Sjmcneill 351.1Sjmcneill/* hi3516CV300 sysctrl CRG */ 361.1Sjmcneill#define HI3516CV300_WDT_CLK 1 371.1Sjmcneill 381.1Sjmcneill#endif /* __DTS_HI3516CV300_CLOCK_H */ 39