11.1Sjmcneill/* $NetBSD: hi3519-clock.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 21.1Sjmcneill 31.1.1.2Sskrll/* SPDX-License-Identifier: GPL-2.0-or-later */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef __DTS_HI3519_CLOCK_H 91.1Sjmcneill#define __DTS_HI3519_CLOCK_H 101.1Sjmcneill 111.1Sjmcneill#define HI3519_FMC_CLK 1 121.1Sjmcneill#define HI3519_SPI0_CLK 2 131.1Sjmcneill#define HI3519_SPI1_CLK 3 141.1Sjmcneill#define HI3519_SPI2_CLK 4 151.1Sjmcneill#define HI3519_UART0_CLK 5 161.1Sjmcneill#define HI3519_UART1_CLK 6 171.1Sjmcneill#define HI3519_UART2_CLK 7 181.1Sjmcneill#define HI3519_UART3_CLK 8 191.1Sjmcneill#define HI3519_UART4_CLK 9 201.1Sjmcneill#define HI3519_PWM_CLK 10 211.1Sjmcneill#define HI3519_DMA_CLK 11 221.1Sjmcneill#define HI3519_IR_CLK 12 231.1Sjmcneill#define HI3519_ETH_PHY_CLK 13 241.1Sjmcneill#define HI3519_ETH_MAC_CLK 14 251.1Sjmcneill#define HI3519_ETH_MACIF_CLK 15 261.1Sjmcneill#define HI3519_USB2_BUS_CLK 16 271.1Sjmcneill#define HI3519_USB2_PORT_CLK 17 281.1Sjmcneill#define HI3519_USB3_CLK 18 291.1Sjmcneill 301.1Sjmcneill#endif /* __DTS_HI3519_CLOCK_H */ 31