hi6220-clock.h revision 1.1.1.3 
1/*	$NetBSD: hi6220-clock.h,v 1.1.1.3 2017/10/28 10:30:32 jmcneill Exp $	*/
2
3/*
4 * Copyright (c) 2015 Hisilicon Limited.
5 *
6 * Author: Bintian Wang <bintian.wang@huawei.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __DT_BINDINGS_CLOCK_HI6220_H
14#define __DT_BINDINGS_CLOCK_HI6220_H
15
16/* clk in Hi6220 AO (always on) controller */
17#define HI6220_NONE_CLOCK	0
18
19/* fixed rate clocks */
20#define HI6220_REF32K		1
21#define HI6220_CLK_TCXO		2
22#define HI6220_MMC1_PAD		3
23#define HI6220_MMC2_PAD		4
24#define HI6220_MMC0_PAD		5
25#define HI6220_PLL_BBP		6
26#define HI6220_PLL_GPU		7
27#define HI6220_PLL1_DDR		8
28#define HI6220_PLL_SYS		9
29#define HI6220_PLL_SYS_MEDIA	10
30#define HI6220_DDR_SRC		11
31#define HI6220_PLL_MEDIA	12
32#define HI6220_PLL_DDR		13
33
34/* fixed factor clocks */
35#define HI6220_300M		14
36#define HI6220_150M		15
37#define HI6220_PICOPHY_SRC	16
38#define HI6220_MMC0_SRC_SEL	17
39#define HI6220_MMC1_SRC_SEL	18
40#define HI6220_MMC2_SRC_SEL	19
41#define HI6220_VPU_CODEC	20
42#define HI6220_MMC0_SMP		21
43#define HI6220_MMC1_SMP		22
44#define HI6220_MMC2_SMP		23
45
46/* gate clocks */
47#define HI6220_WDT0_PCLK	24
48#define HI6220_WDT1_PCLK	25
49#define HI6220_WDT2_PCLK	26
50#define HI6220_TIMER0_PCLK	27
51#define HI6220_TIMER1_PCLK	28
52#define HI6220_TIMER2_PCLK	29
53#define HI6220_TIMER3_PCLK	30
54#define HI6220_TIMER4_PCLK	31
55#define HI6220_TIMER5_PCLK	32
56#define HI6220_TIMER6_PCLK	33
57#define HI6220_TIMER7_PCLK	34
58#define HI6220_TIMER8_PCLK	35
59#define HI6220_UART0_PCLK	36
60#define HI6220_RTC0_PCLK	37
61#define HI6220_RTC1_PCLK	38
62#define HI6220_AO_NR_CLKS	39
63
64/* clk in Hi6220 systrl */
65/* gate clock */
66#define HI6220_MMC0_CLK		1
67#define HI6220_MMC0_CIUCLK	2
68#define HI6220_MMC1_CLK		3
69#define HI6220_MMC1_CIUCLK	4
70#define HI6220_MMC2_CLK		5
71#define HI6220_MMC2_CIUCLK	6
72#define HI6220_USBOTG_HCLK	7
73#define HI6220_CLK_PICOPHY	8
74#define HI6220_HIFI		9
75#define HI6220_DACODEC_PCLK	10
76#define HI6220_EDMAC_ACLK	11
77#define HI6220_CS_ATB		12
78#define HI6220_I2C0_CLK		13
79#define HI6220_I2C1_CLK		14
80#define HI6220_I2C2_CLK		15
81#define HI6220_I2C3_CLK		16
82#define HI6220_UART1_PCLK	17
83#define HI6220_UART2_PCLK	18
84#define HI6220_UART3_PCLK	19
85#define HI6220_UART4_PCLK	20
86#define HI6220_SPI_CLK		21
87#define HI6220_TSENSOR_CLK	22
88#define HI6220_MMU_CLK		23
89#define HI6220_HIFI_SEL		24
90#define HI6220_MMC0_SYSPLL	25
91#define HI6220_MMC1_SYSPLL	26
92#define HI6220_MMC2_SYSPLL	27
93#define HI6220_MMC0_SEL		28
94#define HI6220_MMC1_SEL		29
95#define HI6220_BBPPLL_SEL	30
96#define HI6220_MEDIA_PLL_SRC	31
97#define HI6220_MMC2_SEL		32
98#define HI6220_CS_ATB_SYSPLL	33
99
100/* mux clocks */
101#define HI6220_MMC0_SRC		34
102#define HI6220_MMC0_SMP_IN	35
103#define HI6220_MMC1_SRC		36
104#define HI6220_MMC1_SMP_IN	37
105#define HI6220_MMC2_SRC		38
106#define HI6220_MMC2_SMP_IN	39
107#define HI6220_HIFI_SRC		40
108#define HI6220_UART1_SRC	41
109#define HI6220_UART2_SRC	42
110#define HI6220_UART3_SRC	43
111#define HI6220_UART4_SRC	44
112#define HI6220_MMC0_MUX0	45
113#define HI6220_MMC1_MUX0	46
114#define HI6220_MMC2_MUX0	47
115#define HI6220_MMC0_MUX1	48
116#define HI6220_MMC1_MUX1	49
117#define HI6220_MMC2_MUX1	50
118
119/* divider clocks */
120#define HI6220_CLK_BUS		51
121#define HI6220_MMC0_DIV		52
122#define HI6220_MMC1_DIV		53
123#define HI6220_MMC2_DIV		54
124#define HI6220_HIFI_DIV		55
125#define HI6220_BBPPLL0_DIV	56
126#define HI6220_CS_DAPB		57
127#define HI6220_CS_ATB_DIV	58
128
129/* gate clock */
130#define HI6220_DAPB_CLK		59
131
132#define HI6220_SYS_NR_CLKS	60
133
134/* clk in Hi6220 media controller */
135/* gate clocks */
136#define HI6220_DSI_PCLK		1
137#define HI6220_G3D_PCLK		2
138#define HI6220_ACLK_CODEC_VPU	3
139#define HI6220_ISP_SCLK		4
140#define HI6220_ADE_CORE		5
141#define HI6220_MED_MMU		6
142#define HI6220_CFG_CSI4PHY	7
143#define HI6220_CFG_CSI2PHY	8
144#define HI6220_ISP_SCLK_GATE	9
145#define HI6220_ISP_SCLK_GATE1	10
146#define HI6220_ADE_CORE_GATE	11
147#define HI6220_CODEC_VPU_GATE	12
148#define HI6220_MED_SYSPLL	13
149
150/* mux clocks */
151#define HI6220_1440_1200	14
152#define HI6220_1000_1200	15
153#define HI6220_1000_1440	16
154
155/* divider clocks */
156#define HI6220_CODEC_JPEG	17
157#define HI6220_ISP_SCLK_SRC	18
158#define HI6220_ISP_SCLK1	19
159#define HI6220_ADE_CORE_SRC	20
160#define HI6220_ADE_PIX_SRC	21
161#define HI6220_G3D_CLK		22
162#define HI6220_CODEC_VPU_SRC	23
163
164#define HI6220_MEDIA_NR_CLKS	24
165
166/* clk in Hi6220 power controller */
167/* gate clocks */
168#define HI6220_PLL_GPU_GATE	1
169#define HI6220_PLL1_DDR_GATE	2
170#define HI6220_PLL_DDR_GATE	3
171#define HI6220_PLL_MEDIA_GATE	4
172#define HI6220_PLL0_BBP_GATE	5
173
174/* divider clocks */
175#define HI6220_DDRC_SRC		6
176#define HI6220_DDRC_AXI1	7
177
178#define HI6220_POWER_NR_CLKS	8
179
180/* clk in Hi6220 acpu sctrl */
181#define HI6220_ACPU_SFT_AT_S		0
182
183#endif
184