imx7ulp-clock.h revision 1.1.1.1 
1/*	$NetBSD: imx7ulp-clock.h,v 1.1.1.1 2019/05/25 11:29:13 jmcneill Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0+ */
4/*
5 * Copyright (C) 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017~2018 NXP
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
11#define __DT_BINDINGS_CLOCK_IMX7ULP_H
12
13/* SCG1 */
14
15#define IMX7ULP_CLK_DUMMY		0
16#define IMX7ULP_CLK_ROSC		1
17#define IMX7ULP_CLK_SOSC		2
18#define IMX7ULP_CLK_FIRC		3
19#define IMX7ULP_CLK_SPLL_PRE_SEL	4
20#define IMX7ULP_CLK_SPLL_PRE_DIV	5
21#define IMX7ULP_CLK_SPLL		6
22#define IMX7ULP_CLK_SPLL_POST_DIV1	7
23#define IMX7ULP_CLK_SPLL_POST_DIV2	8
24#define IMX7ULP_CLK_SPLL_PFD0		9
25#define IMX7ULP_CLK_SPLL_PFD1		10
26#define IMX7ULP_CLK_SPLL_PFD2		11
27#define IMX7ULP_CLK_SPLL_PFD3		12
28#define IMX7ULP_CLK_SPLL_PFD_SEL	13
29#define IMX7ULP_CLK_SPLL_SEL		14
30#define IMX7ULP_CLK_APLL_PRE_SEL	15
31#define IMX7ULP_CLK_APLL_PRE_DIV	16
32#define IMX7ULP_CLK_APLL		17
33#define IMX7ULP_CLK_APLL_POST_DIV1	18
34#define IMX7ULP_CLK_APLL_POST_DIV2	19
35#define IMX7ULP_CLK_APLL_PFD0		20
36#define IMX7ULP_CLK_APLL_PFD1		21
37#define IMX7ULP_CLK_APLL_PFD2		22
38#define IMX7ULP_CLK_APLL_PFD3		23
39#define IMX7ULP_CLK_APLL_PFD_SEL	24
40#define IMX7ULP_CLK_APLL_SEL		25
41#define IMX7ULP_CLK_UPLL		26
42#define IMX7ULP_CLK_SYS_SEL		27
43#define IMX7ULP_CLK_CORE_DIV		28
44#define IMX7ULP_CLK_BUS_DIV		29
45#define IMX7ULP_CLK_PLAT_DIV		30
46#define IMX7ULP_CLK_DDR_SEL		31
47#define IMX7ULP_CLK_DDR_DIV		32
48#define IMX7ULP_CLK_NIC_SEL		33
49#define IMX7ULP_CLK_NIC0_DIV		34
50#define IMX7ULP_CLK_GPU_DIV		35
51#define IMX7ULP_CLK_NIC1_DIV		36
52#define IMX7ULP_CLK_NIC1_BUS_DIV	37
53#define IMX7ULP_CLK_NIC1_EXT_DIV	38
54#define IMX7ULP_CLK_MIPI_PLL		39
55#define IMX7ULP_CLK_SIRC		40
56#define IMX7ULP_CLK_SOSC_BUS_CLK	41
57#define IMX7ULP_CLK_FIRC_BUS_CLK	42
58#define IMX7ULP_CLK_SPLL_BUS_CLK	43
59#define IMX7ULP_CLK_HSRUN_SYS_SEL	44
60#define IMX7ULP_CLK_HSRUN_CORE_DIV	45
61
62#define IMX7ULP_CLK_SCG1_END		46
63
64/* PCC2 */
65#define IMX7ULP_CLK_DMA1		0
66#define IMX7ULP_CLK_RGPIO2P1		1
67#define IMX7ULP_CLK_FLEXBUS		2
68#define IMX7ULP_CLK_SEMA42_1		3
69#define IMX7ULP_CLK_DMA_MUX1		4
70#define IMX7ULP_CLK_SNVS		5
71#define IMX7ULP_CLK_CAAM		6
72#define IMX7ULP_CLK_LPTPM4		7
73#define IMX7ULP_CLK_LPTPM5		8
74#define IMX7ULP_CLK_LPIT1		9
75#define IMX7ULP_CLK_LPSPI2		10
76#define IMX7ULP_CLK_LPSPI3		11
77#define IMX7ULP_CLK_LPI2C4		12
78#define IMX7ULP_CLK_LPI2C5		13
79#define IMX7ULP_CLK_LPUART4		14
80#define IMX7ULP_CLK_LPUART5		15
81#define IMX7ULP_CLK_FLEXIO1		16
82#define IMX7ULP_CLK_USB0		17
83#define IMX7ULP_CLK_USB1		18
84#define IMX7ULP_CLK_USB_PHY		19
85#define IMX7ULP_CLK_USB_PL301		20
86#define IMX7ULP_CLK_USDHC0		21
87#define IMX7ULP_CLK_USDHC1		22
88#define IMX7ULP_CLK_WDG1		23
89#define IMX7ULP_CLK_WDG2		24
90
91#define IMX7ULP_CLK_PCC2_END		25
92
93/* PCC3 */
94#define IMX7ULP_CLK_LPTPM6		0
95#define IMX7ULP_CLK_LPTPM7		1
96#define IMX7ULP_CLK_LPI2C6		2
97#define IMX7ULP_CLK_LPI2C7		3
98#define IMX7ULP_CLK_LPUART6		4
99#define IMX7ULP_CLK_LPUART7		5
100#define IMX7ULP_CLK_VIU			6
101#define IMX7ULP_CLK_DSI			7
102#define IMX7ULP_CLK_LCDIF		8
103#define IMX7ULP_CLK_MMDC		9
104#define IMX7ULP_CLK_PCTLC		10
105#define IMX7ULP_CLK_PCTLD		11
106#define IMX7ULP_CLK_PCTLE		12
107#define IMX7ULP_CLK_PCTLF		13
108#define IMX7ULP_CLK_GPU3D		14
109#define IMX7ULP_CLK_GPU2D		15
110
111#define IMX7ULP_CLK_PCC3_END		16
112
113/* SMC1 */
114#define IMX7ULP_CLK_ARM			0
115
116#define IMX7ULP_CLK_SMC1_END		1
117
118#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
119