11.1Sjmcneill/* $NetBSD: jz4725b-cgu.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sjmcneill/* 51.1Sjmcneill * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ 91.1Sjmcneill#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ 101.1Sjmcneill 111.1Sjmcneill#define JZ4725B_CLK_EXT 0 121.1Sjmcneill#define JZ4725B_CLK_OSC32K 1 131.1Sjmcneill#define JZ4725B_CLK_PLL 2 141.1Sjmcneill#define JZ4725B_CLK_PLL_HALF 3 151.1Sjmcneill#define JZ4725B_CLK_CCLK 4 161.1Sjmcneill#define JZ4725B_CLK_HCLK 5 171.1Sjmcneill#define JZ4725B_CLK_PCLK 6 181.1Sjmcneill#define JZ4725B_CLK_MCLK 7 191.1Sjmcneill#define JZ4725B_CLK_IPU 8 201.1Sjmcneill#define JZ4725B_CLK_LCD 9 211.1Sjmcneill#define JZ4725B_CLK_I2S 10 221.1Sjmcneill#define JZ4725B_CLK_SPI 11 231.1Sjmcneill#define JZ4725B_CLK_MMC_MUX 12 241.1Sjmcneill#define JZ4725B_CLK_UDC 13 251.1Sjmcneill#define JZ4725B_CLK_UART 14 261.1Sjmcneill#define JZ4725B_CLK_DMA 15 271.1Sjmcneill#define JZ4725B_CLK_ADC 16 281.1Sjmcneill#define JZ4725B_CLK_I2C 17 291.1Sjmcneill#define JZ4725B_CLK_AIC 18 301.1Sjmcneill#define JZ4725B_CLK_MMC0 19 311.1Sjmcneill#define JZ4725B_CLK_MMC1 20 321.1Sjmcneill#define JZ4725B_CLK_BCH 21 331.1Sjmcneill#define JZ4725B_CLK_TCU 22 341.1Sjmcneill#define JZ4725B_CLK_EXT512 23 351.1Sjmcneill#define JZ4725B_CLK_RTC 24 361.1.1.2Sskrll#define JZ4725B_CLK_UDC_PHY 25 371.1Sjmcneill 381.1Sjmcneill#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ 39