1/* $NetBSD: marvell,mmp2.h,v 1.1.1.4 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4#ifndef __DTS_MARVELL_MMP2_CLOCK_H 5#define __DTS_MARVELL_MMP2_CLOCK_H 6 7/* fixed clocks and plls */ 8#define MMP2_CLK_CLK32 1 9#define MMP2_CLK_VCTCXO 2 10#define MMP2_CLK_PLL1 3 11#define MMP2_CLK_PLL1_2 8 12#define MMP2_CLK_PLL1_4 9 13#define MMP2_CLK_PLL1_8 10 14#define MMP2_CLK_PLL1_16 11 15#define MMP2_CLK_PLL1_3 12 16#define MMP2_CLK_PLL1_6 13 17#define MMP2_CLK_PLL1_12 14 18#define MMP2_CLK_PLL1_20 15 19#define MMP2_CLK_PLL2 16 20#define MMP2_CLK_PLL2_2 17 21#define MMP2_CLK_PLL2_4 18 22#define MMP2_CLK_PLL2_8 19 23#define MMP2_CLK_PLL2_16 20 24#define MMP2_CLK_PLL2_3 21 25#define MMP2_CLK_PLL2_6 22 26#define MMP2_CLK_PLL2_12 23 27#define MMP2_CLK_VCTCXO_2 24 28#define MMP2_CLK_VCTCXO_4 25 29#define MMP2_CLK_UART_PLL 26 30#define MMP2_CLK_USB_PLL 27 31#define MMP3_CLK_PLL1_P 28 32#define MMP3_CLK_PLL2_P 29 33#define MMP3_CLK_PLL3 30 34#define MMP2_CLK_I2S0 31 35#define MMP2_CLK_I2S1 32 36 37/* apb periphrals */ 38#define MMP2_CLK_TWSI0 60 39#define MMP2_CLK_TWSI1 61 40#define MMP2_CLK_TWSI2 62 41#define MMP2_CLK_TWSI3 63 42#define MMP2_CLK_TWSI4 64 43#define MMP2_CLK_TWSI5 65 44#define MMP2_CLK_GPIO 66 45#define MMP2_CLK_KPC 67 46#define MMP2_CLK_RTC 68 47#define MMP2_CLK_PWM0 69 48#define MMP2_CLK_PWM1 70 49#define MMP2_CLK_PWM2 71 50#define MMP2_CLK_PWM3 72 51#define MMP2_CLK_UART0 73 52#define MMP2_CLK_UART1 74 53#define MMP2_CLK_UART2 75 54#define MMP2_CLK_UART3 76 55#define MMP2_CLK_SSP0 77 56#define MMP2_CLK_SSP1 78 57#define MMP2_CLK_SSP2 79 58#define MMP2_CLK_SSP3 80 59#define MMP2_CLK_TIMER 81 60#define MMP2_CLK_THERMAL0 82 61#define MMP3_CLK_THERMAL1 83 62#define MMP3_CLK_THERMAL2 84 63#define MMP3_CLK_THERMAL3 85 64 65/* axi periphrals */ 66#define MMP2_CLK_SDH0 101 67#define MMP2_CLK_SDH1 102 68#define MMP2_CLK_SDH2 103 69#define MMP2_CLK_SDH3 104 70#define MMP2_CLK_USB 105 71#define MMP2_CLK_DISP0 106 72#define MMP2_CLK_DISP0_MUX 107 73#define MMP2_CLK_DISP0_SPHY 108 74#define MMP2_CLK_DISP1 109 75#define MMP2_CLK_DISP1_MUX 110 76#define MMP2_CLK_CCIC_ARBITER 111 77#define MMP2_CLK_CCIC0 112 78#define MMP2_CLK_CCIC0_MIX 113 79#define MMP2_CLK_CCIC0_PHY 114 80#define MMP2_CLK_CCIC0_SPHY 115 81#define MMP2_CLK_CCIC1 116 82#define MMP2_CLK_CCIC1_MIX 117 83#define MMP2_CLK_CCIC1_PHY 118 84#define MMP2_CLK_CCIC1_SPHY 119 85#define MMP2_CLK_DISP0_LCDC 120 86#define MMP2_CLK_USBHSIC0 121 87#define MMP2_CLK_USBHSIC1 122 88#define MMP2_CLK_GPU_BUS 123 89#define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS 90#define MMP2_CLK_GPU_3D 124 91#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D 92#define MMP3_CLK_GPU_2D 125 93#define MMP3_CLK_SDH4 126 94#define MMP2_CLK_AUDIO 127 95 96#define MMP2_NR_CLKS 200 97#endif 98