qcom,camcc-sc7180.h revision 1.1.1.1
1/* $NetBSD: qcom,camcc-sc7180.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only */ 4/* 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 */ 7 8#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H 9#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7180_H 10 11/* CAM_CC clocks */ 12#define CAM_CC_PLL2_OUT_EARLY 0 13#define CAM_CC_PLL0 1 14#define CAM_CC_PLL1 2 15#define CAM_CC_PLL2 3 16#define CAM_CC_PLL2_OUT_AUX 4 17#define CAM_CC_PLL3 5 18#define CAM_CC_CAMNOC_AXI_CLK 6 19#define CAM_CC_CCI_0_CLK 7 20#define CAM_CC_CCI_0_CLK_SRC 8 21#define CAM_CC_CCI_1_CLK 9 22#define CAM_CC_CCI_1_CLK_SRC 10 23#define CAM_CC_CORE_AHB_CLK 11 24#define CAM_CC_CPAS_AHB_CLK 12 25#define CAM_CC_CPHY_RX_CLK_SRC 13 26#define CAM_CC_CSI0PHYTIMER_CLK 14 27#define CAM_CC_CSI0PHYTIMER_CLK_SRC 15 28#define CAM_CC_CSI1PHYTIMER_CLK 16 29#define CAM_CC_CSI1PHYTIMER_CLK_SRC 17 30#define CAM_CC_CSI2PHYTIMER_CLK 18 31#define CAM_CC_CSI2PHYTIMER_CLK_SRC 19 32#define CAM_CC_CSI3PHYTIMER_CLK 20 33#define CAM_CC_CSI3PHYTIMER_CLK_SRC 21 34#define CAM_CC_CSIPHY0_CLK 22 35#define CAM_CC_CSIPHY1_CLK 23 36#define CAM_CC_CSIPHY2_CLK 24 37#define CAM_CC_CSIPHY3_CLK 25 38#define CAM_CC_FAST_AHB_CLK_SRC 26 39#define CAM_CC_ICP_APB_CLK 27 40#define CAM_CC_ICP_ATB_CLK 28 41#define CAM_CC_ICP_CLK 29 42#define CAM_CC_ICP_CLK_SRC 30 43#define CAM_CC_ICP_CTI_CLK 31 44#define CAM_CC_ICP_TS_CLK 32 45#define CAM_CC_IFE_0_AXI_CLK 33 46#define CAM_CC_IFE_0_CLK 34 47#define CAM_CC_IFE_0_CLK_SRC 35 48#define CAM_CC_IFE_0_CPHY_RX_CLK 36 49#define CAM_CC_IFE_0_CSID_CLK 37 50#define CAM_CC_IFE_0_CSID_CLK_SRC 38 51#define CAM_CC_IFE_0_DSP_CLK 39 52#define CAM_CC_IFE_1_AXI_CLK 40 53#define CAM_CC_IFE_1_CLK 41 54#define CAM_CC_IFE_1_CLK_SRC 42 55#define CAM_CC_IFE_1_CPHY_RX_CLK 43 56#define CAM_CC_IFE_1_CSID_CLK 44 57#define CAM_CC_IFE_1_CSID_CLK_SRC 45 58#define CAM_CC_IFE_1_DSP_CLK 46 59#define CAM_CC_IFE_LITE_CLK 47 60#define CAM_CC_IFE_LITE_CLK_SRC 48 61#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 62#define CAM_CC_IFE_LITE_CSID_CLK 50 63#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 64#define CAM_CC_IPE_0_AHB_CLK 52 65#define CAM_CC_IPE_0_AREG_CLK 53 66#define CAM_CC_IPE_0_AXI_CLK 54 67#define CAM_CC_IPE_0_CLK 55 68#define CAM_CC_IPE_0_CLK_SRC 56 69#define CAM_CC_JPEG_CLK 57 70#define CAM_CC_JPEG_CLK_SRC 58 71#define CAM_CC_LRME_CLK 59 72#define CAM_CC_LRME_CLK_SRC 60 73#define CAM_CC_MCLK0_CLK 61 74#define CAM_CC_MCLK0_CLK_SRC 62 75#define CAM_CC_MCLK1_CLK 63 76#define CAM_CC_MCLK1_CLK_SRC 64 77#define CAM_CC_MCLK2_CLK 65 78#define CAM_CC_MCLK2_CLK_SRC 66 79#define CAM_CC_MCLK3_CLK 67 80#define CAM_CC_MCLK3_CLK_SRC 68 81#define CAM_CC_MCLK4_CLK 69 82#define CAM_CC_MCLK4_CLK_SRC 70 83#define CAM_CC_BPS_AHB_CLK 71 84#define CAM_CC_BPS_AREG_CLK 72 85#define CAM_CC_BPS_AXI_CLK 73 86#define CAM_CC_BPS_CLK 74 87#define CAM_CC_BPS_CLK_SRC 75 88#define CAM_CC_SLOW_AHB_CLK_SRC 76 89#define CAM_CC_SOC_AHB_CLK 77 90#define CAM_CC_SYS_TMR_CLK 78 91 92/* CAM_CC power domains */ 93#define BPS_GDSC 0 94#define IFE_0_GDSC 1 95#define IFE_1_GDSC 2 96#define IPE_0_GDSC 3 97#define TITAN_TOP_GDSC 4 98 99/* CAM_CC resets */ 100#define CAM_CC_BPS_BCR 0 101#define CAM_CC_CAMNOC_BCR 1 102#define CAM_CC_CCI_0_BCR 2 103#define CAM_CC_CCI_1_BCR 3 104#define CAM_CC_CPAS_BCR 4 105#define CAM_CC_CSI0PHY_BCR 5 106#define CAM_CC_CSI1PHY_BCR 6 107#define CAM_CC_CSI2PHY_BCR 7 108#define CAM_CC_CSI3PHY_BCR 8 109#define CAM_CC_ICP_BCR 9 110#define CAM_CC_IFE_0_BCR 10 111#define CAM_CC_IFE_1_BCR 11 112#define CAM_CC_IFE_LITE_BCR 12 113#define CAM_CC_IPE_0_BCR 13 114#define CAM_CC_JPEG_BCR 14 115#define CAM_CC_LRME_BCR 15 116#define CAM_CC_MCLK0_BCR 16 117#define CAM_CC_MCLK1_BCR 17 118#define CAM_CC_MCLK2_BCR 18 119#define CAM_CC_MCLK3_BCR 19 120#define CAM_CC_MCLK4_BCR 20 121#define CAM_CC_TITAN_TOP_BCR 21 122 123#endif 124