11.1Sjmcneill/* $NetBSD: qcom,dispcc-sc7280.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (c) 2021, The Linux Foundation. All rights reserved. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H 91.1Sjmcneill#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H 101.1Sjmcneill 111.1Sjmcneill/* DISP_CC clocks */ 121.1Sjmcneill#define DISP_CC_PLL0 0 131.1Sjmcneill#define DISP_CC_MDSS_AHB_CLK 1 141.1Sjmcneill#define DISP_CC_MDSS_AHB_CLK_SRC 2 151.1Sjmcneill#define DISP_CC_MDSS_BYTE0_CLK 3 161.1Sjmcneill#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 171.1Sjmcneill#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 181.1Sjmcneill#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 191.1Sjmcneill#define DISP_CC_MDSS_DP_AUX_CLK 7 201.1Sjmcneill#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8 211.1Sjmcneill#define DISP_CC_MDSS_DP_CRYPTO_CLK 9 221.1Sjmcneill#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10 231.1Sjmcneill#define DISP_CC_MDSS_DP_LINK_CLK 11 241.1Sjmcneill#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12 251.1Sjmcneill#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13 261.1Sjmcneill#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14 271.1Sjmcneill#define DISP_CC_MDSS_DP_PIXEL_CLK 15 281.1Sjmcneill#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16 291.1Sjmcneill#define DISP_CC_MDSS_EDP_AUX_CLK 17 301.1Sjmcneill#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 18 311.1Sjmcneill#define DISP_CC_MDSS_EDP_LINK_CLK 19 321.1Sjmcneill#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 20 331.1Sjmcneill#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 21 341.1Sjmcneill#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 22 351.1Sjmcneill#define DISP_CC_MDSS_EDP_PIXEL_CLK 23 361.1Sjmcneill#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 24 371.1Sjmcneill#define DISP_CC_MDSS_ESC0_CLK 25 381.1Sjmcneill#define DISP_CC_MDSS_ESC0_CLK_SRC 26 391.1Sjmcneill#define DISP_CC_MDSS_MDP_CLK 27 401.1Sjmcneill#define DISP_CC_MDSS_MDP_CLK_SRC 28 411.1Sjmcneill#define DISP_CC_MDSS_MDP_LUT_CLK 29 421.1Sjmcneill#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30 431.1Sjmcneill#define DISP_CC_MDSS_PCLK0_CLK 31 441.1Sjmcneill#define DISP_CC_MDSS_PCLK0_CLK_SRC 32 451.1Sjmcneill#define DISP_CC_MDSS_ROT_CLK 33 461.1Sjmcneill#define DISP_CC_MDSS_ROT_CLK_SRC 34 471.1Sjmcneill#define DISP_CC_MDSS_RSCC_AHB_CLK 35 481.1Sjmcneill#define DISP_CC_MDSS_RSCC_VSYNC_CLK 36 491.1Sjmcneill#define DISP_CC_MDSS_VSYNC_CLK 37 501.1Sjmcneill#define DISP_CC_MDSS_VSYNC_CLK_SRC 38 511.1Sjmcneill#define DISP_CC_SLEEP_CLK 39 521.1Sjmcneill#define DISP_CC_XO_CLK 40 531.1Sjmcneill 541.1Sjmcneill/* DISP_CC power domains */ 551.1Sjmcneill#define DISP_CC_MDSS_CORE_GDSC 0 561.1Sjmcneill 571.1Sjmcneill#endif 58