11.1Sjmcneill/* $NetBSD: qcom,gcc-ipq8074.h,v 1.1.1.4 2021/11/07 16:49:59 jmcneill Exp $ */ 21.1Sjmcneill 31.1.1.3Sskrll/* SPDX-License-Identifier: GPL-2.0-only */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H 91.1Sjmcneill#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H 101.1Sjmcneill 111.1Sjmcneill#define GPLL0 0 121.1Sjmcneill#define GPLL0_MAIN 1 131.1Sjmcneill#define GCC_SLEEP_CLK_SRC 2 141.1Sjmcneill#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 151.1Sjmcneill#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 161.1Sjmcneill#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 171.1Sjmcneill#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 181.1Sjmcneill#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 191.1Sjmcneill#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 201.1Sjmcneill#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 211.1Sjmcneill#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 221.1Sjmcneill#define BLSP1_QUP5_I2C_APPS_CLK_SRC 11 231.1Sjmcneill#define BLSP1_QUP5_SPI_APPS_CLK_SRC 12 241.1Sjmcneill#define BLSP1_QUP6_I2C_APPS_CLK_SRC 13 251.1Sjmcneill#define BLSP1_QUP6_SPI_APPS_CLK_SRC 14 261.1Sjmcneill#define BLSP1_UART1_APPS_CLK_SRC 15 271.1Sjmcneill#define BLSP1_UART2_APPS_CLK_SRC 16 281.1Sjmcneill#define BLSP1_UART3_APPS_CLK_SRC 17 291.1Sjmcneill#define BLSP1_UART4_APPS_CLK_SRC 18 301.1Sjmcneill#define BLSP1_UART5_APPS_CLK_SRC 19 311.1Sjmcneill#define BLSP1_UART6_APPS_CLK_SRC 20 321.1Sjmcneill#define GCC_BLSP1_AHB_CLK 21 331.1Sjmcneill#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 341.1Sjmcneill#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 351.1Sjmcneill#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 361.1Sjmcneill#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 371.1Sjmcneill#define GCC_BLSP1_QUP3_I2C_APPS_CLK 26 381.1Sjmcneill#define GCC_BLSP1_QUP3_SPI_APPS_CLK 27 391.1Sjmcneill#define GCC_BLSP1_QUP4_I2C_APPS_CLK 28 401.1Sjmcneill#define GCC_BLSP1_QUP4_SPI_APPS_CLK 29 411.1Sjmcneill#define GCC_BLSP1_QUP5_I2C_APPS_CLK 30 421.1Sjmcneill#define GCC_BLSP1_QUP5_SPI_APPS_CLK 31 431.1Sjmcneill#define GCC_BLSP1_QUP6_I2C_APPS_CLK 32 441.1Sjmcneill#define GCC_BLSP1_QUP6_SPI_APPS_CLK 33 451.1Sjmcneill#define GCC_BLSP1_UART1_APPS_CLK 34 461.1Sjmcneill#define GCC_BLSP1_UART2_APPS_CLK 35 471.1Sjmcneill#define GCC_BLSP1_UART3_APPS_CLK 36 481.1Sjmcneill#define GCC_BLSP1_UART4_APPS_CLK 37 491.1Sjmcneill#define GCC_BLSP1_UART5_APPS_CLK 38 501.1Sjmcneill#define GCC_BLSP1_UART6_APPS_CLK 39 511.1Sjmcneill#define GCC_PRNG_AHB_CLK 40 521.1Sjmcneill#define GCC_QPIC_AHB_CLK 41 531.1Sjmcneill#define GCC_QPIC_CLK 42 541.1Sjmcneill#define PCNOC_BFDCD_CLK_SRC 43 551.1.1.2Sjmcneill#define GPLL2_MAIN 44 561.1.1.2Sjmcneill#define GPLL2 45 571.1.1.2Sjmcneill#define GPLL4_MAIN 46 581.1.1.2Sjmcneill#define GPLL4 47 591.1.1.2Sjmcneill#define GPLL6_MAIN 48 601.1.1.2Sjmcneill#define GPLL6 49 611.1.1.2Sjmcneill#define UBI32_PLL_MAIN 50 621.1.1.2Sjmcneill#define UBI32_PLL 51 631.1.1.2Sjmcneill#define NSS_CRYPTO_PLL_MAIN 52 641.1.1.2Sjmcneill#define NSS_CRYPTO_PLL 53 651.1.1.2Sjmcneill#define PCIE0_AXI_CLK_SRC 54 661.1.1.2Sjmcneill#define PCIE0_AUX_CLK_SRC 55 671.1.1.2Sjmcneill#define PCIE0_PIPE_CLK_SRC 56 681.1.1.2Sjmcneill#define PCIE1_AXI_CLK_SRC 57 691.1.1.2Sjmcneill#define PCIE1_AUX_CLK_SRC 58 701.1.1.2Sjmcneill#define PCIE1_PIPE_CLK_SRC 59 711.1.1.2Sjmcneill#define SDCC1_APPS_CLK_SRC 60 721.1.1.2Sjmcneill#define SDCC1_ICE_CORE_CLK_SRC 61 731.1.1.2Sjmcneill#define SDCC2_APPS_CLK_SRC 62 741.1.1.2Sjmcneill#define USB0_MASTER_CLK_SRC 63 751.1.1.2Sjmcneill#define USB0_AUX_CLK_SRC 64 761.1.1.2Sjmcneill#define USB0_MOCK_UTMI_CLK_SRC 65 771.1.1.2Sjmcneill#define USB0_PIPE_CLK_SRC 66 781.1.1.2Sjmcneill#define USB1_MASTER_CLK_SRC 67 791.1.1.2Sjmcneill#define USB1_AUX_CLK_SRC 68 801.1.1.2Sjmcneill#define USB1_MOCK_UTMI_CLK_SRC 69 811.1.1.2Sjmcneill#define USB1_PIPE_CLK_SRC 70 821.1.1.2Sjmcneill#define GCC_XO_CLK_SRC 71 831.1.1.2Sjmcneill#define SYSTEM_NOC_BFDCD_CLK_SRC 72 841.1.1.2Sjmcneill#define NSS_CE_CLK_SRC 73 851.1.1.2Sjmcneill#define NSS_NOC_BFDCD_CLK_SRC 74 861.1.1.2Sjmcneill#define NSS_CRYPTO_CLK_SRC 75 871.1.1.2Sjmcneill#define NSS_UBI0_CLK_SRC 76 881.1.1.2Sjmcneill#define NSS_UBI0_DIV_CLK_SRC 77 891.1.1.2Sjmcneill#define NSS_UBI1_CLK_SRC 78 901.1.1.2Sjmcneill#define NSS_UBI1_DIV_CLK_SRC 79 911.1.1.2Sjmcneill#define UBI_MPT_CLK_SRC 80 921.1.1.2Sjmcneill#define NSS_IMEM_CLK_SRC 81 931.1.1.2Sjmcneill#define NSS_PPE_CLK_SRC 82 941.1.1.2Sjmcneill#define NSS_PORT1_RX_CLK_SRC 83 951.1.1.2Sjmcneill#define NSS_PORT1_RX_DIV_CLK_SRC 84 961.1.1.2Sjmcneill#define NSS_PORT1_TX_CLK_SRC 85 971.1.1.2Sjmcneill#define NSS_PORT1_TX_DIV_CLK_SRC 86 981.1.1.2Sjmcneill#define NSS_PORT2_RX_CLK_SRC 87 991.1.1.2Sjmcneill#define NSS_PORT2_RX_DIV_CLK_SRC 88 1001.1.1.2Sjmcneill#define NSS_PORT2_TX_CLK_SRC 89 1011.1.1.2Sjmcneill#define NSS_PORT2_TX_DIV_CLK_SRC 90 1021.1.1.2Sjmcneill#define NSS_PORT3_RX_CLK_SRC 91 1031.1.1.2Sjmcneill#define NSS_PORT3_RX_DIV_CLK_SRC 92 1041.1.1.2Sjmcneill#define NSS_PORT3_TX_CLK_SRC 93 1051.1.1.2Sjmcneill#define NSS_PORT3_TX_DIV_CLK_SRC 94 1061.1.1.2Sjmcneill#define NSS_PORT4_RX_CLK_SRC 95 1071.1.1.2Sjmcneill#define NSS_PORT4_RX_DIV_CLK_SRC 96 1081.1.1.2Sjmcneill#define NSS_PORT4_TX_CLK_SRC 97 1091.1.1.2Sjmcneill#define NSS_PORT4_TX_DIV_CLK_SRC 98 1101.1.1.2Sjmcneill#define NSS_PORT5_RX_CLK_SRC 99 1111.1.1.2Sjmcneill#define NSS_PORT5_RX_DIV_CLK_SRC 100 1121.1.1.2Sjmcneill#define NSS_PORT5_TX_CLK_SRC 101 1131.1.1.2Sjmcneill#define NSS_PORT5_TX_DIV_CLK_SRC 102 1141.1.1.2Sjmcneill#define NSS_PORT6_RX_CLK_SRC 103 1151.1.1.2Sjmcneill#define NSS_PORT6_RX_DIV_CLK_SRC 104 1161.1.1.2Sjmcneill#define NSS_PORT6_TX_CLK_SRC 105 1171.1.1.2Sjmcneill#define NSS_PORT6_TX_DIV_CLK_SRC 106 1181.1.1.2Sjmcneill#define CRYPTO_CLK_SRC 107 1191.1.1.2Sjmcneill#define GP1_CLK_SRC 108 1201.1.1.2Sjmcneill#define GP2_CLK_SRC 109 1211.1.1.2Sjmcneill#define GP3_CLK_SRC 110 1221.1.1.2Sjmcneill#define GCC_PCIE0_AHB_CLK 111 1231.1.1.2Sjmcneill#define GCC_PCIE0_AUX_CLK 112 1241.1.1.2Sjmcneill#define GCC_PCIE0_AXI_M_CLK 113 1251.1.1.2Sjmcneill#define GCC_PCIE0_AXI_S_CLK 114 1261.1.1.2Sjmcneill#define GCC_PCIE0_PIPE_CLK 115 1271.1.1.2Sjmcneill#define GCC_SYS_NOC_PCIE0_AXI_CLK 116 1281.1.1.2Sjmcneill#define GCC_PCIE1_AHB_CLK 117 1291.1.1.2Sjmcneill#define GCC_PCIE1_AUX_CLK 118 1301.1.1.2Sjmcneill#define GCC_PCIE1_AXI_M_CLK 119 1311.1.1.2Sjmcneill#define GCC_PCIE1_AXI_S_CLK 120 1321.1.1.2Sjmcneill#define GCC_PCIE1_PIPE_CLK 121 1331.1.1.2Sjmcneill#define GCC_SYS_NOC_PCIE1_AXI_CLK 122 1341.1.1.2Sjmcneill#define GCC_USB0_AUX_CLK 123 1351.1.1.2Sjmcneill#define GCC_SYS_NOC_USB0_AXI_CLK 124 1361.1.1.2Sjmcneill#define GCC_USB0_MASTER_CLK 125 1371.1.1.2Sjmcneill#define GCC_USB0_MOCK_UTMI_CLK 126 1381.1.1.2Sjmcneill#define GCC_USB0_PHY_CFG_AHB_CLK 127 1391.1.1.2Sjmcneill#define GCC_USB0_PIPE_CLK 128 1401.1.1.2Sjmcneill#define GCC_USB0_SLEEP_CLK 129 1411.1.1.2Sjmcneill#define GCC_USB1_AUX_CLK 130 1421.1.1.2Sjmcneill#define GCC_SYS_NOC_USB1_AXI_CLK 131 1431.1.1.2Sjmcneill#define GCC_USB1_MASTER_CLK 132 1441.1.1.2Sjmcneill#define GCC_USB1_MOCK_UTMI_CLK 133 1451.1.1.2Sjmcneill#define GCC_USB1_PHY_CFG_AHB_CLK 134 1461.1.1.2Sjmcneill#define GCC_USB1_PIPE_CLK 135 1471.1.1.2Sjmcneill#define GCC_USB1_SLEEP_CLK 136 1481.1.1.2Sjmcneill#define GCC_SDCC1_AHB_CLK 137 1491.1.1.2Sjmcneill#define GCC_SDCC1_APPS_CLK 138 1501.1.1.2Sjmcneill#define GCC_SDCC1_ICE_CORE_CLK 139 1511.1.1.2Sjmcneill#define GCC_SDCC2_AHB_CLK 140 1521.1.1.2Sjmcneill#define GCC_SDCC2_APPS_CLK 141 1531.1.1.2Sjmcneill#define GCC_MEM_NOC_NSS_AXI_CLK 142 1541.1.1.2Sjmcneill#define GCC_NSS_CE_APB_CLK 143 1551.1.1.2Sjmcneill#define GCC_NSS_CE_AXI_CLK 144 1561.1.1.2Sjmcneill#define GCC_NSS_CFG_CLK 145 1571.1.1.2Sjmcneill#define GCC_NSS_CRYPTO_CLK 146 1581.1.1.2Sjmcneill#define GCC_NSS_CSR_CLK 147 1591.1.1.2Sjmcneill#define GCC_NSS_EDMA_CFG_CLK 148 1601.1.1.2Sjmcneill#define GCC_NSS_EDMA_CLK 149 1611.1.1.2Sjmcneill#define GCC_NSS_IMEM_CLK 150 1621.1.1.2Sjmcneill#define GCC_NSS_NOC_CLK 151 1631.1.1.2Sjmcneill#define GCC_NSS_PPE_BTQ_CLK 152 1641.1.1.2Sjmcneill#define GCC_NSS_PPE_CFG_CLK 153 1651.1.1.2Sjmcneill#define GCC_NSS_PPE_CLK 154 1661.1.1.2Sjmcneill#define GCC_NSS_PPE_IPE_CLK 155 1671.1.1.2Sjmcneill#define GCC_NSS_PTP_REF_CLK 156 1681.1.1.2Sjmcneill#define GCC_NSSNOC_CE_APB_CLK 157 1691.1.1.2Sjmcneill#define GCC_NSSNOC_CE_AXI_CLK 158 1701.1.1.2Sjmcneill#define GCC_NSSNOC_CRYPTO_CLK 159 1711.1.1.2Sjmcneill#define GCC_NSSNOC_PPE_CFG_CLK 160 1721.1.1.2Sjmcneill#define GCC_NSSNOC_PPE_CLK 161 1731.1.1.2Sjmcneill#define GCC_NSSNOC_QOSGEN_REF_CLK 162 1741.1.1.2Sjmcneill#define GCC_NSSNOC_SNOC_CLK 163 1751.1.1.2Sjmcneill#define GCC_NSSNOC_TIMEOUT_REF_CLK 164 1761.1.1.2Sjmcneill#define GCC_NSSNOC_UBI0_AHB_CLK 165 1771.1.1.2Sjmcneill#define GCC_NSSNOC_UBI1_AHB_CLK 166 1781.1.1.2Sjmcneill#define GCC_UBI0_AHB_CLK 167 1791.1.1.2Sjmcneill#define GCC_UBI0_AXI_CLK 168 1801.1.1.2Sjmcneill#define GCC_UBI0_NC_AXI_CLK 169 1811.1.1.2Sjmcneill#define GCC_UBI0_CORE_CLK 170 1821.1.1.2Sjmcneill#define GCC_UBI0_MPT_CLK 171 1831.1.1.2Sjmcneill#define GCC_UBI1_AHB_CLK 172 1841.1.1.2Sjmcneill#define GCC_UBI1_AXI_CLK 173 1851.1.1.2Sjmcneill#define GCC_UBI1_NC_AXI_CLK 174 1861.1.1.2Sjmcneill#define GCC_UBI1_CORE_CLK 175 1871.1.1.2Sjmcneill#define GCC_UBI1_MPT_CLK 176 1881.1.1.2Sjmcneill#define GCC_CMN_12GPLL_AHB_CLK 177 1891.1.1.2Sjmcneill#define GCC_CMN_12GPLL_SYS_CLK 178 1901.1.1.2Sjmcneill#define GCC_MDIO_AHB_CLK 179 1911.1.1.2Sjmcneill#define GCC_UNIPHY0_AHB_CLK 180 1921.1.1.2Sjmcneill#define GCC_UNIPHY0_SYS_CLK 181 1931.1.1.2Sjmcneill#define GCC_UNIPHY1_AHB_CLK 182 1941.1.1.2Sjmcneill#define GCC_UNIPHY1_SYS_CLK 183 1951.1.1.2Sjmcneill#define GCC_UNIPHY2_AHB_CLK 184 1961.1.1.2Sjmcneill#define GCC_UNIPHY2_SYS_CLK 185 1971.1.1.2Sjmcneill#define GCC_NSS_PORT1_RX_CLK 186 1981.1.1.2Sjmcneill#define GCC_NSS_PORT1_TX_CLK 187 1991.1.1.2Sjmcneill#define GCC_NSS_PORT2_RX_CLK 188 2001.1.1.2Sjmcneill#define GCC_NSS_PORT2_TX_CLK 189 2011.1.1.2Sjmcneill#define GCC_NSS_PORT3_RX_CLK 190 2021.1.1.2Sjmcneill#define GCC_NSS_PORT3_TX_CLK 191 2031.1.1.2Sjmcneill#define GCC_NSS_PORT4_RX_CLK 192 2041.1.1.2Sjmcneill#define GCC_NSS_PORT4_TX_CLK 193 2051.1.1.2Sjmcneill#define GCC_NSS_PORT5_RX_CLK 194 2061.1.1.2Sjmcneill#define GCC_NSS_PORT5_TX_CLK 195 2071.1.1.2Sjmcneill#define GCC_NSS_PORT6_RX_CLK 196 2081.1.1.2Sjmcneill#define GCC_NSS_PORT6_TX_CLK 197 2091.1.1.2Sjmcneill#define GCC_PORT1_MAC_CLK 198 2101.1.1.2Sjmcneill#define GCC_PORT2_MAC_CLK 199 2111.1.1.2Sjmcneill#define GCC_PORT3_MAC_CLK 200 2121.1.1.2Sjmcneill#define GCC_PORT4_MAC_CLK 201 2131.1.1.2Sjmcneill#define GCC_PORT5_MAC_CLK 202 2141.1.1.2Sjmcneill#define GCC_PORT6_MAC_CLK 203 2151.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT1_RX_CLK 204 2161.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT1_TX_CLK 205 2171.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT2_RX_CLK 206 2181.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT2_TX_CLK 207 2191.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT3_RX_CLK 208 2201.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT3_TX_CLK 209 2211.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT4_RX_CLK 210 2221.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT4_TX_CLK 211 2231.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT5_RX_CLK 212 2241.1.1.2Sjmcneill#define GCC_UNIPHY0_PORT5_TX_CLK 213 2251.1.1.2Sjmcneill#define GCC_UNIPHY1_PORT5_RX_CLK 214 2261.1.1.2Sjmcneill#define GCC_UNIPHY1_PORT5_TX_CLK 215 2271.1.1.2Sjmcneill#define GCC_UNIPHY2_PORT6_RX_CLK 216 2281.1.1.2Sjmcneill#define GCC_UNIPHY2_PORT6_TX_CLK 217 2291.1.1.2Sjmcneill#define GCC_CRYPTO_AHB_CLK 218 2301.1.1.2Sjmcneill#define GCC_CRYPTO_AXI_CLK 219 2311.1.1.2Sjmcneill#define GCC_CRYPTO_CLK 220 2321.1.1.2Sjmcneill#define GCC_GP1_CLK 221 2331.1.1.2Sjmcneill#define GCC_GP2_CLK 222 2341.1.1.2Sjmcneill#define GCC_GP3_CLK 223 2351.1.1.4Sjmcneill#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 2361.1.1.4Sjmcneill#define GCC_PCIE0_RCHNG_CLK_SRC 225 2371.1.1.4Sjmcneill#define GCC_PCIE0_RCHNG_CLK 226 2381.1Sjmcneill 2391.1Sjmcneill#define GCC_BLSP1_BCR 0 2401.1Sjmcneill#define GCC_BLSP1_QUP1_BCR 1 2411.1Sjmcneill#define GCC_BLSP1_UART1_BCR 2 2421.1Sjmcneill#define GCC_BLSP1_QUP2_BCR 3 2431.1Sjmcneill#define GCC_BLSP1_UART2_BCR 4 2441.1Sjmcneill#define GCC_BLSP1_QUP3_BCR 5 2451.1Sjmcneill#define GCC_BLSP1_UART3_BCR 6 2461.1Sjmcneill#define GCC_BLSP1_QUP4_BCR 7 2471.1Sjmcneill#define GCC_BLSP1_UART4_BCR 8 2481.1Sjmcneill#define GCC_BLSP1_QUP5_BCR 9 2491.1Sjmcneill#define GCC_BLSP1_UART5_BCR 10 2501.1Sjmcneill#define GCC_BLSP1_QUP6_BCR 11 2511.1Sjmcneill#define GCC_BLSP1_UART6_BCR 12 2521.1Sjmcneill#define GCC_IMEM_BCR 13 2531.1Sjmcneill#define GCC_SMMU_BCR 14 2541.1Sjmcneill#define GCC_APSS_TCU_BCR 15 2551.1Sjmcneill#define GCC_SMMU_XPU_BCR 16 2561.1Sjmcneill#define GCC_PCNOC_TBU_BCR 17 2571.1Sjmcneill#define GCC_SMMU_CFG_BCR 18 2581.1Sjmcneill#define GCC_PRNG_BCR 19 2591.1Sjmcneill#define GCC_BOOT_ROM_BCR 20 2601.1Sjmcneill#define GCC_CRYPTO_BCR 21 2611.1Sjmcneill#define GCC_WCSS_BCR 22 2621.1Sjmcneill#define GCC_WCSS_Q6_BCR 23 2631.1Sjmcneill#define GCC_NSS_BCR 24 2641.1Sjmcneill#define GCC_SEC_CTRL_BCR 25 2651.1Sjmcneill#define GCC_ADSS_BCR 26 2661.1Sjmcneill#define GCC_DDRSS_BCR 27 2671.1Sjmcneill#define GCC_SYSTEM_NOC_BCR 28 2681.1Sjmcneill#define GCC_PCNOC_BCR 29 2691.1Sjmcneill#define GCC_TCSR_BCR 30 2701.1Sjmcneill#define GCC_QDSS_BCR 31 2711.1Sjmcneill#define GCC_DCD_BCR 32 2721.1Sjmcneill#define GCC_MSG_RAM_BCR 33 2731.1Sjmcneill#define GCC_MPM_BCR 34 2741.1Sjmcneill#define GCC_SPMI_BCR 35 2751.1Sjmcneill#define GCC_SPDM_BCR 36 2761.1Sjmcneill#define GCC_RBCPR_BCR 37 2771.1Sjmcneill#define GCC_RBCPR_MX_BCR 38 2781.1Sjmcneill#define GCC_TLMM_BCR 39 2791.1Sjmcneill#define GCC_RBCPR_WCSS_BCR 40 2801.1Sjmcneill#define GCC_USB0_PHY_BCR 41 2811.1Sjmcneill#define GCC_USB3PHY_0_PHY_BCR 42 2821.1Sjmcneill#define GCC_USB0_BCR 43 2831.1Sjmcneill#define GCC_USB1_PHY_BCR 44 2841.1Sjmcneill#define GCC_USB3PHY_1_PHY_BCR 45 2851.1Sjmcneill#define GCC_USB1_BCR 46 2861.1Sjmcneill#define GCC_QUSB2_0_PHY_BCR 47 2871.1Sjmcneill#define GCC_QUSB2_1_PHY_BCR 48 2881.1Sjmcneill#define GCC_SDCC1_BCR 49 2891.1Sjmcneill#define GCC_SDCC2_BCR 50 2901.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 2911.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT2_BCR 52 2921.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 2931.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 2941.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 2951.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 2961.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 2971.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 2981.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 2991.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 3001.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 3011.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 3021.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 3031.1Sjmcneill#define GCC_UNIPHY0_BCR 64 3041.1Sjmcneill#define GCC_UNIPHY1_BCR 65 3051.1Sjmcneill#define GCC_UNIPHY2_BCR 66 3061.1Sjmcneill#define GCC_CMN_12GPLL_BCR 67 3071.1Sjmcneill#define GCC_QPIC_BCR 68 3081.1Sjmcneill#define GCC_MDIO_BCR 69 3091.1Sjmcneill#define GCC_PCIE1_TBU_BCR 70 3101.1Sjmcneill#define GCC_WCSS_CORE_TBU_BCR 71 3111.1Sjmcneill#define GCC_WCSS_Q6_TBU_BCR 72 3121.1Sjmcneill#define GCC_USB0_TBU_BCR 73 3131.1Sjmcneill#define GCC_USB1_TBU_BCR 74 3141.1Sjmcneill#define GCC_PCIE0_TBU_BCR 75 3151.1Sjmcneill#define GCC_NSS_NOC_TBU_BCR 76 3161.1Sjmcneill#define GCC_PCIE0_BCR 77 3171.1Sjmcneill#define GCC_PCIE0_PHY_BCR 78 3181.1Sjmcneill#define GCC_PCIE0PHY_PHY_BCR 79 3191.1Sjmcneill#define GCC_PCIE0_LINK_DOWN_BCR 80 3201.1Sjmcneill#define GCC_PCIE1_BCR 81 3211.1Sjmcneill#define GCC_PCIE1_PHY_BCR 82 3221.1Sjmcneill#define GCC_PCIE1PHY_PHY_BCR 83 3231.1Sjmcneill#define GCC_PCIE1_LINK_DOWN_BCR 84 3241.1Sjmcneill#define GCC_DCC_BCR 85 3251.1Sjmcneill#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86 3261.1Sjmcneill#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87 3271.1Sjmcneill#define GCC_SMMU_CATS_BCR 88 3281.1.1.2Sjmcneill#define GCC_UBI0_AXI_ARES 89 3291.1.1.2Sjmcneill#define GCC_UBI0_AHB_ARES 90 3301.1.1.2Sjmcneill#define GCC_UBI0_NC_AXI_ARES 91 3311.1.1.2Sjmcneill#define GCC_UBI0_DBG_ARES 92 3321.1.1.2Sjmcneill#define GCC_UBI0_CORE_CLAMP_ENABLE 93 3331.1.1.2Sjmcneill#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94 3341.1.1.2Sjmcneill#define GCC_UBI1_AXI_ARES 95 3351.1.1.2Sjmcneill#define GCC_UBI1_AHB_ARES 96 3361.1.1.2Sjmcneill#define GCC_UBI1_NC_AXI_ARES 97 3371.1.1.2Sjmcneill#define GCC_UBI1_DBG_ARES 98 3381.1.1.2Sjmcneill#define GCC_UBI1_CORE_CLAMP_ENABLE 99 3391.1.1.2Sjmcneill#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100 3401.1.1.2Sjmcneill#define GCC_NSS_CFG_ARES 101 3411.1.1.2Sjmcneill#define GCC_NSS_IMEM_ARES 102 3421.1.1.2Sjmcneill#define GCC_NSS_NOC_ARES 103 3431.1.1.2Sjmcneill#define GCC_NSS_CRYPTO_ARES 104 3441.1.1.2Sjmcneill#define GCC_NSS_CSR_ARES 105 3451.1.1.2Sjmcneill#define GCC_NSS_CE_APB_ARES 106 3461.1.1.2Sjmcneill#define GCC_NSS_CE_AXI_ARES 107 3471.1.1.2Sjmcneill#define GCC_NSSNOC_CE_APB_ARES 108 3481.1.1.2Sjmcneill#define GCC_NSSNOC_CE_AXI_ARES 109 3491.1.1.2Sjmcneill#define GCC_NSSNOC_UBI0_AHB_ARES 110 3501.1.1.2Sjmcneill#define GCC_NSSNOC_UBI1_AHB_ARES 111 3511.1.1.2Sjmcneill#define GCC_NSSNOC_SNOC_ARES 112 3521.1.1.2Sjmcneill#define GCC_NSSNOC_CRYPTO_ARES 113 3531.1.1.2Sjmcneill#define GCC_NSSNOC_ATB_ARES 114 3541.1.1.2Sjmcneill#define GCC_NSSNOC_QOSGEN_REF_ARES 115 3551.1.1.2Sjmcneill#define GCC_NSSNOC_TIMEOUT_REF_ARES 116 3561.1.1.2Sjmcneill#define GCC_PCIE0_PIPE_ARES 117 3571.1.1.2Sjmcneill#define GCC_PCIE0_SLEEP_ARES 118 3581.1.1.2Sjmcneill#define GCC_PCIE0_CORE_STICKY_ARES 119 3591.1.1.2Sjmcneill#define GCC_PCIE0_AXI_MASTER_ARES 120 3601.1.1.2Sjmcneill#define GCC_PCIE0_AXI_SLAVE_ARES 121 3611.1.1.2Sjmcneill#define GCC_PCIE0_AHB_ARES 122 3621.1.1.2Sjmcneill#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123 3631.1.1.2Sjmcneill#define GCC_PCIE1_PIPE_ARES 124 3641.1.1.2Sjmcneill#define GCC_PCIE1_SLEEP_ARES 125 3651.1.1.2Sjmcneill#define GCC_PCIE1_CORE_STICKY_ARES 126 3661.1.1.2Sjmcneill#define GCC_PCIE1_AXI_MASTER_ARES 127 3671.1.1.2Sjmcneill#define GCC_PCIE1_AXI_SLAVE_ARES 128 3681.1.1.2Sjmcneill#define GCC_PCIE1_AHB_ARES 129 3691.1.1.2Sjmcneill#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 3701.1.1.4Sjmcneill#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 3711.1Sjmcneill 3721.1Sjmcneill#endif 373