qcom,gcc-msm8974.h revision 1.1.1.1
1/* $NetBSD: qcom,gcc-msm8974.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3/* 4 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H 17#define _DT_BINDINGS_CLK_MSM_GCC_8974_H 18 19#define GPLL0 0 20#define GPLL0_VOTE 1 21#define CONFIG_NOC_CLK_SRC 2 22#define GPLL2 3 23#define GPLL2_VOTE 4 24#define GPLL3 5 25#define GPLL3_VOTE 6 26#define PERIPH_NOC_CLK_SRC 7 27#define BLSP_UART_SIM_CLK_SRC 8 28#define QDSS_TSCTR_CLK_SRC 9 29#define BIMC_DDR_CLK_SRC 10 30#define SYSTEM_NOC_CLK_SRC 11 31#define GPLL1 12 32#define GPLL1_VOTE 13 33#define RPM_CLK_SRC 14 34#define GCC_BIMC_CLK 15 35#define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 36#define KPSS_AHB_CLK_SRC 17 37#define QDSS_AT_CLK_SRC 18 38#define USB30_MASTER_CLK_SRC 19 39#define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 40#define QDSS_STM_CLK_SRC 21 41#define ACC_CLK_SRC 22 42#define SEC_CTRL_CLK_SRC 23 43#define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 44#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 45#define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 46#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 47#define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 48#define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 49#define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 50#define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 51#define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 52#define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 53#define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 54#define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 55#define BLSP1_UART1_APPS_CLK_SRC 36 56#define BLSP1_UART2_APPS_CLK_SRC 37 57#define BLSP1_UART3_APPS_CLK_SRC 38 58#define BLSP1_UART4_APPS_CLK_SRC 39 59#define BLSP1_UART5_APPS_CLK_SRC 40 60#define BLSP1_UART6_APPS_CLK_SRC 41 61#define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 62#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 63#define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 64#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 65#define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 66#define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 67#define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 68#define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 69#define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 70#define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 71#define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 72#define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 73#define BLSP2_UART1_APPS_CLK_SRC 54 74#define BLSP2_UART2_APPS_CLK_SRC 55 75#define BLSP2_UART3_APPS_CLK_SRC 56 76#define BLSP2_UART4_APPS_CLK_SRC 57 77#define BLSP2_UART5_APPS_CLK_SRC 58 78#define BLSP2_UART6_APPS_CLK_SRC 59 79#define CE1_CLK_SRC 60 80#define CE2_CLK_SRC 61 81#define GP1_CLK_SRC 62 82#define GP2_CLK_SRC 63 83#define GP3_CLK_SRC 64 84#define PDM2_CLK_SRC 65 85#define QDSS_TRACECLKIN_CLK_SRC 66 86#define RBCPR_CLK_SRC 67 87#define SDCC1_APPS_CLK_SRC 68 88#define SDCC2_APPS_CLK_SRC 69 89#define SDCC3_APPS_CLK_SRC 70 90#define SDCC4_APPS_CLK_SRC 71 91#define SPMI_AHB_CLK_SRC 72 92#define SPMI_SER_CLK_SRC 73 93#define TSIF_REF_CLK_SRC 74 94#define USB30_MOCK_UTMI_CLK_SRC 75 95#define USB_HS_SYSTEM_CLK_SRC 76 96#define USB_HSIC_CLK_SRC 77 97#define USB_HSIC_IO_CAL_CLK_SRC 78 98#define USB_HSIC_SYSTEM_CLK_SRC 79 99#define GCC_BAM_DMA_AHB_CLK 80 100#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 101#define GCC_BIMC_CFG_AHB_CLK 82 102#define GCC_BIMC_KPSS_AXI_CLK 83 103#define GCC_BIMC_SLEEP_CLK 84 104#define GCC_BIMC_SYSNOC_AXI_CLK 85 105#define GCC_BIMC_XO_CLK 86 106#define GCC_BLSP1_AHB_CLK 87 107#define GCC_BLSP1_SLEEP_CLK 88 108#define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 109#define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 110#define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 111#define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 112#define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 113#define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 114#define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 115#define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 116#define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 117#define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 118#define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 119#define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 120#define GCC_BLSP1_UART1_APPS_CLK 101 121#define GCC_BLSP1_UART1_SIM_CLK 102 122#define GCC_BLSP1_UART2_APPS_CLK 103 123#define GCC_BLSP1_UART2_SIM_CLK 104 124#define GCC_BLSP1_UART3_APPS_CLK 105 125#define GCC_BLSP1_UART3_SIM_CLK 106 126#define GCC_BLSP1_UART4_APPS_CLK 107 127#define GCC_BLSP1_UART4_SIM_CLK 108 128#define GCC_BLSP1_UART5_APPS_CLK 109 129#define GCC_BLSP1_UART5_SIM_CLK 110 130#define GCC_BLSP1_UART6_APPS_CLK 111 131#define GCC_BLSP1_UART6_SIM_CLK 112 132#define GCC_BLSP2_AHB_CLK 113 133#define GCC_BLSP2_SLEEP_CLK 114 134#define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 135#define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 136#define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 137#define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 138#define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 139#define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 140#define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 141#define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 142#define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 143#define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 144#define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 145#define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 146#define GCC_BLSP2_UART1_APPS_CLK 127 147#define GCC_BLSP2_UART1_SIM_CLK 128 148#define GCC_BLSP2_UART2_APPS_CLK 129 149#define GCC_BLSP2_UART2_SIM_CLK 130 150#define GCC_BLSP2_UART3_APPS_CLK 131 151#define GCC_BLSP2_UART3_SIM_CLK 132 152#define GCC_BLSP2_UART4_APPS_CLK 133 153#define GCC_BLSP2_UART4_SIM_CLK 134 154#define GCC_BLSP2_UART5_APPS_CLK 135 155#define GCC_BLSP2_UART5_SIM_CLK 136 156#define GCC_BLSP2_UART6_APPS_CLK 137 157#define GCC_BLSP2_UART6_SIM_CLK 138 158#define GCC_BOOT_ROM_AHB_CLK 139 159#define GCC_CE1_AHB_CLK 140 160#define GCC_CE1_AXI_CLK 141 161#define GCC_CE1_CLK 142 162#define GCC_CE2_AHB_CLK 143 163#define GCC_CE2_AXI_CLK 144 164#define GCC_CE2_CLK 145 165#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 166#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 167#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 168#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 169#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 170#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 171#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 172#define GCC_CFG_NOC_AHB_CLK 153 173#define GCC_CFG_NOC_DDR_CFG_CLK 154 174#define GCC_CFG_NOC_RPM_AHB_CLK 155 175#define GCC_BIMC_DDR_CPLL0_CLK 156 176#define GCC_BIMC_DDR_CPLL1_CLK 157 177#define GCC_DDR_DIM_CFG_CLK 158 178#define GCC_DDR_DIM_SLEEP_CLK 159 179#define GCC_DEHR_CLK 160 180#define GCC_AHB_CLK 161 181#define GCC_IM_SLEEP_CLK 162 182#define GCC_XO_CLK 163 183#define GCC_XO_DIV4_CLK 164 184#define GCC_GP1_CLK 165 185#define GCC_GP2_CLK 166 186#define GCC_GP3_CLK 167 187#define GCC_IMEM_AXI_CLK 168 188#define GCC_IMEM_CFG_AHB_CLK 169 189#define GCC_KPSS_AHB_CLK 170 190#define GCC_KPSS_AXI_CLK 171 191#define GCC_LPASS_Q6_AXI_CLK 172 192#define GCC_MMSS_NOC_AT_CLK 173 193#define GCC_MMSS_NOC_CFG_AHB_CLK 174 194#define GCC_OCMEM_NOC_CFG_AHB_CLK 175 195#define GCC_OCMEM_SYS_NOC_AXI_CLK 176 196#define GCC_MPM_AHB_CLK 177 197#define GCC_MSG_RAM_AHB_CLK 178 198#define GCC_MSS_CFG_AHB_CLK 179 199#define GCC_MSS_Q6_BIMC_AXI_CLK 180 200#define GCC_NOC_CONF_XPU_AHB_CLK 181 201#define GCC_PDM2_CLK 182 202#define GCC_PDM_AHB_CLK 183 203#define GCC_PDM_XO4_CLK 184 204#define GCC_PERIPH_NOC_AHB_CLK 185 205#define GCC_PERIPH_NOC_AT_CLK 186 206#define GCC_PERIPH_NOC_CFG_AHB_CLK 187 207#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 208#define GCC_PERIPH_XPU_AHB_CLK 189 209#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 210#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 211#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 212#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 213#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 214#define GCC_PRNG_AHB_CLK 195 215#define GCC_QDSS_AT_CLK 196 216#define GCC_QDSS_CFG_AHB_CLK 197 217#define GCC_QDSS_DAP_AHB_CLK 198 218#define GCC_QDSS_DAP_CLK 199 219#define GCC_QDSS_ETR_USB_CLK 200 220#define GCC_QDSS_STM_CLK 201 221#define GCC_QDSS_TRACECLKIN_CLK 202 222#define GCC_QDSS_TSCTR_DIV16_CLK 203 223#define GCC_QDSS_TSCTR_DIV2_CLK 204 224#define GCC_QDSS_TSCTR_DIV3_CLK 205 225#define GCC_QDSS_TSCTR_DIV4_CLK 206 226#define GCC_QDSS_TSCTR_DIV8_CLK 207 227#define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 228#define GCC_RBCPR_AHB_CLK 209 229#define GCC_RBCPR_CLK 210 230#define GCC_RPM_BUS_AHB_CLK 211 231#define GCC_RPM_PROC_HCLK 212 232#define GCC_RPM_SLEEP_CLK 213 233#define GCC_RPM_TIMER_CLK 214 234#define GCC_SDCC1_AHB_CLK 215 235#define GCC_SDCC1_APPS_CLK 216 236#define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 237#define GCC_SDCC2_AHB_CLK 218 238#define GCC_SDCC2_APPS_CLK 219 239#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 240#define GCC_SDCC3_AHB_CLK 221 241#define GCC_SDCC3_APPS_CLK 222 242#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 243#define GCC_SDCC4_AHB_CLK 224 244#define GCC_SDCC4_APPS_CLK 225 245#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 246#define GCC_SEC_CTRL_ACC_CLK 227 247#define GCC_SEC_CTRL_AHB_CLK 228 248#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 249#define GCC_SEC_CTRL_CLK 230 250#define GCC_SEC_CTRL_SENSE_CLK 231 251#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 252#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 253#define GCC_SPDM_BIMC_CY_CLK 234 254#define GCC_SPDM_CFG_AHB_CLK 235 255#define GCC_SPDM_DEBUG_CY_CLK 236 256#define GCC_SPDM_FF_CLK 237 257#define GCC_SPDM_MSTR_AHB_CLK 238 258#define GCC_SPDM_PNOC_CY_CLK 239 259#define GCC_SPDM_RPM_CY_CLK 240 260#define GCC_SPDM_SNOC_CY_CLK 241 261#define GCC_SPMI_AHB_CLK 242 262#define GCC_SPMI_CNOC_AHB_CLK 243 263#define GCC_SPMI_SER_CLK 244 264#define GCC_SNOC_CNOC_AHB_CLK 245 265#define GCC_SNOC_PNOC_AHB_CLK 246 266#define GCC_SYS_NOC_AT_CLK 247 267#define GCC_SYS_NOC_AXI_CLK 248 268#define GCC_SYS_NOC_KPSS_AHB_CLK 249 269#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 270#define GCC_SYS_NOC_USB3_AXI_CLK 251 271#define GCC_TCSR_AHB_CLK 252 272#define GCC_TLMM_AHB_CLK 253 273#define GCC_TLMM_CLK 254 274#define GCC_TSIF_AHB_CLK 255 275#define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 276#define GCC_TSIF_REF_CLK 257 277#define GCC_USB2A_PHY_SLEEP_CLK 258 278#define GCC_USB2B_PHY_SLEEP_CLK 259 279#define GCC_USB30_MASTER_CLK 260 280#define GCC_USB30_MOCK_UTMI_CLK 261 281#define GCC_USB30_SLEEP_CLK 262 282#define GCC_USB_HS_AHB_CLK 263 283#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 284#define GCC_USB_HS_SYSTEM_CLK 265 285#define GCC_USB_HSIC_AHB_CLK 266 286#define GCC_USB_HSIC_CLK 267 287#define GCC_USB_HSIC_IO_CAL_CLK 268 288#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 289#define GCC_USB_HSIC_SYSTEM_CLK 270 290#define GCC_WCSS_GPLL1_CLK_SRC 271 291#define GCC_MMSS_GPLL0_CLK_SRC 272 292#define GCC_LPASS_GPLL0_CLK_SRC 273 293#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 294#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 295#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 296#define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 297#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 298#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 299#define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 300#define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 301#define GCC_MPM_AHB_CLK_SLEEP_ENA 282 302#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 303#define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 304#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 305#define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 306#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 307#define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 308#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 309#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 310#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 311#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 312#define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 313#define GCC_TLMM_CLK_SLEEP_ENA 294 314#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 315#define GCC_CE1_CLK_SLEEP_ENA 296 316#define GCC_CE1_AXI_CLK_SLEEP_ENA 297 317#define GCC_CE1_AHB_CLK_SLEEP_ENA 298 318#define GCC_CE2_CLK_SLEEP_ENA 299 319#define GCC_CE2_AXI_CLK_SLEEP_ENA 300 320#define GCC_CE2_AHB_CLK_SLEEP_ENA 301 321#define GPLL4 302 322#define GPLL4_VOTE 303 323#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 324#define GCC_SDCC1_CDCCAL_FF_CLK 305 325 326/* gdscs */ 327#define USB_HS_HSIC_GDSC 0 328 329#endif 330