11.1Sjmcneill/*	$NetBSD: qcom,gcc-msm8994.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $	*/
21.1Sjmcneill
31.1.1.2Sskrll/* SPDX-License-Identifier: GPL-2.0-only */
41.1Sjmcneill/*
51.1Sjmcneill * Copyright (c) 2016, The Linux Foundation. All rights reserved.
61.1Sjmcneill */
71.1Sjmcneill
81.1Sjmcneill
91.1Sjmcneill#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
101.1Sjmcneill#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
111.1Sjmcneill
121.1Sjmcneill#define GPLL0_EARLY				0
131.1Sjmcneill#define GPLL0					1
141.1Sjmcneill#define GPLL4_EARLY				2
151.1Sjmcneill#define GPLL4					3
161.1Sjmcneill#define UFS_AXI_CLK_SRC				4
171.1Sjmcneill#define USB30_MASTER_CLK_SRC			5
181.1Sjmcneill#define BLSP1_QUP1_I2C_APPS_CLK_SRC		6
191.1Sjmcneill#define BLSP1_QUP1_SPI_APPS_CLK_SRC		7
201.1Sjmcneill#define BLSP1_QUP2_I2C_APPS_CLK_SRC		8
211.1Sjmcneill#define BLSP1_QUP2_SPI_APPS_CLK_SRC		9
221.1Sjmcneill#define BLSP1_QUP3_I2C_APPS_CLK_SRC		10
231.1Sjmcneill#define BLSP1_QUP3_SPI_APPS_CLK_SRC		11
241.1Sjmcneill#define BLSP1_QUP4_I2C_APPS_CLK_SRC		12
251.1Sjmcneill#define BLSP1_QUP4_SPI_APPS_CLK_SRC		13
261.1Sjmcneill#define BLSP1_QUP5_I2C_APPS_CLK_SRC		14
271.1Sjmcneill#define BLSP1_QUP5_SPI_APPS_CLK_SRC		15
281.1Sjmcneill#define BLSP1_QUP6_I2C_APPS_CLK_SRC		16
291.1Sjmcneill#define BLSP1_QUP6_SPI_APPS_CLK_SRC		17
301.1Sjmcneill#define BLSP1_UART1_APPS_CLK_SRC		18
311.1Sjmcneill#define BLSP1_UART2_APPS_CLK_SRC		19
321.1Sjmcneill#define BLSP1_UART3_APPS_CLK_SRC		20
331.1Sjmcneill#define BLSP1_UART4_APPS_CLK_SRC		21
341.1Sjmcneill#define BLSP1_UART5_APPS_CLK_SRC		22
351.1Sjmcneill#define BLSP1_UART6_APPS_CLK_SRC		23
361.1Sjmcneill#define BLSP2_QUP1_I2C_APPS_CLK_SRC		24
371.1Sjmcneill#define BLSP2_QUP1_SPI_APPS_CLK_SRC		25
381.1Sjmcneill#define BLSP2_QUP2_I2C_APPS_CLK_SRC		26
391.1Sjmcneill#define BLSP2_QUP2_SPI_APPS_CLK_SRC		27
401.1Sjmcneill#define BLSP2_QUP3_I2C_APPS_CLK_SRC		28
411.1Sjmcneill#define BLSP2_QUP3_SPI_APPS_CLK_SRC		29
421.1Sjmcneill#define BLSP2_QUP4_I2C_APPS_CLK_SRC		30
431.1Sjmcneill#define BLSP2_QUP4_SPI_APPS_CLK_SRC		31
441.1Sjmcneill#define BLSP2_QUP5_I2C_APPS_CLK_SRC		32
451.1Sjmcneill#define BLSP2_QUP5_SPI_APPS_CLK_SRC		33
461.1Sjmcneill#define BLSP2_QUP6_I2C_APPS_CLK_SRC		34
471.1Sjmcneill#define BLSP2_QUP6_SPI_APPS_CLK_SRC		35
481.1Sjmcneill#define BLSP2_UART1_APPS_CLK_SRC		36
491.1Sjmcneill#define BLSP2_UART2_APPS_CLK_SRC		37
501.1Sjmcneill#define BLSP2_UART3_APPS_CLK_SRC		38
511.1Sjmcneill#define BLSP2_UART4_APPS_CLK_SRC		39
521.1Sjmcneill#define BLSP2_UART5_APPS_CLK_SRC		40
531.1Sjmcneill#define BLSP2_UART6_APPS_CLK_SRC		41
541.1Sjmcneill#define GP1_CLK_SRC				42
551.1Sjmcneill#define GP2_CLK_SRC				43
561.1Sjmcneill#define GP3_CLK_SRC				44
571.1Sjmcneill#define PCIE_0_AUX_CLK_SRC			45
581.1Sjmcneill#define PCIE_0_PIPE_CLK_SRC			46
591.1Sjmcneill#define PCIE_1_AUX_CLK_SRC			47
601.1Sjmcneill#define PCIE_1_PIPE_CLK_SRC			48
611.1Sjmcneill#define PDM2_CLK_SRC				49
621.1Sjmcneill#define SDCC1_APPS_CLK_SRC			50
631.1Sjmcneill#define SDCC2_APPS_CLK_SRC			51
641.1Sjmcneill#define SDCC3_APPS_CLK_SRC			52
651.1Sjmcneill#define SDCC4_APPS_CLK_SRC			53
661.1Sjmcneill#define TSIF_REF_CLK_SRC			54
671.1Sjmcneill#define USB30_MOCK_UTMI_CLK_SRC			55
681.1Sjmcneill#define USB3_PHY_AUX_CLK_SRC			56
691.1Sjmcneill#define USB_HS_SYSTEM_CLK_SRC			57
701.1Sjmcneill#define GCC_BLSP1_AHB_CLK			58
711.1Sjmcneill#define GCC_BLSP1_QUP1_I2C_APPS_CLK		59
721.1Sjmcneill#define GCC_BLSP1_QUP1_SPI_APPS_CLK		60
731.1Sjmcneill#define GCC_BLSP1_QUP2_I2C_APPS_CLK		61
741.1Sjmcneill#define GCC_BLSP1_QUP2_SPI_APPS_CLK		62
751.1Sjmcneill#define GCC_BLSP1_QUP3_I2C_APPS_CLK		63
761.1Sjmcneill#define GCC_BLSP1_QUP3_SPI_APPS_CLK		64
771.1Sjmcneill#define GCC_BLSP1_QUP4_I2C_APPS_CLK		65
781.1Sjmcneill#define GCC_BLSP1_QUP4_SPI_APPS_CLK		66
791.1Sjmcneill#define GCC_BLSP1_QUP5_I2C_APPS_CLK		67
801.1Sjmcneill#define GCC_BLSP1_QUP5_SPI_APPS_CLK		68
811.1Sjmcneill#define GCC_BLSP1_QUP6_I2C_APPS_CLK		69
821.1Sjmcneill#define GCC_BLSP1_QUP6_SPI_APPS_CLK		70
831.1Sjmcneill#define GCC_BLSP1_UART1_APPS_CLK		71
841.1Sjmcneill#define GCC_BLSP1_UART2_APPS_CLK		72
851.1Sjmcneill#define GCC_BLSP1_UART3_APPS_CLK		73
861.1Sjmcneill#define GCC_BLSP1_UART4_APPS_CLK		74
871.1Sjmcneill#define GCC_BLSP1_UART5_APPS_CLK		75
881.1Sjmcneill#define GCC_BLSP1_UART6_APPS_CLK		76
891.1Sjmcneill#define GCC_BLSP2_AHB_CLK			77
901.1Sjmcneill#define GCC_BLSP2_QUP1_I2C_APPS_CLK		78
911.1Sjmcneill#define GCC_BLSP2_QUP1_SPI_APPS_CLK		79
921.1Sjmcneill#define GCC_BLSP2_QUP2_I2C_APPS_CLK		80
931.1Sjmcneill#define GCC_BLSP2_QUP2_SPI_APPS_CLK		81
941.1Sjmcneill#define GCC_BLSP2_QUP3_I2C_APPS_CLK		82
951.1Sjmcneill#define GCC_BLSP2_QUP3_SPI_APPS_CLK		83
961.1Sjmcneill#define GCC_BLSP2_QUP4_I2C_APPS_CLK		84
971.1Sjmcneill#define GCC_BLSP2_QUP4_SPI_APPS_CLK		85
981.1Sjmcneill#define GCC_BLSP2_QUP5_I2C_APPS_CLK		86
991.1Sjmcneill#define GCC_BLSP2_QUP5_SPI_APPS_CLK		87
1001.1Sjmcneill#define GCC_BLSP2_QUP6_I2C_APPS_CLK		88
1011.1Sjmcneill#define GCC_BLSP2_QUP6_SPI_APPS_CLK		89
1021.1Sjmcneill#define GCC_BLSP2_UART1_APPS_CLK		90
1031.1Sjmcneill#define GCC_BLSP2_UART2_APPS_CLK		91
1041.1Sjmcneill#define GCC_BLSP2_UART3_APPS_CLK		92
1051.1Sjmcneill#define GCC_BLSP2_UART4_APPS_CLK		93
1061.1Sjmcneill#define GCC_BLSP2_UART5_APPS_CLK		94
1071.1Sjmcneill#define GCC_BLSP2_UART6_APPS_CLK		95
1081.1Sjmcneill#define GCC_GP1_CLK				96
1091.1Sjmcneill#define GCC_GP2_CLK				97
1101.1Sjmcneill#define GCC_GP3_CLK				98
1111.1Sjmcneill#define GCC_PCIE_0_AUX_CLK			99
1121.1Sjmcneill#define GCC_PCIE_0_PIPE_CLK			100
1131.1Sjmcneill#define GCC_PCIE_1_AUX_CLK			101
1141.1Sjmcneill#define GCC_PCIE_1_PIPE_CLK			102
1151.1Sjmcneill#define GCC_PDM2_CLK				103
1161.1Sjmcneill#define GCC_SDCC1_APPS_CLK			104
1171.1Sjmcneill#define GCC_SDCC2_APPS_CLK			105
1181.1Sjmcneill#define GCC_SDCC3_APPS_CLK			106
1191.1Sjmcneill#define GCC_SDCC4_APPS_CLK			107
1201.1Sjmcneill#define GCC_SYS_NOC_UFS_AXI_CLK			108
1211.1Sjmcneill#define GCC_SYS_NOC_USB3_AXI_CLK		109
1221.1Sjmcneill#define GCC_TSIF_REF_CLK			110
1231.1Sjmcneill#define GCC_UFS_AXI_CLK				111
1241.1Sjmcneill#define GCC_UFS_RX_CFG_CLK			112
1251.1Sjmcneill#define GCC_UFS_TX_CFG_CLK			113
1261.1Sjmcneill#define GCC_USB30_MASTER_CLK			114
1271.1Sjmcneill#define GCC_USB30_MOCK_UTMI_CLK			115
1281.1Sjmcneill#define GCC_USB3_PHY_AUX_CLK			116
1291.1Sjmcneill#define GCC_USB_HS_SYSTEM_CLK			117
1301.1Sjmcneill#define GCC_SDCC1_AHB_CLK			118
1311.1.1.3Sjmcneill#define GCC_LPASS_Q6_AXI_CLK		119
1321.1.1.3Sjmcneill#define GCC_MSS_Q6_BIMC_AXI_CLK		120
1331.1.1.3Sjmcneill#define GCC_PCIE_0_CFG_AHB_CLK		121
1341.1.1.3Sjmcneill#define GCC_PCIE_0_MSTR_AXI_CLK		122
1351.1.1.3Sjmcneill#define GCC_PCIE_0_SLV_AXI_CLK		123
1361.1.1.3Sjmcneill#define GCC_PCIE_1_CFG_AHB_CLK		124
1371.1.1.3Sjmcneill#define GCC_PCIE_1_MSTR_AXI_CLK		125
1381.1.1.3Sjmcneill#define GCC_PCIE_1_SLV_AXI_CLK		126
1391.1.1.3Sjmcneill#define GCC_PDM_AHB_CLK				127
1401.1.1.3Sjmcneill#define GCC_SDCC2_AHB_CLK			128
1411.1.1.3Sjmcneill#define GCC_SDCC3_AHB_CLK			129
1421.1.1.3Sjmcneill#define GCC_SDCC4_AHB_CLK			130
1431.1.1.3Sjmcneill#define GCC_TSIF_AHB_CLK			131
1441.1.1.3Sjmcneill#define GCC_UFS_AHB_CLK				132
1451.1.1.3Sjmcneill#define GCC_UFS_RX_SYMBOL_0_CLK		133
1461.1.1.3Sjmcneill#define GCC_UFS_RX_SYMBOL_1_CLK		134
1471.1.1.3Sjmcneill#define GCC_UFS_TX_SYMBOL_0_CLK		135
1481.1.1.3Sjmcneill#define GCC_UFS_TX_SYMBOL_1_CLK		136
1491.1.1.3Sjmcneill#define GCC_USB2_HS_PHY_SLEEP_CLK	137
1501.1.1.3Sjmcneill#define GCC_USB30_SLEEP_CLK			138
1511.1.1.3Sjmcneill#define GCC_USB_HS_AHB_CLK			139
1521.1.1.3Sjmcneill#define GCC_USB_PHY_CFG_AHB2PHY_CLK	140
1531.1.1.3Sjmcneill
1541.1.1.3Sjmcneill/* GDSCs */
1551.1.1.3Sjmcneill#define PCIE_GDSC			0
1561.1.1.3Sjmcneill#define PCIE_0_GDSC			1
1571.1.1.3Sjmcneill#define PCIE_1_GDSC			2
1581.1.1.3Sjmcneill#define USB30_GDSC			3
1591.1.1.3Sjmcneill#define UFS_GDSC			4
1601.1.1.3Sjmcneill
1611.1.1.3Sjmcneill/* Resets */
1621.1.1.3Sjmcneill#define USB3_PHY_RESET			0
1631.1.1.3Sjmcneill#define USB3PHY_PHY_RESET		1
1641.1.1.3Sjmcneill#define PCIE_PHY_0_RESET		2
1651.1.1.3Sjmcneill#define PCIE_PHY_1_RESET		3
1661.1.1.3Sjmcneill#define QUSB2_PHY_RESET			4
1671.1Sjmcneill
1681.1Sjmcneill#endif
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