qcom,gcc-msm8998.h revision 1.1.1.2
1/* $NetBSD: qcom,gcc-msm8998.h,v 1.1.1.2 2019/05/25 11:29:13 jmcneill Exp $ */ 2 3/* 4 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H 17#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H 18 19#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 20#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 21#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 22#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 23#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 24#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 25#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 26#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 27#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8 28#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9 29#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10 30#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11 31#define BLSP1_UART1_APPS_CLK_SRC 12 32#define BLSP1_UART2_APPS_CLK_SRC 13 33#define BLSP1_UART3_APPS_CLK_SRC 14 34#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15 35#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16 36#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17 37#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18 38#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19 39#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20 40#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21 41#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22 42#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23 43#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24 44#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25 45#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26 46#define BLSP2_UART1_APPS_CLK_SRC 27 47#define BLSP2_UART2_APPS_CLK_SRC 28 48#define BLSP2_UART3_APPS_CLK_SRC 29 49#define GCC_AGGRE1_NOC_XO_CLK 30 50#define GCC_AGGRE1_UFS_AXI_CLK 31 51#define GCC_AGGRE1_USB3_AXI_CLK 32 52#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33 53#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34 54#define GCC_BIMC_HMSS_AXI_CLK 35 55#define GCC_BIMC_MSS_Q6_AXI_CLK 36 56#define GCC_BLSP1_AHB_CLK 37 57#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38 58#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39 59#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40 60#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41 61#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42 62#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43 63#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44 64#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45 65#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46 66#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47 67#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48 68#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49 69#define GCC_BLSP1_SLEEP_CLK 50 70#define GCC_BLSP1_UART1_APPS_CLK 51 71#define GCC_BLSP1_UART2_APPS_CLK 52 72#define GCC_BLSP1_UART3_APPS_CLK 53 73#define GCC_BLSP2_AHB_CLK 54 74#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55 75#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56 76#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57 77#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58 78#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59 79#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60 80#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61 81#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62 82#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63 83#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64 84#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65 85#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66 86#define GCC_BLSP2_SLEEP_CLK 67 87#define GCC_BLSP2_UART1_APPS_CLK 68 88#define GCC_BLSP2_UART2_APPS_CLK 69 89#define GCC_BLSP2_UART3_APPS_CLK 70 90#define GCC_CFG_NOC_USB3_AXI_CLK 71 91#define GCC_GP1_CLK 72 92#define GCC_GP2_CLK 73 93#define GCC_GP3_CLK 74 94#define GCC_GPU_BIMC_GFX_CLK 75 95#define GCC_GPU_BIMC_GFX_SRC_CLK 76 96#define GCC_GPU_CFG_AHB_CLK 77 97#define GCC_GPU_SNOC_DVM_GFX_CLK 78 98#define GCC_HMSS_AHB_CLK 79 99#define GCC_HMSS_AT_CLK 80 100#define GCC_HMSS_DVM_BUS_CLK 81 101#define GCC_HMSS_RBCPR_CLK 82 102#define GCC_HMSS_TRIG_CLK 83 103#define GCC_LPASS_AT_CLK 84 104#define GCC_LPASS_TRIG_CLK 85 105#define GCC_MMSS_NOC_CFG_AHB_CLK 86 106#define GCC_MMSS_QM_AHB_CLK 87 107#define GCC_MMSS_QM_CORE_CLK 88 108#define GCC_MMSS_SYS_NOC_AXI_CLK 89 109#define GCC_MSS_AT_CLK 90 110#define GCC_PCIE_0_AUX_CLK 91 111#define GCC_PCIE_0_CFG_AHB_CLK 92 112#define GCC_PCIE_0_MSTR_AXI_CLK 93 113#define GCC_PCIE_0_PIPE_CLK 94 114#define GCC_PCIE_0_SLV_AXI_CLK 95 115#define GCC_PCIE_PHY_AUX_CLK 96 116#define GCC_PDM2_CLK 97 117#define GCC_PDM_AHB_CLK 98 118#define GCC_PDM_XO4_CLK 99 119#define GCC_PRNG_AHB_CLK 100 120#define GCC_SDCC2_AHB_CLK 101 121#define GCC_SDCC2_APPS_CLK 102 122#define GCC_SDCC4_AHB_CLK 103 123#define GCC_SDCC4_APPS_CLK 104 124#define GCC_TSIF_AHB_CLK 105 125#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106 126#define GCC_TSIF_REF_CLK 107 127#define GCC_UFS_AHB_CLK 108 128#define GCC_UFS_AXI_CLK 109 129#define GCC_UFS_ICE_CORE_CLK 110 130#define GCC_UFS_PHY_AUX_CLK 111 131#define GCC_UFS_RX_SYMBOL_0_CLK 112 132#define GCC_UFS_RX_SYMBOL_1_CLK 113 133#define GCC_UFS_TX_SYMBOL_0_CLK 114 134#define GCC_UFS_UNIPRO_CORE_CLK 115 135#define GCC_USB30_MASTER_CLK 116 136#define GCC_USB30_MOCK_UTMI_CLK 117 137#define GCC_USB30_SLEEP_CLK 118 138#define GCC_USB3_PHY_AUX_CLK 119 139#define GCC_USB3_PHY_PIPE_CLK 120 140#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121 141#define GP1_CLK_SRC 122 142#define GP2_CLK_SRC 123 143#define GP3_CLK_SRC 124 144#define GPLL0 125 145#define GPLL0_OUT_EVEN 126 146#define GPLL0_OUT_MAIN 127 147#define GPLL0_OUT_ODD 128 148#define GPLL0_OUT_TEST 129 149#define GPLL1 130 150#define GPLL1_OUT_EVEN 131 151#define GPLL1_OUT_MAIN 132 152#define GPLL1_OUT_ODD 133 153#define GPLL1_OUT_TEST 134 154#define GPLL2 135 155#define GPLL2_OUT_EVEN 136 156#define GPLL2_OUT_MAIN 137 157#define GPLL2_OUT_ODD 138 158#define GPLL2_OUT_TEST 139 159#define GPLL3 140 160#define GPLL3_OUT_EVEN 141 161#define GPLL3_OUT_MAIN 142 162#define GPLL3_OUT_ODD 143 163#define GPLL3_OUT_TEST 144 164#define GPLL4 145 165#define GPLL4_OUT_EVEN 146 166#define GPLL4_OUT_MAIN 147 167#define GPLL4_OUT_ODD 148 168#define GPLL4_OUT_TEST 149 169#define GPLL6 150 170#define GPLL6_OUT_EVEN 151 171#define GPLL6_OUT_MAIN 152 172#define GPLL6_OUT_ODD 153 173#define GPLL6_OUT_TEST 154 174#define HMSS_AHB_CLK_SRC 155 175#define HMSS_RBCPR_CLK_SRC 156 176#define PCIE_AUX_CLK_SRC 157 177#define PDM2_CLK_SRC 158 178#define SDCC2_APPS_CLK_SRC 159 179#define SDCC4_APPS_CLK_SRC 160 180#define TSIF_REF_CLK_SRC 161 181#define UFS_AXI_CLK_SRC 162 182#define USB30_MASTER_CLK_SRC 163 183#define USB30_MOCK_UTMI_CLK_SRC 164 184#define USB3_PHY_AUX_CLK_SRC 165 185#define GCC_USB3_CLKREF_CLK 166 186#define GCC_HDMI_CLKREF_CLK 167 187#define GCC_UFS_CLKREF_CLK 168 188#define GCC_PCIE_CLKREF_CLK 169 189#define GCC_RX1_USB2_CLKREF_CLK 170 190 191#define PCIE_0_GDSC 0 192#define UFS_GDSC 1 193#define USB_30_GDSC 2 194 195#define GCC_BLSP1_QUP1_BCR 0 196#define GCC_BLSP1_QUP2_BCR 1 197#define GCC_BLSP1_QUP3_BCR 2 198#define GCC_BLSP1_QUP4_BCR 3 199#define GCC_BLSP1_QUP5_BCR 4 200#define GCC_BLSP1_QUP6_BCR 5 201#define GCC_BLSP2_QUP1_BCR 6 202#define GCC_BLSP2_QUP2_BCR 7 203#define GCC_BLSP2_QUP3_BCR 8 204#define GCC_BLSP2_QUP4_BCR 9 205#define GCC_BLSP2_QUP5_BCR 10 206#define GCC_BLSP2_QUP6_BCR 11 207#define GCC_PCIE_0_BCR 12 208#define GCC_PDM_BCR 13 209#define GCC_SDCC2_BCR 14 210#define GCC_SDCC4_BCR 15 211#define GCC_TSIF_BCR 16 212#define GCC_UFS_BCR 17 213#define GCC_USB_30_BCR 18 214#define GCC_SYSTEM_NOC_BCR 19 215#define GCC_CONFIG_NOC_BCR 20 216#define GCC_AHB2PHY_EAST_BCR 21 217#define GCC_IMEM_BCR 22 218#define GCC_PIMEM_BCR 23 219#define GCC_MMSS_BCR 24 220#define GCC_QDSS_BCR 25 221#define GCC_WCSS_BCR 26 222#define GCC_BLSP1_BCR 27 223#define GCC_BLSP1_UART1_BCR 28 224#define GCC_BLSP1_UART2_BCR 29 225#define GCC_BLSP1_UART3_BCR 30 226#define GCC_CM_PHY_REFGEN1_BCR 31 227#define GCC_CM_PHY_REFGEN2_BCR 32 228#define GCC_BLSP2_BCR 33 229#define GCC_BLSP2_UART1_BCR 34 230#define GCC_BLSP2_UART2_BCR 35 231#define GCC_BLSP2_UART3_BCR 36 232#define GCC_SRAM_SENSOR_BCR 37 233#define GCC_PRNG_BCR 38 234#define GCC_TSIF_0_RESET 39 235#define GCC_TSIF_1_RESET 40 236#define GCC_TCSR_BCR 41 237#define GCC_BOOT_ROM_BCR 42 238#define GCC_MSG_RAM_BCR 43 239#define GCC_TLMM_BCR 44 240#define GCC_MPM_BCR 45 241#define GCC_SEC_CTRL_BCR 46 242#define GCC_SPMI_BCR 47 243#define GCC_SPDM_BCR 48 244#define GCC_CE1_BCR 49 245#define GCC_BIMC_BCR 50 246#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 247#define GCC_SNOC_BUS_TIMEOUT1_BCR 52 248#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 249#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 54 250#define GCC_PNOC_BUS_TIMEOUT0_BCR 55 251#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 56 252#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 57 253#define GCC_CNOC_BUS_TIMEOUT0_BCR 58 254#define GCC_CNOC_BUS_TIMEOUT1_BCR 59 255#define GCC_CNOC_BUS_TIMEOUT2_BCR 60 256#define GCC_CNOC_BUS_TIMEOUT3_BCR 61 257#define GCC_CNOC_BUS_TIMEOUT4_BCR 62 258#define GCC_CNOC_BUS_TIMEOUT5_BCR 63 259#define GCC_CNOC_BUS_TIMEOUT6_BCR 64 260#define GCC_CNOC_BUS_TIMEOUT7_BCR 65 261#define GCC_APB2JTAG_BCR 66 262#define GCC_RBCPR_CX_BCR 67 263#define GCC_RBCPR_MX_BCR 68 264#define GCC_USB3_PHY_BCR 69 265#define GCC_USB3PHY_PHY_BCR 70 266#define GCC_USB3_DP_PHY_BCR 71 267#define GCC_SSC_BCR 72 268#define GCC_SSC_RESET 73 269#define GCC_USB_PHY_CFG_AHB2PHY_BCR 74 270#define GCC_PCIE_0_LINK_DOWN_BCR 75 271#define GCC_PCIE_0_PHY_BCR 76 272#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 77 273#define GCC_PCIE_PHY_BCR 78 274#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 79 275#define GCC_PCIE_PHY_CFG_AHB_BCR 80 276#define GCC_PCIE_PHY_COM_BCR 81 277#define GCC_GPU_BCR 82 278#define GCC_SPSS_BCR 83 279#define GCC_OBT_ODT_BCR 84 280#define GCC_VS_BCR 85 281#define GCC_MSS_VS_RESET 86 282#define GCC_GPU_VS_RESET 87 283#define GCC_APC0_VS_RESET 88 284#define GCC_APC1_VS_RESET 89 285#define GCC_CNOC_BUS_TIMEOUT8_BCR 90 286#define GCC_CNOC_BUS_TIMEOUT9_BCR 91 287#define GCC_CNOC_BUS_TIMEOUT10_BCR 92 288#define GCC_CNOC_BUS_TIMEOUT11_BCR 93 289#define GCC_CNOC_BUS_TIMEOUT12_BCR 94 290#define GCC_CNOC_BUS_TIMEOUT13_BCR 95 291#define GCC_CNOC_BUS_TIMEOUT14_BCR 96 292#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 97 293#define GCC_AGGRE1_NOC_BCR 98 294#define GCC_AGGRE2_NOC_BCR 99 295#define GCC_DCC_BCR 100 296#define GCC_QREFS_VBG_CAL_BCR 101 297#define GCC_IPA_BCR 102 298#define GCC_GLM_BCR 103 299#define GCC_SKL_BCR 104 300#define GCC_MSMPU_BCR 105 301#define GCC_QUSB2PHY_PRIM_BCR 106 302#define GCC_QUSB2PHY_SEC_BCR 107 303 304#endif 305