11.1Sjmcneill/* $NetBSD: qcom,gcc-qcs404.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (c) 2018, The Linux Foundation. All rights reserved. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H 91.1Sjmcneill#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H 101.1Sjmcneill 111.1Sjmcneill#define GCC_APSS_AHB_CLK_SRC 0 121.1Sjmcneill#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 131.1Sjmcneill#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 141.1Sjmcneill#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 151.1Sjmcneill#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 161.1Sjmcneill#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 171.1Sjmcneill#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 181.1Sjmcneill#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 191.1Sjmcneill#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 201.1Sjmcneill#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 211.1Sjmcneill#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 221.1Sjmcneill#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 231.1Sjmcneill#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 241.1Sjmcneill#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 251.1Sjmcneill#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 261.1Sjmcneill#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 271.1Sjmcneill#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 281.1Sjmcneill#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 291.1Sjmcneill#define GCC_BYTE0_CLK_SRC 18 301.1Sjmcneill#define GCC_EMAC_CLK_SRC 19 311.1Sjmcneill#define GCC_EMAC_PTP_CLK_SRC 20 321.1Sjmcneill#define GCC_ESC0_CLK_SRC 21 331.1Sjmcneill#define GCC_APSS_AHB_CLK 22 341.1Sjmcneill#define GCC_APSS_AXI_CLK 23 351.1Sjmcneill#define GCC_BIMC_APSS_AXI_CLK 24 361.1Sjmcneill#define GCC_BIMC_GFX_CLK 25 371.1Sjmcneill#define GCC_BIMC_MDSS_CLK 26 381.1Sjmcneill#define GCC_BLSP1_AHB_CLK 27 391.1Sjmcneill#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 401.1Sjmcneill#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 411.1Sjmcneill#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 421.1Sjmcneill#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 431.1Sjmcneill#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 441.1Sjmcneill#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 451.1Sjmcneill#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 461.1Sjmcneill#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 471.1Sjmcneill#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 481.1Sjmcneill#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 491.1Sjmcneill#define GCC_BLSP1_UART0_APPS_CLK 38 501.1Sjmcneill#define GCC_BLSP1_UART1_APPS_CLK 39 511.1Sjmcneill#define GCC_BLSP1_UART2_APPS_CLK 40 521.1Sjmcneill#define GCC_BLSP1_UART3_APPS_CLK 41 531.1Sjmcneill#define GCC_BLSP2_AHB_CLK 42 541.1Sjmcneill#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 551.1Sjmcneill#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 561.1Sjmcneill#define GCC_BLSP2_UART0_APPS_CLK 45 571.1Sjmcneill#define GCC_BOOT_ROM_AHB_CLK 46 581.1Sjmcneill#define GCC_DCC_CLK 47 591.1Sjmcneill#define GCC_GENI_IR_H_CLK 48 601.1Sjmcneill#define GCC_ETH_AXI_CLK 49 611.1Sjmcneill#define GCC_ETH_PTP_CLK 50 621.1Sjmcneill#define GCC_ETH_RGMII_CLK 51 631.1Sjmcneill#define GCC_ETH_SLAVE_AHB_CLK 52 641.1Sjmcneill#define GCC_GENI_IR_S_CLK 53 651.1Sjmcneill#define GCC_GP1_CLK 54 661.1Sjmcneill#define GCC_GP2_CLK 55 671.1Sjmcneill#define GCC_GP3_CLK 56 681.1Sjmcneill#define GCC_MDSS_AHB_CLK 57 691.1Sjmcneill#define GCC_MDSS_AXI_CLK 58 701.1Sjmcneill#define GCC_MDSS_BYTE0_CLK 59 711.1Sjmcneill#define GCC_MDSS_ESC0_CLK 60 721.1Sjmcneill#define GCC_MDSS_HDMI_APP_CLK 61 731.1Sjmcneill#define GCC_MDSS_HDMI_PCLK_CLK 62 741.1Sjmcneill#define GCC_MDSS_MDP_CLK 63 751.1Sjmcneill#define GCC_MDSS_PCLK0_CLK 64 761.1Sjmcneill#define GCC_MDSS_VSYNC_CLK 65 771.1Sjmcneill#define GCC_OXILI_AHB_CLK 66 781.1Sjmcneill#define GCC_OXILI_GFX3D_CLK 67 791.1Sjmcneill#define GCC_PCIE_0_AUX_CLK 68 801.1Sjmcneill#define GCC_PCIE_0_CFG_AHB_CLK 69 811.1Sjmcneill#define GCC_PCIE_0_MSTR_AXI_CLK 70 821.1Sjmcneill#define GCC_PCIE_0_PIPE_CLK 71 831.1Sjmcneill#define GCC_PCIE_0_SLV_AXI_CLK 72 841.1Sjmcneill#define GCC_PCNOC_USB2_CLK 73 851.1Sjmcneill#define GCC_PCNOC_USB3_CLK 74 861.1Sjmcneill#define GCC_PDM2_CLK 75 871.1Sjmcneill#define GCC_PDM_AHB_CLK 76 881.1Sjmcneill#define GCC_VSYNC_CLK_SRC 77 891.1Sjmcneill#define GCC_PRNG_AHB_CLK 78 901.1Sjmcneill#define GCC_PWM0_XO512_CLK 79 911.1Sjmcneill#define GCC_PWM1_XO512_CLK 80 921.1Sjmcneill#define GCC_PWM2_XO512_CLK 81 931.1Sjmcneill#define GCC_SDCC1_AHB_CLK 82 941.1Sjmcneill#define GCC_SDCC1_APPS_CLK 83 951.1Sjmcneill#define GCC_SDCC1_ICE_CORE_CLK 84 961.1Sjmcneill#define GCC_SDCC2_AHB_CLK 85 971.1Sjmcneill#define GCC_SDCC2_APPS_CLK 86 981.1Sjmcneill#define GCC_SYS_NOC_USB3_CLK 87 991.1Sjmcneill#define GCC_USB20_MOCK_UTMI_CLK 88 1001.1Sjmcneill#define GCC_USB2A_PHY_SLEEP_CLK 89 1011.1Sjmcneill#define GCC_USB30_MASTER_CLK 90 1021.1Sjmcneill#define GCC_USB30_MOCK_UTMI_CLK 91 1031.1Sjmcneill#define GCC_USB30_SLEEP_CLK 92 1041.1Sjmcneill#define GCC_USB3_PHY_AUX_CLK 93 1051.1Sjmcneill#define GCC_USB3_PHY_PIPE_CLK 94 1061.1Sjmcneill#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 1071.1Sjmcneill#define GCC_USB_HS_SYSTEM_CLK 96 1081.1Sjmcneill#define GCC_GFX3D_CLK_SRC 97 1091.1Sjmcneill#define GCC_GP1_CLK_SRC 98 1101.1Sjmcneill#define GCC_GP2_CLK_SRC 99 1111.1Sjmcneill#define GCC_GP3_CLK_SRC 100 1121.1Sjmcneill#define GCC_GPLL0_OUT_MAIN 101 1131.1Sjmcneill#define GCC_GPLL1_OUT_MAIN 102 1141.1Sjmcneill#define GCC_GPLL3_OUT_MAIN 103 1151.1Sjmcneill#define GCC_GPLL4_OUT_MAIN 104 1161.1Sjmcneill#define GCC_HDMI_APP_CLK_SRC 105 1171.1Sjmcneill#define GCC_HDMI_PCLK_CLK_SRC 106 1181.1Sjmcneill#define GCC_MDP_CLK_SRC 107 1191.1Sjmcneill#define GCC_PCIE_0_AUX_CLK_SRC 108 1201.1Sjmcneill#define GCC_PCIE_0_PIPE_CLK_SRC 109 1211.1Sjmcneill#define GCC_PCLK0_CLK_SRC 110 1221.1Sjmcneill#define GCC_PDM2_CLK_SRC 111 1231.1Sjmcneill#define GCC_SDCC1_APPS_CLK_SRC 112 1241.1Sjmcneill#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 1251.1Sjmcneill#define GCC_SDCC2_APPS_CLK_SRC 114 1261.1Sjmcneill#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 1271.1Sjmcneill#define GCC_USB30_MASTER_CLK_SRC 116 1281.1Sjmcneill#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 1291.1Sjmcneill#define GCC_USB3_PHY_AUX_CLK_SRC 118 1301.1Sjmcneill#define GCC_USB_HS_SYSTEM_CLK_SRC 119 1311.1Sjmcneill#define GCC_GPLL0_AO_CLK_SRC 120 1321.1Sjmcneill#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 1331.1Sjmcneill#define GCC_GPLL0_AO_OUT_MAIN 123 1341.1Sjmcneill#define GCC_GPLL0_SLEEP_CLK_SRC 124 1351.1Sjmcneill#define GCC_GPLL6 125 1361.1Sjmcneill#define GCC_GPLL6_OUT_AUX 126 1371.1Sjmcneill#define GCC_MDSS_MDP_VOTE_CLK 127 1381.1Sjmcneill#define GCC_MDSS_ROTATOR_VOTE_CLK 128 1391.1Sjmcneill#define GCC_BIMC_GPU_CLK 129 1401.1Sjmcneill#define GCC_GTCU_AHB_CLK 130 1411.1Sjmcneill#define GCC_GFX_TCU_CLK 131 1421.1Sjmcneill#define GCC_GFX_TBU_CLK 132 1431.1Sjmcneill#define GCC_SMMU_CFG_CLK 133 1441.1Sjmcneill#define GCC_APSS_TCU_CLK 134 1451.1Sjmcneill#define GCC_CRYPTO_AHB_CLK 135 1461.1Sjmcneill#define GCC_CRYPTO_AXI_CLK 136 1471.1Sjmcneill#define GCC_CRYPTO_CLK 137 1481.1Sjmcneill#define GCC_MDP_TBU_CLK 138 1491.1Sjmcneill#define GCC_QDSS_DAP_CLK 139 1501.1Sjmcneill#define GCC_DCC_XO_CLK 140 1511.1.1.2Sskrll#define GCC_WCSS_Q6_AHB_CLK 141 1521.1.1.2Sskrll#define GCC_WCSS_Q6_AXIM_CLK 142 1531.1.1.2Sskrll#define GCC_CDSP_CFG_AHB_CLK 143 1541.1.1.2Sskrll#define GCC_BIMC_CDSP_CLK 144 1551.1.1.2Sskrll#define GCC_CDSP_TBU_CLK 145 1561.1.1.2Sskrll#define GCC_CDSP_BIMC_CLK_SRC 146 1571.1Sjmcneill 1581.1Sjmcneill#define GCC_GENI_IR_BCR 0 1591.1Sjmcneill#define GCC_USB_HS_BCR 1 1601.1Sjmcneill#define GCC_USB2_HS_PHY_ONLY_BCR 2 1611.1Sjmcneill#define GCC_QUSB2_PHY_BCR 3 1621.1Sjmcneill#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 1631.1Sjmcneill#define GCC_USB2A_PHY_BCR 5 1641.1Sjmcneill#define GCC_USB3_PHY_BCR 6 1651.1Sjmcneill#define GCC_USB_30_BCR 7 1661.1Sjmcneill#define GCC_USB3PHY_PHY_BCR 8 1671.1Sjmcneill#define GCC_PCIE_0_BCR 9 1681.1Sjmcneill#define GCC_PCIE_0_PHY_BCR 10 1691.1Sjmcneill#define GCC_PCIE_0_LINK_DOWN_BCR 11 1701.1Sjmcneill#define GCC_PCIEPHY_0_PHY_BCR 12 1711.1Sjmcneill#define GCC_EMAC_BCR 13 1721.1.1.2Sskrll#define GCC_CDSP_RESTART 14 1731.1.1.2Sskrll#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 1741.1.1.2Sskrll#define GCC_PCIE_0_AHB_ARES 16 1751.1.1.2Sskrll#define GCC_PCIE_0_AXI_SLAVE_ARES 17 1761.1.1.2Sskrll#define GCC_PCIE_0_AXI_MASTER_ARES 18 1771.1.1.2Sskrll#define GCC_PCIE_0_CORE_STICKY_ARES 19 1781.1.1.2Sskrll#define GCC_PCIE_0_SLEEP_ARES 20 1791.1.1.2Sskrll#define GCC_PCIE_0_PIPE_ARES 21 1801.1.1.2Sskrll#define GCC_WDSP_RESTART 22 1811.1Sjmcneill 1821.1Sjmcneill#endif 183