11.1Sjmcneill/* $NetBSD: qcom,gcc-sc8180x.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 61.1Sjmcneill * Copyright (c) 2021, Linaro Ltd. 71.1Sjmcneill */ 81.1Sjmcneill 91.1Sjmcneill#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H 101.1Sjmcneill#define _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H 111.1Sjmcneill 121.1Sjmcneill#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 131.1Sjmcneill#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 141.1Sjmcneill#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 151.1Sjmcneill#define GCC_AGGRE_UFS_PHY_AXI_CLK 3 161.1Sjmcneill#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 171.1Sjmcneill#define GCC_AGGRE_USB3_MP_AXI_CLK 5 181.1Sjmcneill#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6 191.1Sjmcneill#define GCC_AGGRE_USB3_SEC_AXI_CLK 7 201.1Sjmcneill#define GCC_BOOT_ROM_AHB_CLK 8 211.1Sjmcneill#define GCC_CAMERA_HF_AXI_CLK 9 221.1Sjmcneill#define GCC_CAMERA_SF_AXI_CLK 10 231.1Sjmcneill#define GCC_CFG_NOC_USB3_MP_AXI_CLK 11 241.1Sjmcneill#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 251.1Sjmcneill#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 261.1Sjmcneill#define GCC_CPUSS_AHB_CLK 14 271.1Sjmcneill#define GCC_CPUSS_AHB_CLK_SRC 15 281.1Sjmcneill#define GCC_CPUSS_RBCPR_CLK 16 291.1Sjmcneill#define GCC_DDRSS_GPU_AXI_CLK 17 301.1Sjmcneill#define GCC_DISP_HF_AXI_CLK 18 311.1Sjmcneill#define GCC_DISP_SF_AXI_CLK 19 321.1Sjmcneill#define GCC_EMAC_AXI_CLK 20 331.1Sjmcneill#define GCC_EMAC_PTP_CLK 21 341.1Sjmcneill#define GCC_EMAC_PTP_CLK_SRC 22 351.1Sjmcneill#define GCC_EMAC_RGMII_CLK 23 361.1Sjmcneill#define GCC_EMAC_RGMII_CLK_SRC 24 371.1Sjmcneill#define GCC_EMAC_SLV_AHB_CLK 25 381.1Sjmcneill#define GCC_GP1_CLK 26 391.1Sjmcneill#define GCC_GP1_CLK_SRC 27 401.1Sjmcneill#define GCC_GP2_CLK 28 411.1Sjmcneill#define GCC_GP2_CLK_SRC 29 421.1Sjmcneill#define GCC_GP3_CLK 30 431.1Sjmcneill#define GCC_GP3_CLK_SRC 31 441.1Sjmcneill#define GCC_GP4_CLK 32 451.1Sjmcneill#define GCC_GP4_CLK_SRC 33 461.1Sjmcneill#define GCC_GP5_CLK 34 471.1Sjmcneill#define GCC_GP5_CLK_SRC 35 481.1Sjmcneill#define GCC_GPU_GPLL0_CLK_SRC 36 491.1Sjmcneill#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 501.1Sjmcneill#define GCC_GPU_MEMNOC_GFX_CLK 38 511.1Sjmcneill#define GCC_GPU_SNOC_DVM_GFX_CLK 39 521.1Sjmcneill#define GCC_NPU_AT_CLK 40 531.1Sjmcneill#define GCC_NPU_AXI_CLK 41 541.1Sjmcneill#define GCC_NPU_AXI_CLK_SRC 42 551.1Sjmcneill#define GCC_NPU_GPLL0_CLK_SRC 43 561.1Sjmcneill#define GCC_NPU_GPLL0_DIV_CLK_SRC 44 571.1Sjmcneill#define GCC_NPU_TRIG_CLK 45 581.1Sjmcneill#define GCC_PCIE0_PHY_REFGEN_CLK 46 591.1Sjmcneill#define GCC_PCIE1_PHY_REFGEN_CLK 47 601.1Sjmcneill#define GCC_PCIE2_PHY_REFGEN_CLK 48 611.1Sjmcneill#define GCC_PCIE3_PHY_REFGEN_CLK 49 621.1Sjmcneill#define GCC_PCIE_0_AUX_CLK 50 631.1Sjmcneill#define GCC_PCIE_0_AUX_CLK_SRC 51 641.1Sjmcneill#define GCC_PCIE_0_CFG_AHB_CLK 52 651.1Sjmcneill#define GCC_PCIE_0_MSTR_AXI_CLK 53 661.1Sjmcneill#define GCC_PCIE_0_PIPE_CLK 54 671.1Sjmcneill#define GCC_PCIE_0_SLV_AXI_CLK 55 681.1Sjmcneill#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56 691.1Sjmcneill#define GCC_PCIE_1_AUX_CLK 57 701.1Sjmcneill#define GCC_PCIE_1_AUX_CLK_SRC 58 711.1Sjmcneill#define GCC_PCIE_1_CFG_AHB_CLK 59 721.1Sjmcneill#define GCC_PCIE_1_MSTR_AXI_CLK 60 731.1Sjmcneill#define GCC_PCIE_1_PIPE_CLK 61 741.1Sjmcneill#define GCC_PCIE_1_SLV_AXI_CLK 62 751.1Sjmcneill#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63 761.1Sjmcneill#define GCC_PCIE_2_AUX_CLK 64 771.1Sjmcneill#define GCC_PCIE_2_AUX_CLK_SRC 65 781.1Sjmcneill#define GCC_PCIE_2_CFG_AHB_CLK 66 791.1Sjmcneill#define GCC_PCIE_2_MSTR_AXI_CLK 67 801.1Sjmcneill#define GCC_PCIE_2_PIPE_CLK 68 811.1Sjmcneill#define GCC_PCIE_2_SLV_AXI_CLK 69 821.1Sjmcneill#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 70 831.1Sjmcneill#define GCC_PCIE_3_AUX_CLK 71 841.1Sjmcneill#define GCC_PCIE_3_AUX_CLK_SRC 72 851.1Sjmcneill#define GCC_PCIE_3_CFG_AHB_CLK 73 861.1Sjmcneill#define GCC_PCIE_3_MSTR_AXI_CLK 74 871.1Sjmcneill#define GCC_PCIE_3_PIPE_CLK 75 881.1Sjmcneill#define GCC_PCIE_3_SLV_AXI_CLK 76 891.1Sjmcneill#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 77 901.1Sjmcneill#define GCC_PCIE_PHY_AUX_CLK 78 911.1Sjmcneill#define GCC_PCIE_PHY_REFGEN_CLK_SRC 79 921.1Sjmcneill#define GCC_PDM2_CLK 80 931.1Sjmcneill#define GCC_PDM2_CLK_SRC 81 941.1Sjmcneill#define GCC_PDM_AHB_CLK 82 951.1Sjmcneill#define GCC_PDM_XO4_CLK 83 961.1Sjmcneill#define GCC_PRNG_AHB_CLK 84 971.1Sjmcneill#define GCC_QMIP_CAMERA_NRT_AHB_CLK 85 981.1Sjmcneill#define GCC_QMIP_CAMERA_RT_AHB_CLK 86 991.1Sjmcneill#define GCC_QMIP_DISP_AHB_CLK 87 1001.1Sjmcneill#define GCC_QMIP_VIDEO_CVP_AHB_CLK 88 1011.1Sjmcneill#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89 1021.1Sjmcneill#define GCC_QSPI_1_CNOC_PERIPH_AHB_CLK 90 1031.1Sjmcneill#define GCC_QSPI_1_CORE_CLK 91 1041.1Sjmcneill#define GCC_QSPI_1_CORE_CLK_SRC 92 1051.1Sjmcneill#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 93 1061.1Sjmcneill#define GCC_QSPI_CORE_CLK 94 1071.1Sjmcneill#define GCC_QSPI_CORE_CLK_SRC 95 1081.1Sjmcneill#define GCC_QUPV3_WRAP0_S0_CLK 96 1091.1Sjmcneill#define GCC_QUPV3_WRAP0_S0_CLK_SRC 97 1101.1Sjmcneill#define GCC_QUPV3_WRAP0_S1_CLK 98 1111.1Sjmcneill#define GCC_QUPV3_WRAP0_S1_CLK_SRC 99 1121.1Sjmcneill#define GCC_QUPV3_WRAP0_S2_CLK 100 1131.1Sjmcneill#define GCC_QUPV3_WRAP0_S2_CLK_SRC 101 1141.1Sjmcneill#define GCC_QUPV3_WRAP0_S3_CLK 102 1151.1Sjmcneill#define GCC_QUPV3_WRAP0_S3_CLK_SRC 103 1161.1Sjmcneill#define GCC_QUPV3_WRAP0_S4_CLK 104 1171.1Sjmcneill#define GCC_QUPV3_WRAP0_S4_CLK_SRC 105 1181.1Sjmcneill#define GCC_QUPV3_WRAP0_S5_CLK 106 1191.1Sjmcneill#define GCC_QUPV3_WRAP0_S5_CLK_SRC 107 1201.1Sjmcneill#define GCC_QUPV3_WRAP0_S6_CLK 108 1211.1Sjmcneill#define GCC_QUPV3_WRAP0_S6_CLK_SRC 109 1221.1Sjmcneill#define GCC_QUPV3_WRAP0_S7_CLK 110 1231.1Sjmcneill#define GCC_QUPV3_WRAP0_S7_CLK_SRC 111 1241.1Sjmcneill#define GCC_QUPV3_WRAP1_S0_CLK 112 1251.1Sjmcneill#define GCC_QUPV3_WRAP1_S0_CLK_SRC 113 1261.1Sjmcneill#define GCC_QUPV3_WRAP1_S1_CLK 114 1271.1Sjmcneill#define GCC_QUPV3_WRAP1_S1_CLK_SRC 115 1281.1Sjmcneill#define GCC_QUPV3_WRAP1_S2_CLK 116 1291.1Sjmcneill#define GCC_QUPV3_WRAP1_S2_CLK_SRC 117 1301.1Sjmcneill#define GCC_QUPV3_WRAP1_S3_CLK 118 1311.1Sjmcneill#define GCC_QUPV3_WRAP1_S3_CLK_SRC 119 1321.1Sjmcneill#define GCC_QUPV3_WRAP1_S4_CLK 120 1331.1Sjmcneill#define GCC_QUPV3_WRAP1_S4_CLK_SRC 121 1341.1Sjmcneill#define GCC_QUPV3_WRAP1_S5_CLK 122 1351.1Sjmcneill#define GCC_QUPV3_WRAP1_S5_CLK_SRC 123 1361.1Sjmcneill#define GCC_QUPV3_WRAP2_S0_CLK 124 1371.1Sjmcneill#define GCC_QUPV3_WRAP2_S0_CLK_SRC 125 1381.1Sjmcneill#define GCC_QUPV3_WRAP2_S1_CLK 126 1391.1Sjmcneill#define GCC_QUPV3_WRAP2_S1_CLK_SRC 127 1401.1Sjmcneill#define GCC_QUPV3_WRAP2_S2_CLK 128 1411.1Sjmcneill#define GCC_QUPV3_WRAP2_S2_CLK_SRC 129 1421.1Sjmcneill#define GCC_QUPV3_WRAP2_S3_CLK 130 1431.1Sjmcneill#define GCC_QUPV3_WRAP2_S3_CLK_SRC 131 1441.1Sjmcneill#define GCC_QUPV3_WRAP2_S4_CLK 132 1451.1Sjmcneill#define GCC_QUPV3_WRAP2_S4_CLK_SRC 133 1461.1Sjmcneill#define GCC_QUPV3_WRAP2_S5_CLK 134 1471.1Sjmcneill#define GCC_QUPV3_WRAP2_S5_CLK_SRC 135 1481.1Sjmcneill#define GCC_QUPV3_WRAP_0_M_AHB_CLK 136 1491.1Sjmcneill#define GCC_QUPV3_WRAP_0_S_AHB_CLK 137 1501.1Sjmcneill#define GCC_QUPV3_WRAP_1_M_AHB_CLK 138 1511.1Sjmcneill#define GCC_QUPV3_WRAP_1_S_AHB_CLK 139 1521.1Sjmcneill#define GCC_QUPV3_WRAP_2_M_AHB_CLK 140 1531.1Sjmcneill#define GCC_QUPV3_WRAP_2_S_AHB_CLK 141 1541.1Sjmcneill#define GCC_SDCC2_AHB_CLK 142 1551.1Sjmcneill#define GCC_SDCC2_APPS_CLK 143 1561.1Sjmcneill#define GCC_SDCC2_APPS_CLK_SRC 144 1571.1Sjmcneill#define GCC_SDCC4_AHB_CLK 145 1581.1Sjmcneill#define GCC_SDCC4_APPS_CLK 146 1591.1Sjmcneill#define GCC_SDCC4_APPS_CLK_SRC 147 1601.1Sjmcneill#define GCC_SYS_NOC_CPUSS_AHB_CLK 148 1611.1Sjmcneill#define GCC_TSIF_AHB_CLK 149 1621.1Sjmcneill#define GCC_TSIF_INACTIVITY_TIMERS_CLK 150 1631.1Sjmcneill#define GCC_TSIF_REF_CLK 151 1641.1Sjmcneill#define GCC_TSIF_REF_CLK_SRC 152 1651.1Sjmcneill#define GCC_UFS_CARD_2_AHB_CLK 153 1661.1Sjmcneill#define GCC_UFS_CARD_2_AXI_CLK 154 1671.1Sjmcneill#define GCC_UFS_CARD_2_AXI_CLK_SRC 155 1681.1Sjmcneill#define GCC_UFS_CARD_2_ICE_CORE_CLK 156 1691.1Sjmcneill#define GCC_UFS_CARD_2_ICE_CORE_CLK_SRC 157 1701.1Sjmcneill#define GCC_UFS_CARD_2_PHY_AUX_CLK 158 1711.1Sjmcneill#define GCC_UFS_CARD_2_PHY_AUX_CLK_SRC 159 1721.1Sjmcneill#define GCC_UFS_CARD_2_RX_SYMBOL_0_CLK 160 1731.1Sjmcneill#define GCC_UFS_CARD_2_RX_SYMBOL_1_CLK 161 1741.1Sjmcneill#define GCC_UFS_CARD_2_TX_SYMBOL_0_CLK 162 1751.1Sjmcneill#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK 163 1761.1Sjmcneill#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC 164 1771.1Sjmcneill#define GCC_UFS_CARD_AHB_CLK 165 1781.1Sjmcneill#define GCC_UFS_CARD_AXI_CLK 166 1791.1Sjmcneill#define GCC_UFS_CARD_AXI_CLK_SRC 167 1801.1Sjmcneill#define GCC_UFS_CARD_AXI_HW_CTL_CLK 168 1811.1Sjmcneill#define GCC_UFS_CARD_ICE_CORE_CLK 169 1821.1Sjmcneill#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 170 1831.1Sjmcneill#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 171 1841.1Sjmcneill#define GCC_UFS_CARD_PHY_AUX_CLK 172 1851.1Sjmcneill#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 173 1861.1Sjmcneill#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 174 1871.1Sjmcneill#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 175 1881.1Sjmcneill#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 176 1891.1Sjmcneill#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 177 1901.1Sjmcneill#define GCC_UFS_CARD_UNIPRO_CORE_CLK 178 1911.1Sjmcneill#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 179 1921.1Sjmcneill#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 180 1931.1Sjmcneill#define GCC_UFS_PHY_AHB_CLK 181 1941.1Sjmcneill#define GCC_UFS_PHY_AXI_CLK 182 1951.1Sjmcneill#define GCC_UFS_PHY_AXI_CLK_SRC 183 1961.1Sjmcneill#define GCC_UFS_PHY_AXI_HW_CTL_CLK 184 1971.1Sjmcneill#define GCC_UFS_PHY_ICE_CORE_CLK 185 1981.1Sjmcneill#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 186 1991.1Sjmcneill#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 187 2001.1Sjmcneill#define GCC_UFS_PHY_PHY_AUX_CLK 188 2011.1Sjmcneill#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 189 2021.1Sjmcneill#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 190 2031.1Sjmcneill#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 191 2041.1Sjmcneill#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 192 2051.1Sjmcneill#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 193 2061.1Sjmcneill#define GCC_UFS_PHY_UNIPRO_CORE_CLK 194 2071.1Sjmcneill#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 195 2081.1Sjmcneill#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 196 2091.1Sjmcneill#define GCC_USB30_MP_MASTER_CLK 197 2101.1Sjmcneill#define GCC_USB30_MP_MASTER_CLK_SRC 198 2111.1Sjmcneill#define GCC_USB30_MP_MOCK_UTMI_CLK 199 2121.1Sjmcneill#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 200 2131.1Sjmcneill#define GCC_USB30_MP_SLEEP_CLK 201 2141.1Sjmcneill#define GCC_USB30_PRIM_MASTER_CLK 202 2151.1Sjmcneill#define GCC_USB30_PRIM_MASTER_CLK_SRC 203 2161.1Sjmcneill#define GCC_USB30_PRIM_MOCK_UTMI_CLK 204 2171.1Sjmcneill#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 205 2181.1Sjmcneill#define GCC_USB30_PRIM_SLEEP_CLK 206 2191.1Sjmcneill#define GCC_USB30_SEC_MASTER_CLK 207 2201.1Sjmcneill#define GCC_USB30_SEC_MASTER_CLK_SRC 208 2211.1Sjmcneill#define GCC_USB30_SEC_MOCK_UTMI_CLK 209 2221.1Sjmcneill#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 210 2231.1Sjmcneill#define GCC_USB30_SEC_SLEEP_CLK 211 2241.1Sjmcneill#define GCC_USB3_MP_PHY_AUX_CLK 212 2251.1Sjmcneill#define GCC_USB3_MP_PHY_AUX_CLK_SRC 213 2261.1Sjmcneill#define GCC_USB3_MP_PHY_COM_AUX_CLK 214 2271.1Sjmcneill#define GCC_USB3_MP_PHY_PIPE_0_CLK 215 2281.1Sjmcneill#define GCC_USB3_MP_PHY_PIPE_1_CLK 216 2291.1Sjmcneill#define GCC_USB3_PRIM_PHY_AUX_CLK 217 2301.1Sjmcneill#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 218 2311.1Sjmcneill#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 219 2321.1Sjmcneill#define GCC_USB3_PRIM_PHY_PIPE_CLK 220 2331.1Sjmcneill#define GCC_USB3_SEC_PHY_AUX_CLK 221 2341.1Sjmcneill#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 222 2351.1Sjmcneill#define GCC_USB3_SEC_PHY_COM_AUX_CLK 223 2361.1Sjmcneill#define GCC_USB3_SEC_PHY_PIPE_CLK 224 2371.1Sjmcneill#define GCC_VIDEO_AXI0_CLK 225 2381.1Sjmcneill#define GCC_VIDEO_AXI1_CLK 226 2391.1Sjmcneill#define GCC_VIDEO_AXIC_CLK 227 2401.1Sjmcneill#define GPLL0 228 2411.1Sjmcneill#define GPLL0_OUT_EVEN 229 2421.1Sjmcneill#define GPLL1 230 2431.1Sjmcneill#define GPLL4 231 2441.1Sjmcneill#define GPLL7 232 2451.1Sjmcneill#define GCC_PCIE_0_CLKREF_CLK 233 2461.1Sjmcneill#define GCC_PCIE_1_CLKREF_CLK 234 2471.1Sjmcneill#define GCC_PCIE_2_CLKREF_CLK 235 2481.1Sjmcneill#define GCC_PCIE_3_CLKREF_CLK 236 2491.1Sjmcneill#define GCC_USB3_PRIM_CLKREF_CLK 237 2501.1Sjmcneill#define GCC_USB3_SEC_CLKREF_CLK 238 2511.1Sjmcneill 2521.1Sjmcneill#define GCC_EMAC_BCR 0 2531.1Sjmcneill#define GCC_GPU_BCR 1 2541.1Sjmcneill#define GCC_MMSS_BCR 2 2551.1Sjmcneill#define GCC_NPU_BCR 3 2561.1Sjmcneill#define GCC_PCIE_0_BCR 4 2571.1Sjmcneill#define GCC_PCIE_0_PHY_BCR 5 2581.1Sjmcneill#define GCC_PCIE_1_BCR 6 2591.1Sjmcneill#define GCC_PCIE_1_PHY_BCR 7 2601.1Sjmcneill#define GCC_PCIE_2_BCR 8 2611.1Sjmcneill#define GCC_PCIE_2_PHY_BCR 9 2621.1Sjmcneill#define GCC_PCIE_3_BCR 10 2631.1Sjmcneill#define GCC_PCIE_3_PHY_BCR 11 2641.1Sjmcneill#define GCC_PCIE_PHY_BCR 12 2651.1Sjmcneill#define GCC_PDM_BCR 13 2661.1Sjmcneill#define GCC_PRNG_BCR 14 2671.1Sjmcneill#define GCC_QSPI_1_BCR 15 2681.1Sjmcneill#define GCC_QSPI_BCR 16 2691.1Sjmcneill#define GCC_QUPV3_WRAPPER_0_BCR 17 2701.1Sjmcneill#define GCC_QUPV3_WRAPPER_1_BCR 18 2711.1Sjmcneill#define GCC_QUPV3_WRAPPER_2_BCR 19 2721.1Sjmcneill#define GCC_QUSB2PHY_5_BCR 20 2731.1Sjmcneill#define GCC_QUSB2PHY_MP0_BCR 21 2741.1Sjmcneill#define GCC_QUSB2PHY_MP1_BCR 22 2751.1Sjmcneill#define GCC_QUSB2PHY_PRIM_BCR 23 2761.1Sjmcneill#define GCC_QUSB2PHY_SEC_BCR 24 2771.1Sjmcneill#define GCC_USB3_PHY_PRIM_SP0_BCR 25 2781.1Sjmcneill#define GCC_USB3_PHY_PRIM_SP1_BCR 26 2791.1Sjmcneill#define GCC_USB3_DP_PHY_PRIM_SP0_BCR 27 2801.1Sjmcneill#define GCC_USB3_DP_PHY_PRIM_SP1_BCR 28 2811.1Sjmcneill#define GCC_USB3_PHY_SEC_BCR 29 2821.1Sjmcneill#define GCC_USB3PHY_PHY_SEC_BCR 30 2831.1Sjmcneill#define GCC_SDCC2_BCR 31 2841.1Sjmcneill#define GCC_SDCC4_BCR 32 2851.1Sjmcneill#define GCC_TSIF_BCR 33 2861.1Sjmcneill#define GCC_UFS_CARD_2_BCR 34 2871.1Sjmcneill#define GCC_UFS_CARD_BCR 35 2881.1Sjmcneill#define GCC_UFS_PHY_BCR 36 2891.1Sjmcneill#define GCC_USB30_MP_BCR 37 2901.1Sjmcneill#define GCC_USB30_PRIM_BCR 38 2911.1Sjmcneill#define GCC_USB30_SEC_BCR 39 2921.1Sjmcneill#define GCC_USB_PHY_CFG_AHB2PHY_BCR 40 2931.1Sjmcneill#define GCC_VIDEO_AXIC_CLK_BCR 41 2941.1Sjmcneill#define GCC_VIDEO_AXI0_CLK_BCR 42 2951.1Sjmcneill#define GCC_VIDEO_AXI1_CLK_BCR 43 2961.1Sjmcneill#define GCC_USB3_DP_PHY_SEC_BCR 44 2971.1Sjmcneill 2981.1Sjmcneill/* GCC GDSCRs */ 2991.1Sjmcneill#define EMAC_GDSC 0 3001.1Sjmcneill#define PCIE_0_GDSC 1 3011.1Sjmcneill#define PCIE_1_GDSC 2 3021.1Sjmcneill#define PCIE_2_GDSC 3 3031.1Sjmcneill#define PCIE_3_GDSC 4 3041.1Sjmcneill#define UFS_CARD_2_GDSC 5 3051.1Sjmcneill#define UFS_CARD_GDSC 6 3061.1Sjmcneill#define UFS_PHY_GDSC 7 3071.1Sjmcneill#define USB30_MP_GDSC 8 3081.1Sjmcneill#define USB30_PRIM_GDSC 9 3091.1Sjmcneill#define USB30_SEC_GDSC 10 3101.1Sjmcneill 3111.1Sjmcneill#endif 312