11.1Sjmcneill/*	$NetBSD: qcom,gcc-sm6125.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $	*/
21.1Sjmcneill
31.1Sjmcneill/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
41.1Sjmcneill/*
51.1Sjmcneill * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
61.1Sjmcneill */
71.1Sjmcneill
81.1Sjmcneill#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H
91.1Sjmcneill#define _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H
101.1Sjmcneill
111.1Sjmcneill#define GPLL0_OUT_AUX2				0
121.1Sjmcneill#define GPLL0_OUT_MAIN				1
131.1Sjmcneill#define GPLL6_OUT_MAIN				2
141.1Sjmcneill#define GPLL7_OUT_MAIN				3
151.1Sjmcneill#define GPLL8_OUT_MAIN				4
161.1Sjmcneill#define GPLL9_OUT_MAIN				5
171.1Sjmcneill#define GPLL0_OUT_EARLY				6
181.1Sjmcneill#define GPLL3_OUT_EARLY				7
191.1Sjmcneill#define GPLL4_OUT_MAIN				8
201.1Sjmcneill#define GPLL5_OUT_MAIN				9
211.1Sjmcneill#define GPLL6_OUT_EARLY				10
221.1Sjmcneill#define GPLL7_OUT_EARLY				11
231.1Sjmcneill#define GPLL8_OUT_EARLY				12
241.1Sjmcneill#define GPLL9_OUT_EARLY				13
251.1Sjmcneill#define GCC_AHB2PHY_CSI_CLK			14
261.1Sjmcneill#define GCC_AHB2PHY_USB_CLK			15
271.1Sjmcneill#define GCC_APC_VS_CLK				16
281.1Sjmcneill#define GCC_BOOT_ROM_AHB_CLK		17
291.1Sjmcneill#define GCC_CAMERA_AHB_CLK			18
301.1Sjmcneill#define GCC_CAMERA_XO_CLK			19
311.1Sjmcneill#define GCC_CAMSS_AHB_CLK_SRC		20
321.1Sjmcneill#define GCC_CAMSS_CCI_AHB_CLK		21
331.1Sjmcneill#define GCC_CAMSS_CCI_CLK			22
341.1Sjmcneill#define GCC_CAMSS_CCI_CLK_SRC			23
351.1Sjmcneill#define GCC_CAMSS_CPHY_CSID0_CLK		24
361.1Sjmcneill#define GCC_CAMSS_CPHY_CSID1_CLK		25
371.1Sjmcneill#define GCC_CAMSS_CPHY_CSID2_CLK		26
381.1Sjmcneill#define GCC_CAMSS_CPHY_CSID3_CLK		27
391.1Sjmcneill#define GCC_CAMSS_CPP_AHB_CLK			28
401.1Sjmcneill#define GCC_CAMSS_CPP_AXI_CLK			29
411.1Sjmcneill#define GCC_CAMSS_CPP_CLK			30
421.1Sjmcneill#define GCC_CAMSS_CPP_CLK_SRC			31
431.1Sjmcneill#define GCC_CAMSS_CPP_VBIF_AHB_CLK		32
441.1Sjmcneill#define GCC_CAMSS_CSI0_AHB_CLK			33
451.1Sjmcneill#define GCC_CAMSS_CSI0_CLK				34
461.1Sjmcneill#define GCC_CAMSS_CSI0_CLK_SRC			35
471.1Sjmcneill#define GCC_CAMSS_CSI0PHYTIMER_CLK		36
481.1Sjmcneill#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC	37
491.1Sjmcneill#define GCC_CAMSS_CSI0PIX_CLK			38
501.1Sjmcneill#define GCC_CAMSS_CSI0RDI_CLK			39
511.1Sjmcneill#define GCC_CAMSS_CSI1_AHB_CLK			40
521.1Sjmcneill#define GCC_CAMSS_CSI1_CLK				41
531.1Sjmcneill#define GCC_CAMSS_CSI1_CLK_SRC			42
541.1Sjmcneill#define GCC_CAMSS_CSI1PHYTIMER_CLK		43
551.1Sjmcneill#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC	44
561.1Sjmcneill#define GCC_CAMSS_CSI1PIX_CLK			45
571.1Sjmcneill#define GCC_CAMSS_CSI1RDI_CLK			46
581.1Sjmcneill#define GCC_CAMSS_CSI2_AHB_CLK			47
591.1Sjmcneill#define GCC_CAMSS_CSI2_CLK				48
601.1Sjmcneill#define GCC_CAMSS_CSI2_CLK_SRC			49
611.1Sjmcneill#define GCC_CAMSS_CSI2PHYTIMER_CLK		50
621.1Sjmcneill#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC	51
631.1Sjmcneill#define GCC_CAMSS_CSI2PIX_CLK			52
641.1Sjmcneill#define GCC_CAMSS_CSI2RDI_CLK			53
651.1Sjmcneill#define GCC_CAMSS_CSI3_AHB_CLK			54
661.1Sjmcneill#define GCC_CAMSS_CSI3_CLK				55
671.1Sjmcneill#define GCC_CAMSS_CSI3_CLK_SRC			56
681.1Sjmcneill#define GCC_CAMSS_CSI3PIX_CLK			57
691.1Sjmcneill#define GCC_CAMSS_CSI3RDI_CLK			58
701.1Sjmcneill#define GCC_CAMSS_CSI_VFE0_CLK			59
711.1Sjmcneill#define GCC_CAMSS_CSI_VFE1_CLK			60
721.1Sjmcneill#define GCC_CAMSS_CSIPHY0_CLK			61
731.1Sjmcneill#define GCC_CAMSS_CSIPHY1_CLK			62
741.1Sjmcneill#define GCC_CAMSS_CSIPHY2_CLK			63
751.1Sjmcneill#define GCC_CAMSS_CSIPHY_CLK_SRC		64
761.1Sjmcneill#define GCC_CAMSS_GP0_CLK				65
771.1Sjmcneill#define GCC_CAMSS_GP0_CLK_SRC			66
781.1Sjmcneill#define GCC_CAMSS_GP1_CLK				67
791.1Sjmcneill#define GCC_CAMSS_GP1_CLK_SRC			68
801.1Sjmcneill#define GCC_CAMSS_ISPIF_AHB_CLK			69
811.1Sjmcneill#define GCC_CAMSS_JPEG_AHB_CLK			70
821.1Sjmcneill#define GCC_CAMSS_JPEG_AXI_CLK			71
831.1Sjmcneill#define GCC_CAMSS_JPEG_CLK				72
841.1Sjmcneill#define GCC_CAMSS_JPEG_CLK_SRC			73
851.1Sjmcneill#define GCC_CAMSS_MCLK0_CLK				74
861.1Sjmcneill#define GCC_CAMSS_MCLK0_CLK_SRC			75
871.1Sjmcneill#define GCC_CAMSS_MCLK1_CLK				76
881.1Sjmcneill#define GCC_CAMSS_MCLK1_CLK_SRC			77
891.1Sjmcneill#define GCC_CAMSS_MCLK2_CLK				78
901.1Sjmcneill#define GCC_CAMSS_MCLK2_CLK_SRC			79
911.1Sjmcneill#define GCC_CAMSS_MCLK3_CLK				80
921.1Sjmcneill#define GCC_CAMSS_MCLK3_CLK_SRC			81
931.1Sjmcneill#define GCC_CAMSS_MICRO_AHB_CLK			82
941.1Sjmcneill#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK	83
951.1Sjmcneill#define GCC_CAMSS_THROTTLE_RT_AXI_CLK	84
961.1Sjmcneill#define GCC_CAMSS_TOP_AHB_CLK			85
971.1Sjmcneill#define GCC_CAMSS_VFE0_AHB_CLK			86
981.1Sjmcneill#define GCC_CAMSS_VFE0_CLK				87
991.1Sjmcneill#define GCC_CAMSS_VFE0_CLK_SRC			88
1001.1Sjmcneill#define GCC_CAMSS_VFE0_STREAM_CLK		89
1011.1Sjmcneill#define GCC_CAMSS_VFE1_AHB_CLK			90
1021.1Sjmcneill#define GCC_CAMSS_VFE1_CLK				91
1031.1Sjmcneill#define GCC_CAMSS_VFE1_CLK_SRC			92
1041.1Sjmcneill#define GCC_CAMSS_VFE1_STREAM_CLK		93
1051.1Sjmcneill#define GCC_CAMSS_VFE_TSCTR_CLK			94
1061.1Sjmcneill#define GCC_CAMSS_VFE_VBIF_AHB_CLK		95
1071.1Sjmcneill#define GCC_CAMSS_VFE_VBIF_AXI_CLK		96
1081.1Sjmcneill#define GCC_CE1_AHB_CLK					97
1091.1Sjmcneill#define GCC_CE1_AXI_CLK					98
1101.1Sjmcneill#define GCC_CE1_CLK						99
1111.1Sjmcneill#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK	100
1121.1Sjmcneill#define GCC_CPUSS_GNOC_CLK				101
1131.1Sjmcneill#define GCC_DISP_AHB_CLK				102
1141.1Sjmcneill#define GCC_DISP_GPLL0_DIV_CLK_SRC		103
1151.1Sjmcneill#define GCC_DISP_HF_AXI_CLK				104
1161.1Sjmcneill#define GCC_DISP_THROTTLE_CORE_CLK		105
1171.1Sjmcneill#define GCC_DISP_XO_CLK					106
1181.1Sjmcneill#define GCC_GP1_CLK						107
1191.1Sjmcneill#define GCC_GP1_CLK_SRC					108
1201.1Sjmcneill#define GCC_GP2_CLK						109
1211.1Sjmcneill#define GCC_GP2_CLK_SRC					110
1221.1Sjmcneill#define GCC_GP3_CLK						111
1231.1Sjmcneill#define GCC_GP3_CLK_SRC					112
1241.1Sjmcneill#define GCC_GPU_CFG_AHB_CLK				113
1251.1Sjmcneill#define GCC_GPU_GPLL0_CLK_SRC			114
1261.1Sjmcneill#define GCC_GPU_GPLL0_DIV_CLK_SRC		115
1271.1Sjmcneill#define GCC_GPU_MEMNOC_GFX_CLK			116
1281.1Sjmcneill#define GCC_GPU_SNOC_DVM_GFX_CLK		117
1291.1Sjmcneill#define GCC_GPU_THROTTLE_CORE_CLK		118
1301.1Sjmcneill#define GCC_GPU_THROTTLE_XO_CLK			119
1311.1Sjmcneill#define GCC_MSS_VS_CLK					120
1321.1Sjmcneill#define GCC_PDM2_CLK					121
1331.1Sjmcneill#define GCC_PDM2_CLK_SRC				122
1341.1Sjmcneill#define GCC_PDM_AHB_CLK					123
1351.1Sjmcneill#define GCC_PDM_XO4_CLK					124
1361.1Sjmcneill#define GCC_PRNG_AHB_CLK				125
1371.1Sjmcneill#define GCC_QMIP_CAMERA_NRT_AHB_CLK		126
1381.1Sjmcneill#define GCC_QMIP_CAMERA_RT_AHB_CLK		127
1391.1Sjmcneill#define GCC_QMIP_DISP_AHB_CLK			128
1401.1Sjmcneill#define GCC_QMIP_GPU_CFG_AHB_CLK		129
1411.1Sjmcneill#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK	130
1421.1Sjmcneill#define GCC_QUPV3_WRAP0_CORE_2X_CLK		131
1431.1Sjmcneill#define GCC_QUPV3_WRAP0_CORE_CLK		132
1441.1Sjmcneill#define GCC_QUPV3_WRAP0_S0_CLK			133
1451.1Sjmcneill#define GCC_QUPV3_WRAP0_S0_CLK_SRC		134
1461.1Sjmcneill#define GCC_QUPV3_WRAP0_S1_CLK			135
1471.1Sjmcneill#define GCC_QUPV3_WRAP0_S1_CLK_SRC		136
1481.1Sjmcneill#define GCC_QUPV3_WRAP0_S2_CLK			137
1491.1Sjmcneill#define GCC_QUPV3_WRAP0_S2_CLK_SRC		138
1501.1Sjmcneill#define GCC_QUPV3_WRAP0_S3_CLK			139
1511.1Sjmcneill#define GCC_QUPV3_WRAP0_S3_CLK_SRC		140
1521.1Sjmcneill#define GCC_QUPV3_WRAP0_S4_CLK			141
1531.1Sjmcneill#define GCC_QUPV3_WRAP0_S4_CLK_SRC		142
1541.1Sjmcneill#define GCC_QUPV3_WRAP0_S5_CLK			143
1551.1Sjmcneill#define GCC_QUPV3_WRAP0_S5_CLK_SRC		144
1561.1Sjmcneill#define GCC_QUPV3_WRAP1_CORE_2X_CLK		145
1571.1Sjmcneill#define GCC_QUPV3_WRAP1_CORE_CLK		146
1581.1Sjmcneill#define GCC_QUPV3_WRAP1_S0_CLK			147
1591.1Sjmcneill#define GCC_QUPV3_WRAP1_S0_CLK_SRC		148
1601.1Sjmcneill#define GCC_QUPV3_WRAP1_S1_CLK			149
1611.1Sjmcneill#define GCC_QUPV3_WRAP1_S1_CLK_SRC		150
1621.1Sjmcneill#define GCC_QUPV3_WRAP1_S2_CLK			151
1631.1Sjmcneill#define GCC_QUPV3_WRAP1_S2_CLK_SRC		152
1641.1Sjmcneill#define GCC_QUPV3_WRAP1_S3_CLK			153
1651.1Sjmcneill#define GCC_QUPV3_WRAP1_S3_CLK_SRC		154
1661.1Sjmcneill#define GCC_QUPV3_WRAP1_S4_CLK			155
1671.1Sjmcneill#define GCC_QUPV3_WRAP1_S4_CLK_SRC		156
1681.1Sjmcneill#define GCC_QUPV3_WRAP1_S5_CLK			157
1691.1Sjmcneill#define GCC_QUPV3_WRAP1_S5_CLK_SRC		158
1701.1Sjmcneill#define GCC_QUPV3_WRAP_0_M_AHB_CLK		159
1711.1Sjmcneill#define GCC_QUPV3_WRAP_0_S_AHB_CLK		160
1721.1Sjmcneill#define GCC_QUPV3_WRAP_1_M_AHB_CLK		161
1731.1Sjmcneill#define GCC_QUPV3_WRAP_1_S_AHB_CLK		162
1741.1Sjmcneill#define GCC_SDCC1_AHB_CLK				163
1751.1Sjmcneill#define GCC_SDCC1_APPS_CLK				164
1761.1Sjmcneill#define GCC_SDCC1_APPS_CLK_SRC			165
1771.1Sjmcneill#define GCC_SDCC1_ICE_CORE_CLK			166
1781.1Sjmcneill#define GCC_SDCC1_ICE_CORE_CLK_SRC		167
1791.1Sjmcneill#define GCC_SDCC2_AHB_CLK				168
1801.1Sjmcneill#define GCC_SDCC2_APPS_CLK				169
1811.1Sjmcneill#define GCC_SDCC2_APPS_CLK_SRC			170
1821.1Sjmcneill#define GCC_SYS_NOC_CPUSS_AHB_CLK		171
1831.1Sjmcneill#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		172
1841.1Sjmcneill#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK	173
1851.1Sjmcneill#define GCC_UFS_PHY_AHB_CLK				174
1861.1Sjmcneill#define GCC_UFS_PHY_AXI_CLK				175
1871.1Sjmcneill#define GCC_UFS_PHY_AXI_CLK_SRC			176
1881.1Sjmcneill#define GCC_UFS_PHY_ICE_CORE_CLK		177
1891.1Sjmcneill#define GCC_UFS_PHY_ICE_CORE_CLK_SRC	178
1901.1Sjmcneill#define GCC_UFS_PHY_PHY_AUX_CLK			179
1911.1Sjmcneill#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		180
1921.1Sjmcneill#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		181
1931.1Sjmcneill#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		182
1941.1Sjmcneill#define GCC_UFS_PHY_UNIPRO_CORE_CLK		183
1951.1Sjmcneill#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC	184
1961.1Sjmcneill#define GCC_USB30_PRIM_MASTER_CLK		185
1971.1Sjmcneill#define GCC_USB30_PRIM_MASTER_CLK_SRC	186
1981.1Sjmcneill#define GCC_USB30_PRIM_MOCK_UTMI_CLK	187
1991.1Sjmcneill#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	188
2001.1Sjmcneill#define GCC_USB30_PRIM_SLEEP_CLK		189
2011.1Sjmcneill#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC	190
2021.1Sjmcneill#define GCC_USB3_PRIM_PHY_COM_AUX_CLK	191
2031.1Sjmcneill#define GCC_USB3_PRIM_PHY_PIPE_CLK		192
2041.1Sjmcneill#define GCC_VDDA_VS_CLK					193
2051.1Sjmcneill#define GCC_VDDCX_VS_CLK				194
2061.1Sjmcneill#define GCC_VDDMX_VS_CLK				195
2071.1Sjmcneill#define GCC_VIDEO_AHB_CLK				196
2081.1Sjmcneill#define GCC_VIDEO_AXI0_CLK				197
2091.1Sjmcneill#define GCC_VIDEO_THROTTLE_CORE_CLK		198
2101.1Sjmcneill#define GCC_VIDEO_XO_CLK				199
2111.1Sjmcneill#define GCC_VS_CTRL_AHB_CLK				200
2121.1Sjmcneill#define GCC_VS_CTRL_CLK					201
2131.1Sjmcneill#define GCC_VS_CTRL_CLK_SRC				202
2141.1Sjmcneill#define GCC_VSENSOR_CLK_SRC				203
2151.1Sjmcneill#define GCC_WCSS_VS_CLK					204
2161.1Sjmcneill#define GCC_USB3_PRIM_CLKREF_CLK		205
2171.1Sjmcneill#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK	206
2181.1Sjmcneill#define GCC_BIMC_GPU_AXI_CLK			207
2191.1Sjmcneill#define GCC_UFS_MEM_CLKREF_CLK			208
2201.1Sjmcneill
2211.1Sjmcneill/* GDSCs */
2221.1Sjmcneill#define USB30_PRIM_GDSC					0
2231.1Sjmcneill#define UFS_PHY_GDSC					1
2241.1Sjmcneill#define CAMSS_VFE0_GDSC					2
2251.1Sjmcneill#define CAMSS_VFE1_GDSC					3
2261.1Sjmcneill#define CAMSS_TOP_GDSC					4
2271.1Sjmcneill#define CAM_CPP_GDSC					5
2281.1Sjmcneill#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC	6
2291.1Sjmcneill#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC	7
2301.1Sjmcneill#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC	8
2311.1Sjmcneill#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC	9
2321.1Sjmcneill
2331.1Sjmcneill#define GCC_QUSB2PHY_PRIM_BCR			0
2341.1Sjmcneill#define GCC_QUSB2PHY_SEC_BCR			1
2351.1Sjmcneill#define GCC_UFS_PHY_BCR				2
2361.1Sjmcneill#define GCC_USB30_PRIM_BCR			3
2371.1Sjmcneill#define GCC_USB_PHY_CFG_AHB2PHY_BCR		4
2381.1Sjmcneill#define GCC_USB3_PHY_PRIM_SP0_BCR		5
2391.1Sjmcneill#define GCC_USB3PHY_PHY_PRIM_SP0_BCR		6
2401.1Sjmcneill#define GCC_CAMSS_MICRO_BCR			7
2411.1Sjmcneill
2421.1Sjmcneill#endif
243