r7s72100-clock.h revision 1.1.1.5 
1/*	$NetBSD: r7s72100-clock.h,v 1.1.1.5 2019/01/22 14:57:02 jmcneill Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0
4 *
5 * Copyright (C) 2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7 */
8
9#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
10#define __DT_BINDINGS_CLOCK_R7S72100_H__
11
12#define R7S72100_CLK_PLL	0
13#define R7S72100_CLK_I		1
14#define R7S72100_CLK_G		2
15
16/* MSTP2 */
17#define R7S72100_CLK_CORESIGHT	0
18
19/* MSTP3 */
20#define R7S72100_CLK_IEBUS	7
21#define R7S72100_CLK_IRDA	6
22#define R7S72100_CLK_LIN0	5
23#define R7S72100_CLK_LIN1	4
24#define R7S72100_CLK_MTU2	3
25#define R7S72100_CLK_CAN	2
26#define R7S72100_CLK_ADCPWR	1
27#define R7S72100_CLK_PWM	0
28
29/* MSTP4 */
30#define R7S72100_CLK_SCIF0	7
31#define R7S72100_CLK_SCIF1	6
32#define R7S72100_CLK_SCIF2	5
33#define R7S72100_CLK_SCIF3	4
34#define R7S72100_CLK_SCIF4	3
35#define R7S72100_CLK_SCIF5	2
36#define R7S72100_CLK_SCIF6	1
37#define R7S72100_CLK_SCIF7	0
38
39/* MSTP5 */
40#define R7S72100_CLK_SCI0	7
41#define R7S72100_CLK_SCI1	6
42#define R7S72100_CLK_SG0	5
43#define R7S72100_CLK_SG1	4
44#define R7S72100_CLK_SG2	3
45#define R7S72100_CLK_SG3	2
46#define R7S72100_CLK_OSTM0	1
47#define R7S72100_CLK_OSTM1	0
48
49/* MSTP6 */
50#define R7S72100_CLK_ADC	7
51#define R7S72100_CLK_CEU	6
52#define R7S72100_CLK_DOC0	5
53#define R7S72100_CLK_DOC1	4
54#define R7S72100_CLK_DRC0	3
55#define R7S72100_CLK_DRC1	2
56#define R7S72100_CLK_JCU	1
57#define R7S72100_CLK_RTC	0
58
59/* MSTP7 */
60#define R7S72100_CLK_VDEC0	7
61#define R7S72100_CLK_VDEC1	6
62#define R7S72100_CLK_ETHER	4
63#define R7S72100_CLK_NAND	3
64#define R7S72100_CLK_USB0	1
65#define R7S72100_CLK_USB1	0
66
67/* MSTP8 */
68#define R7S72100_CLK_IMR0	7
69#define R7S72100_CLK_IMR1	6
70#define R7S72100_CLK_IMRDISP	5
71#define R7S72100_CLK_MMCIF	4
72#define R7S72100_CLK_MLB	3
73#define R7S72100_CLK_ETHAVB	2
74#define R7S72100_CLK_SCUX	1
75
76/* MSTP9 */
77#define R7S72100_CLK_I2C0	7
78#define R7S72100_CLK_I2C1	6
79#define R7S72100_CLK_I2C2	5
80#define R7S72100_CLK_I2C3	4
81#define R7S72100_CLK_SPIBSC0	3
82#define R7S72100_CLK_SPIBSC1	2
83#define R7S72100_CLK_VDC50	1	/* and LVDS */
84#define R7S72100_CLK_VDC51	0
85
86/* MSTP10 */
87#define R7S72100_CLK_SPI0	7
88#define R7S72100_CLK_SPI1	6
89#define R7S72100_CLK_SPI2	5
90#define R7S72100_CLK_SPI3	4
91#define R7S72100_CLK_SPI4	3
92#define R7S72100_CLK_CDROM	2
93#define R7S72100_CLK_SPDIF	1
94#define R7S72100_CLK_RGPVG2	0
95
96/* MSTP11 */
97#define R7S72100_CLK_SSI0	5
98#define R7S72100_CLK_SSI1	4
99#define R7S72100_CLK_SSI2	3
100#define R7S72100_CLK_SSI3	2
101#define R7S72100_CLK_SSI4	1
102#define R7S72100_CLK_SSI5	0
103
104/* MSTP12 */
105#define R7S72100_CLK_SDHI00	3
106#define R7S72100_CLK_SDHI01	2
107#define R7S72100_CLK_SDHI10	1
108#define R7S72100_CLK_SDHI11	0
109
110/* MSTP13 */
111#define R7S72100_CLK_PIX1	2
112#define R7S72100_CLK_PIX0	1
113
114#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
115