11.1Sjmcneill/* $NetBSD: r8a7744-cpg-mssr.h,v 1.1.1.1 2019/01/22 14:57:01 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: GPL-2.0 41.1Sjmcneill * 51.1Sjmcneill * Copyright (C) 2018 Renesas Electronics Corp. 61.1Sjmcneill */ 71.1Sjmcneill#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ 81.1Sjmcneill#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ 91.1Sjmcneill 101.1Sjmcneill#include <dt-bindings/clock/renesas-cpg-mssr.h> 111.1Sjmcneill 121.1Sjmcneill/* r8a7744 CPG Core Clocks */ 131.1Sjmcneill#define R8A7744_CLK_Z 0 141.1Sjmcneill#define R8A7744_CLK_ZG 1 151.1Sjmcneill#define R8A7744_CLK_ZTR 2 161.1Sjmcneill#define R8A7744_CLK_ZTRD2 3 171.1Sjmcneill#define R8A7744_CLK_ZT 4 181.1Sjmcneill#define R8A7744_CLK_ZX 5 191.1Sjmcneill#define R8A7744_CLK_ZS 6 201.1Sjmcneill#define R8A7744_CLK_HP 7 211.1Sjmcneill#define R8A7744_CLK_B 9 221.1Sjmcneill#define R8A7744_CLK_LB 10 231.1Sjmcneill#define R8A7744_CLK_P 11 241.1Sjmcneill#define R8A7744_CLK_CL 12 251.1Sjmcneill#define R8A7744_CLK_M2 13 261.1Sjmcneill#define R8A7744_CLK_ZB3 15 271.1Sjmcneill#define R8A7744_CLK_ZB3D2 16 281.1Sjmcneill#define R8A7744_CLK_DDR 17 291.1Sjmcneill#define R8A7744_CLK_SDH 18 301.1Sjmcneill#define R8A7744_CLK_SD0 19 311.1Sjmcneill#define R8A7744_CLK_SD2 20 321.1Sjmcneill#define R8A7744_CLK_SD3 21 331.1Sjmcneill#define R8A7744_CLK_MMC0 22 341.1Sjmcneill#define R8A7744_CLK_MP 23 351.1Sjmcneill#define R8A7744_CLK_QSPI 26 361.1Sjmcneill#define R8A7744_CLK_CP 27 371.1Sjmcneill#define R8A7744_CLK_RCAN 28 381.1Sjmcneill#define R8A7744_CLK_R 29 391.1Sjmcneill#define R8A7744_CLK_OSC 30 401.1Sjmcneill 411.1Sjmcneill#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */ 42