11.1Sjmcneill/* $NetBSD: r8a77470-cpg-mssr.h,v 1.1.1.1 2018/06/27 16:27:08 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: GPL-2.0 41.1Sjmcneill * 51.1Sjmcneill * Copyright (C) 2018 Renesas Electronics Corp. 61.1Sjmcneill */ 71.1Sjmcneill#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 81.1Sjmcneill#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 91.1Sjmcneill 101.1Sjmcneill#include <dt-bindings/clock/renesas-cpg-mssr.h> 111.1Sjmcneill 121.1Sjmcneill/* r8a77470 CPG Core Clocks */ 131.1Sjmcneill#define R8A77470_CLK_Z2 0 141.1Sjmcneill#define R8A77470_CLK_ZTR 1 151.1Sjmcneill#define R8A77470_CLK_ZTRD2 2 161.1Sjmcneill#define R8A77470_CLK_ZT 3 171.1Sjmcneill#define R8A77470_CLK_ZX 4 181.1Sjmcneill#define R8A77470_CLK_ZS 5 191.1Sjmcneill#define R8A77470_CLK_HP 6 201.1Sjmcneill#define R8A77470_CLK_B 7 211.1Sjmcneill#define R8A77470_CLK_LB 8 221.1Sjmcneill#define R8A77470_CLK_P 9 231.1Sjmcneill#define R8A77470_CLK_CL 10 241.1Sjmcneill#define R8A77470_CLK_CP 11 251.1Sjmcneill#define R8A77470_CLK_M2 12 261.1Sjmcneill#define R8A77470_CLK_ZB3 13 271.1Sjmcneill#define R8A77470_CLK_SDH 14 281.1Sjmcneill#define R8A77470_CLK_SD0 15 291.1Sjmcneill#define R8A77470_CLK_SD1 16 301.1Sjmcneill#define R8A77470_CLK_SD2 17 311.1Sjmcneill#define R8A77470_CLK_MP 18 321.1Sjmcneill#define R8A77470_CLK_QSPI 19 331.1Sjmcneill#define R8A77470_CLK_CPEX 20 341.1Sjmcneill#define R8A77470_CLK_RCAN 21 351.1Sjmcneill#define R8A77470_CLK_R 22 361.1Sjmcneill#define R8A77470_CLK_OSC 23 371.1Sjmcneill 381.1Sjmcneill#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */ 39