11.1Sjmcneill/* $NetBSD: r8a7792-cpg-mssr.h,v 1.1.1.2 2019/01/22 14:57:01 jmcneill Exp $ */ 21.1Sjmcneill 31.1.1.2Sjmcneill/* SPDX-License-Identifier: GPL-2.0+ 41.1Sjmcneill * 51.1.1.2Sjmcneill * Copyright (C) 2015 Renesas Electronics Corp. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 91.1Sjmcneill#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 101.1Sjmcneill 111.1Sjmcneill#include <dt-bindings/clock/renesas-cpg-mssr.h> 121.1Sjmcneill 131.1Sjmcneill/* r8a7792 CPG Core Clocks */ 141.1Sjmcneill#define R8A7792_CLK_Z 0 151.1Sjmcneill#define R8A7792_CLK_ZG 1 161.1Sjmcneill#define R8A7792_CLK_ZTR 2 171.1Sjmcneill#define R8A7792_CLK_ZTRD2 3 181.1Sjmcneill#define R8A7792_CLK_ZT 4 191.1Sjmcneill#define R8A7792_CLK_ZX 5 201.1Sjmcneill#define R8A7792_CLK_ZS 6 211.1Sjmcneill#define R8A7792_CLK_HP 7 221.1Sjmcneill#define R8A7792_CLK_I 8 231.1Sjmcneill#define R8A7792_CLK_B 9 241.1Sjmcneill#define R8A7792_CLK_LB 10 251.1Sjmcneill#define R8A7792_CLK_P 11 261.1Sjmcneill#define R8A7792_CLK_CL 12 271.1Sjmcneill#define R8A7792_CLK_M2 13 281.1Sjmcneill#define R8A7792_CLK_IMP 14 291.1Sjmcneill#define R8A7792_CLK_ZB3 15 301.1Sjmcneill#define R8A7792_CLK_ZB3D2 16 311.1Sjmcneill#define R8A7792_CLK_DDR 17 321.1Sjmcneill#define R8A7792_CLK_SD 18 331.1Sjmcneill#define R8A7792_CLK_MP 19 341.1Sjmcneill#define R8A7792_CLK_QSPI 20 351.1Sjmcneill#define R8A7792_CLK_CP 21 361.1Sjmcneill#define R8A7792_CLK_CPEX 22 371.1Sjmcneill#define R8A7792_CLK_RCAN 23 381.1Sjmcneill#define R8A7792_CLK_R 24 391.1Sjmcneill#define R8A7792_CLK_OSC 25 401.1Sjmcneill 411.1Sjmcneill#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ 42