11.1Sjmcneill/* $NetBSD: r8a77970-cpg-mssr.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $ */ 21.1Sjmcneill 31.1.1.2Sjmcneill/* SPDX-License-Identifier: GPL-2.0+ 41.1.1.2Sjmcneill * 51.1Sjmcneill * Copyright (C) 2016 Renesas Electronics Corp. 61.1Sjmcneill * Copyright (C) 2017 Cogent Embedded, Inc. 71.1Sjmcneill */ 81.1Sjmcneill#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 91.1Sjmcneill#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 101.1Sjmcneill 111.1Sjmcneill#include <dt-bindings/clock/renesas-cpg-mssr.h> 121.1Sjmcneill 131.1Sjmcneill/* r8a77970 CPG Core Clocks */ 141.1Sjmcneill#define R8A77970_CLK_Z2 0 151.1Sjmcneill#define R8A77970_CLK_ZR 1 161.1Sjmcneill#define R8A77970_CLK_ZTR 2 171.1Sjmcneill#define R8A77970_CLK_ZTRD2 3 181.1Sjmcneill#define R8A77970_CLK_ZT 4 191.1Sjmcneill#define R8A77970_CLK_ZX 5 201.1Sjmcneill#define R8A77970_CLK_S1D1 6 211.1Sjmcneill#define R8A77970_CLK_S1D2 7 221.1Sjmcneill#define R8A77970_CLK_S1D4 8 231.1Sjmcneill#define R8A77970_CLK_S2D1 9 241.1Sjmcneill#define R8A77970_CLK_S2D2 10 251.1Sjmcneill#define R8A77970_CLK_S2D4 11 261.1Sjmcneill#define R8A77970_CLK_LB 12 271.1Sjmcneill#define R8A77970_CLK_CL 13 281.1Sjmcneill#define R8A77970_CLK_ZB3 14 291.1Sjmcneill#define R8A77970_CLK_ZB3D2 15 301.1Sjmcneill#define R8A77970_CLK_DDR 16 311.1Sjmcneill#define R8A77970_CLK_CR 17 321.1Sjmcneill#define R8A77970_CLK_CRD2 18 331.1Sjmcneill#define R8A77970_CLK_SD0H 19 341.1Sjmcneill#define R8A77970_CLK_SD0 20 351.1Sjmcneill#define R8A77970_CLK_RPC 21 361.1Sjmcneill#define R8A77970_CLK_RPCD2 22 371.1Sjmcneill#define R8A77970_CLK_MSO 23 381.1Sjmcneill#define R8A77970_CLK_CANFD 24 391.1Sjmcneill#define R8A77970_CLK_CSI0 25 401.1Sjmcneill#define R8A77970_CLK_FRAY 26 411.1Sjmcneill#define R8A77970_CLK_CP 27 421.1Sjmcneill#define R8A77970_CLK_CPEX 28 431.1Sjmcneill#define R8A77970_CLK_R 29 441.1Sjmcneill#define R8A77970_CLK_OSC 30 451.1Sjmcneill 461.1Sjmcneill#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ 47