hisi,hi6220-resets.h revision 1.1.1.2
1/* $NetBSD: hisi,hi6220-resets.h,v 1.1.1.2 2017/11/30 19:40:51 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/** 5 * This header provides index for the reset controller 6 * based on hi6220 SoC. 7 */ 8#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 9#define _DT_BINDINGS_RESET_CONTROLLER_HI6220 10 11#define PERIPH_RSTDIS0_MMC0 0x000 12#define PERIPH_RSTDIS0_MMC1 0x001 13#define PERIPH_RSTDIS0_MMC2 0x002 14#define PERIPH_RSTDIS0_NANDC 0x003 15#define PERIPH_RSTDIS0_USBOTG_BUS 0x004 16#define PERIPH_RSTDIS0_POR_PICOPHY 0x005 17#define PERIPH_RSTDIS0_USBOTG 0x006 18#define PERIPH_RSTDIS0_USBOTG_32K 0x007 19#define PERIPH_RSTDIS1_HIFI 0x100 20#define PERIPH_RSTDIS1_DIGACODEC 0x105 21#define PERIPH_RSTEN2_IPF 0x200 22#define PERIPH_RSTEN2_SOCP 0x201 23#define PERIPH_RSTEN2_DMAC 0x202 24#define PERIPH_RSTEN2_SECENG 0x203 25#define PERIPH_RSTEN2_ABB 0x204 26#define PERIPH_RSTEN2_HPM0 0x205 27#define PERIPH_RSTEN2_HPM1 0x206 28#define PERIPH_RSTEN2_HPM2 0x207 29#define PERIPH_RSTEN2_HPM3 0x208 30#define PERIPH_RSTEN3_CSSYS 0x300 31#define PERIPH_RSTEN3_I2C0 0x301 32#define PERIPH_RSTEN3_I2C1 0x302 33#define PERIPH_RSTEN3_I2C2 0x303 34#define PERIPH_RSTEN3_I2C3 0x304 35#define PERIPH_RSTEN3_UART1 0x305 36#define PERIPH_RSTEN3_UART2 0x306 37#define PERIPH_RSTEN3_UART3 0x307 38#define PERIPH_RSTEN3_UART4 0x308 39#define PERIPH_RSTEN3_SSP 0x309 40#define PERIPH_RSTEN3_PWM 0x30a 41#define PERIPH_RSTEN3_BLPWM 0x30b 42#define PERIPH_RSTEN3_TSENSOR 0x30c 43#define PERIPH_RSTEN3_DAPB 0x312 44#define PERIPH_RSTEN3_HKADC 0x313 45#define PERIPH_RSTEN3_CODEC_SSI 0x314 46#define PERIPH_RSTEN3_PMUSSI1 0x316 47#define PERIPH_RSTEN8_RS0 0x400 48#define PERIPH_RSTEN8_RS2 0x401 49#define PERIPH_RSTEN8_RS3 0x402 50#define PERIPH_RSTEN8_MS0 0x403 51#define PERIPH_RSTEN8_MS2 0x405 52#define PERIPH_RSTEN8_XG2RAM0 0x406 53#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 54#define PERIPH_RSTEN8_SRAM 0x408 55#define PERIPH_RSTEN8_HARQ 0x40a 56#define PERIPH_RSTEN8_DDRC 0x40c 57#define PERIPH_RSTEN8_DDRC_APB 0x40d 58#define PERIPH_RSTEN8_DDRPACK_APB 0x40e 59#define PERIPH_RSTEN8_DDRT 0x411 60#define PERIPH_RSDIST9_CARM_DAP 0x500 61#define PERIPH_RSDIST9_CARM_ATB 0x501 62#define PERIPH_RSDIST9_CARM_LBUS 0x502 63#define PERIPH_RSDIST9_CARM_POR 0x503 64#define PERIPH_RSDIST9_CARM_CORE 0x504 65#define PERIPH_RSDIST9_CARM_DBG 0x505 66#define PERIPH_RSDIST9_CARM_L2 0x506 67#define PERIPH_RSDIST9_CARM_SOCDBG 0x507 68#define PERIPH_RSDIST9_CARM_ETM 0x508 69 70#define MEDIA_G3D 0 71#define MEDIA_CODEC_VPU 2 72#define MEDIA_CODEC_JPEG 3 73#define MEDIA_ISP 4 74#define MEDIA_ADE 5 75#define MEDIA_MMU 6 76#define MEDIA_XG2RAM1 7 77 78#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ 79