qcom,gcc-apq8084.h revision 1.1.1.1 
1/*	$NetBSD: qcom,gcc-apq8084.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $	*/
2
3/*
4 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H
17#define _DT_BINDINGS_RESET_APQ_GCC_8084_H
18
19#define GCC_SYSTEM_NOC_BCR		0
20#define GCC_CONFIG_NOC_BCR		1
21#define GCC_PERIPH_NOC_BCR		2
22#define GCC_IMEM_BCR			3
23#define GCC_MMSS_BCR			4
24#define GCC_QDSS_BCR			5
25#define GCC_USB_30_BCR			6
26#define GCC_USB3_PHY_BCR		7
27#define GCC_USB_HS_HSIC_BCR		8
28#define GCC_USB_HS_BCR			9
29#define GCC_USB2A_PHY_BCR		10
30#define GCC_USB2B_PHY_BCR		11
31#define GCC_SDCC1_BCR			12
32#define GCC_SDCC2_BCR			13
33#define GCC_SDCC3_BCR			14
34#define GCC_SDCC4_BCR			15
35#define GCC_BLSP1_BCR			16
36#define GCC_BLSP1_QUP1_BCR		17
37#define GCC_BLSP1_UART1_BCR		18
38#define GCC_BLSP1_QUP2_BCR		19
39#define GCC_BLSP1_UART2_BCR		20
40#define GCC_BLSP1_QUP3_BCR		21
41#define GCC_BLSP1_UART3_BCR		22
42#define GCC_BLSP1_QUP4_BCR		23
43#define GCC_BLSP1_UART4_BCR		24
44#define GCC_BLSP1_QUP5_BCR		25
45#define GCC_BLSP1_UART5_BCR		26
46#define GCC_BLSP1_QUP6_BCR		27
47#define GCC_BLSP1_UART6_BCR		28
48#define GCC_BLSP2_BCR			29
49#define GCC_BLSP2_QUP1_BCR		30
50#define GCC_BLSP2_UART1_BCR		31
51#define GCC_BLSP2_QUP2_BCR		32
52#define GCC_BLSP2_UART2_BCR		33
53#define GCC_BLSP2_QUP3_BCR		34
54#define GCC_BLSP2_UART3_BCR		35
55#define GCC_BLSP2_QUP4_BCR		36
56#define GCC_BLSP2_UART4_BCR		37
57#define GCC_BLSP2_QUP5_BCR		38
58#define GCC_BLSP2_UART5_BCR		39
59#define GCC_BLSP2_QUP6_BCR		40
60#define GCC_BLSP2_UART6_BCR		41
61#define GCC_PDM_BCR			42
62#define GCC_PRNG_BCR			43
63#define GCC_BAM_DMA_BCR			44
64#define GCC_TSIF_BCR			45
65#define GCC_TCSR_BCR			46
66#define GCC_BOOT_ROM_BCR		47
67#define GCC_MSG_RAM_BCR			48
68#define GCC_TLMM_BCR			49
69#define GCC_MPM_BCR			50
70#define GCC_MPM_AHB_RESET		51
71#define GCC_MPM_NON_AHB_RESET		52
72#define GCC_SEC_CTRL_BCR		53
73#define GCC_SPMI_BCR			54
74#define GCC_SPDM_BCR			55
75#define GCC_CE1_BCR			56
76#define GCC_CE2_BCR			57
77#define GCC_BIMC_BCR			58
78#define GCC_SNOC_BUS_TIMEOUT0_BCR	59
79#define GCC_SNOC_BUS_TIMEOUT2_BCR	60
80#define GCC_PNOC_BUS_TIMEOUT0_BCR	61
81#define GCC_PNOC_BUS_TIMEOUT1_BCR	62
82#define GCC_PNOC_BUS_TIMEOUT2_BCR	63
83#define GCC_PNOC_BUS_TIMEOUT3_BCR	64
84#define GCC_PNOC_BUS_TIMEOUT4_BCR	65
85#define GCC_CNOC_BUS_TIMEOUT0_BCR	66
86#define GCC_CNOC_BUS_TIMEOUT1_BCR	67
87#define GCC_CNOC_BUS_TIMEOUT2_BCR	68
88#define GCC_CNOC_BUS_TIMEOUT3_BCR	69
89#define GCC_CNOC_BUS_TIMEOUT4_BCR	70
90#define GCC_CNOC_BUS_TIMEOUT5_BCR	71
91#define GCC_CNOC_BUS_TIMEOUT6_BCR	72
92#define GCC_DEHR_BCR			73
93#define GCC_RBCPR_BCR			74
94#define GCC_MSS_RESTART			75
95#define GCC_LPASS_RESTART		76
96#define GCC_WCSS_RESTART		77
97#define GCC_VENUS_RESTART		78
98#define GCC_COPSS_SMMU_BCR		79
99#define GCC_SPSS_BCR			80
100#define GCC_PCIE_0_BCR			81
101#define GCC_PCIE_0_PHY_BCR		82
102#define GCC_PCIE_1_BCR			83
103#define GCC_PCIE_1_PHY_BCR		84
104#define GCC_USB_30_SEC_BCR		85
105#define GCC_USB3_SEC_PHY_BCR		86
106#define GCC_SATA_BCR			87
107#define GCC_CE3_BCR			88
108#define GCC_UFS_BCR			89
109#define GCC_USB30_PHY_COM_BCR		90
110
111#endif
112