11.1Sjmcneill/*	$NetBSD: qcom,gcc-ipq6018.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
21.1Sjmcneill
31.1Sjmcneill/* SPDX-License-Identifier: GPL-2.0 */
41.1Sjmcneill/*
51.1Sjmcneill * Copyright (c) 2018, The Linux Foundation. All rights reserved.
61.1Sjmcneill */
71.1Sjmcneill
81.1Sjmcneill#ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H
91.1Sjmcneill#define _DT_BINDINGS_RESET_IPQ_GCC_6018_H
101.1Sjmcneill
111.1Sjmcneill#define GCC_BLSP1_BCR				0
121.1Sjmcneill#define GCC_BLSP1_QUP1_BCR			1
131.1Sjmcneill#define GCC_BLSP1_UART1_BCR			2
141.1Sjmcneill#define GCC_BLSP1_QUP2_BCR			3
151.1Sjmcneill#define GCC_BLSP1_UART2_BCR			4
161.1Sjmcneill#define GCC_BLSP1_QUP3_BCR			5
171.1Sjmcneill#define GCC_BLSP1_UART3_BCR			6
181.1Sjmcneill#define GCC_BLSP1_QUP4_BCR			7
191.1Sjmcneill#define GCC_BLSP1_UART4_BCR			8
201.1Sjmcneill#define GCC_BLSP1_QUP5_BCR			9
211.1Sjmcneill#define GCC_BLSP1_UART5_BCR			10
221.1Sjmcneill#define GCC_BLSP1_QUP6_BCR			11
231.1Sjmcneill#define GCC_BLSP1_UART6_BCR			12
241.1Sjmcneill#define GCC_IMEM_BCR				13
251.1Sjmcneill#define GCC_SMMU_BCR				14
261.1Sjmcneill#define GCC_APSS_TCU_BCR			15
271.1Sjmcneill#define GCC_SMMU_XPU_BCR			16
281.1Sjmcneill#define GCC_PCNOC_TBU_BCR			17
291.1Sjmcneill#define GCC_SMMU_CFG_BCR			18
301.1Sjmcneill#define GCC_PRNG_BCR				19
311.1Sjmcneill#define GCC_BOOT_ROM_BCR			20
321.1Sjmcneill#define GCC_CRYPTO_BCR				21
331.1Sjmcneill#define GCC_WCSS_BCR				22
341.1Sjmcneill#define GCC_WCSS_Q6_BCR				23
351.1Sjmcneill#define GCC_NSS_BCR				24
361.1Sjmcneill#define GCC_SEC_CTRL_BCR			25
371.1Sjmcneill#define GCC_DDRSS_BCR				26
381.1Sjmcneill#define GCC_SYSTEM_NOC_BCR			27
391.1Sjmcneill#define GCC_PCNOC_BCR				28
401.1Sjmcneill#define GCC_TCSR_BCR				29
411.1Sjmcneill#define GCC_QDSS_BCR				30
421.1Sjmcneill#define GCC_DCD_BCR				31
431.1Sjmcneill#define GCC_MSG_RAM_BCR				32
441.1Sjmcneill#define GCC_MPM_BCR				33
451.1Sjmcneill#define GCC_SPDM_BCR				34
461.1Sjmcneill#define GCC_RBCPR_BCR				35
471.1Sjmcneill#define GCC_RBCPR_MX_BCR			36
481.1Sjmcneill#define GCC_TLMM_BCR				37
491.1Sjmcneill#define GCC_RBCPR_WCSS_BCR			38
501.1Sjmcneill#define GCC_USB0_PHY_BCR			39
511.1Sjmcneill#define GCC_USB3PHY_0_PHY_BCR			40
521.1Sjmcneill#define GCC_USB0_BCR				41
531.1Sjmcneill#define GCC_USB1_BCR				42
541.1Sjmcneill#define GCC_QUSB2_0_PHY_BCR			43
551.1Sjmcneill#define GCC_QUSB2_1_PHY_BCR			44
561.1Sjmcneill#define GCC_SDCC1_BCR				45
571.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT0_BCR		46
581.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT1_BCR		47
591.1Sjmcneill#define GCC_SNOC_BUS_TIMEOUT2_BCR		48
601.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT0_BCR		49
611.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT1_BCR		50
621.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT2_BCR		51
631.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT3_BCR		52
641.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT4_BCR		53
651.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT5_BCR		54
661.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT6_BCR		55
671.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT7_BCR		56
681.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT8_BCR		57
691.1Sjmcneill#define GCC_PCNOC_BUS_TIMEOUT9_BCR		58
701.1Sjmcneill#define GCC_UNIPHY0_BCR				59
711.1Sjmcneill#define GCC_UNIPHY1_BCR				60
721.1Sjmcneill#define GCC_CMN_12GPLL_BCR			61
731.1Sjmcneill#define GCC_QPIC_BCR				62
741.1Sjmcneill#define GCC_MDIO_BCR				63
751.1Sjmcneill#define GCC_WCSS_CORE_TBU_BCR			64
761.1Sjmcneill#define GCC_WCSS_Q6_TBU_BCR			65
771.1Sjmcneill#define GCC_USB0_TBU_BCR			66
781.1Sjmcneill#define GCC_PCIE0_TBU_BCR			67
791.1Sjmcneill#define GCC_PCIE0_BCR				68
801.1Sjmcneill#define GCC_PCIE0_PHY_BCR			69
811.1Sjmcneill#define GCC_PCIE0PHY_PHY_BCR			70
821.1Sjmcneill#define GCC_PCIE0_LINK_DOWN_BCR			71
831.1Sjmcneill#define GCC_DCC_BCR				72
841.1Sjmcneill#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	73
851.1Sjmcneill#define GCC_SMMU_CATS_BCR			74
861.1Sjmcneill#define GCC_UBI0_AXI_ARES			75
871.1Sjmcneill#define GCC_UBI0_AHB_ARES			76
881.1Sjmcneill#define GCC_UBI0_NC_AXI_ARES			77
891.1Sjmcneill#define GCC_UBI0_DBG_ARES			78
901.1Sjmcneill#define GCC_UBI0_CORE_CLAMP_ENABLE		79
911.1Sjmcneill#define GCC_UBI0_CLKRST_CLAMP_ENABLE		80
921.1Sjmcneill#define GCC_UBI0_UTCM_ARES			81
931.1Sjmcneill#define GCC_NSS_CFG_ARES			82
941.1Sjmcneill#define GCC_NSS_NOC_ARES			83
951.1Sjmcneill#define GCC_NSS_CRYPTO_ARES			84
961.1Sjmcneill#define GCC_NSS_CSR_ARES			85
971.1Sjmcneill#define GCC_NSS_CE_APB_ARES			86
981.1Sjmcneill#define GCC_NSS_CE_AXI_ARES			87
991.1Sjmcneill#define GCC_NSSNOC_CE_APB_ARES			88
1001.1Sjmcneill#define GCC_NSSNOC_CE_AXI_ARES			89
1011.1Sjmcneill#define GCC_NSSNOC_UBI0_AHB_ARES		90
1021.1Sjmcneill#define GCC_NSSNOC_SNOC_ARES			91
1031.1Sjmcneill#define GCC_NSSNOC_CRYPTO_ARES			92
1041.1Sjmcneill#define GCC_NSSNOC_ATB_ARES			93
1051.1Sjmcneill#define GCC_NSSNOC_QOSGEN_REF_ARES		94
1061.1Sjmcneill#define GCC_NSSNOC_TIMEOUT_REF_ARES		95
1071.1Sjmcneill#define GCC_PCIE0_PIPE_ARES			96
1081.1Sjmcneill#define GCC_PCIE0_SLEEP_ARES			97
1091.1Sjmcneill#define GCC_PCIE0_CORE_STICKY_ARES		98
1101.1Sjmcneill#define GCC_PCIE0_AXI_MASTER_ARES		99
1111.1Sjmcneill#define GCC_PCIE0_AXI_SLAVE_ARES		100
1121.1Sjmcneill#define GCC_PCIE0_AHB_ARES			101
1131.1Sjmcneill#define GCC_PCIE0_AXI_MASTER_STICKY_ARES	102
1141.1Sjmcneill#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		103
1151.1Sjmcneill#define GCC_PPE_FULL_RESET			104
1161.1Sjmcneill#define GCC_UNIPHY0_SOFT_RESET			105
1171.1Sjmcneill#define GCC_UNIPHY0_XPCS_RESET			106
1181.1Sjmcneill#define GCC_UNIPHY1_SOFT_RESET			107
1191.1Sjmcneill#define GCC_UNIPHY1_XPCS_RESET			108
1201.1Sjmcneill#define GCC_EDMA_HW_RESET			109
1211.1Sjmcneill#define GCC_ADSS_BCR				110
1221.1Sjmcneill#define GCC_NSS_NOC_TBU_BCR			111
1231.1Sjmcneill#define GCC_NSSPORT1_RESET			112
1241.1Sjmcneill#define GCC_NSSPORT2_RESET			113
1251.1Sjmcneill#define GCC_NSSPORT3_RESET			114
1261.1Sjmcneill#define GCC_NSSPORT4_RESET			115
1271.1Sjmcneill#define GCC_NSSPORT5_RESET			116
1281.1Sjmcneill#define GCC_UNIPHY0_PORT1_ARES			117
1291.1Sjmcneill#define GCC_UNIPHY0_PORT2_ARES			118
1301.1Sjmcneill#define GCC_UNIPHY0_PORT3_ARES			119
1311.1Sjmcneill#define GCC_UNIPHY0_PORT4_ARES			120
1321.1Sjmcneill#define GCC_UNIPHY0_PORT5_ARES			121
1331.1Sjmcneill#define GCC_UNIPHY0_PORT_4_5_RESET		122
1341.1Sjmcneill#define GCC_UNIPHY0_PORT_4_RESET		123
1351.1Sjmcneill#define GCC_LPASS_BCR				124
1361.1Sjmcneill#define GCC_UBI32_TBU_BCR			125
1371.1Sjmcneill#define GCC_LPASS_TBU_BCR			126
1381.1Sjmcneill#define GCC_WCSSAON_RESET			127
1391.1Sjmcneill#define GCC_LPASS_Q6_AXIM_ARES			128
1401.1Sjmcneill#define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES		129
1411.1Sjmcneill#define GCC_LPASS_Q6SS_TRIG_ARES		130
1421.1Sjmcneill#define GCC_LPASS_Q6_ATBM_AT_ARES		131
1431.1Sjmcneill#define GCC_LPASS_Q6_PCLKDBG_ARES		132
1441.1Sjmcneill#define GCC_LPASS_CORE_AXIM_ARES		133
1451.1Sjmcneill#define GCC_LPASS_SNOC_CFG_ARES			134
1461.1Sjmcneill#define GCC_WCSS_DBG_ARES			135
1471.1Sjmcneill#define GCC_WCSS_ECAHB_ARES			136
1481.1Sjmcneill#define GCC_WCSS_ACMT_ARES			137
1491.1Sjmcneill#define GCC_WCSS_DBG_BDG_ARES			138
1501.1Sjmcneill#define GCC_WCSS_AHB_S_ARES			139
1511.1Sjmcneill#define GCC_WCSS_AXI_M_ARES			140
1521.1Sjmcneill#define GCC_Q6SS_DBG_ARES			141
1531.1Sjmcneill#define GCC_Q6_AHB_S_ARES			142
1541.1Sjmcneill#define GCC_Q6_AHB_ARES				143
1551.1Sjmcneill#define GCC_Q6_AXIM2_ARES			144
1561.1Sjmcneill#define GCC_Q6_AXIM_ARES			145
1571.1Sjmcneill#define GCC_UBI0_CORE_ARES			146
1581.1Sjmcneill
1591.1Sjmcneill#endif
160