ah_internal.h revision 1.3.2.2
1 1.3.2.2 snj /* 2 1.3.2.2 snj * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 1.3.2.2 snj * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 1.3.2.2 snj * 5 1.3.2.2 snj * Permission to use, copy, modify, and/or distribute this software for any 6 1.3.2.2 snj * purpose with or without fee is hereby granted, provided that the above 7 1.3.2.2 snj * copyright notice and this permission notice appear in all copies. 8 1.3.2.2 snj * 9 1.3.2.2 snj * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 1.3.2.2 snj * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 1.3.2.2 snj * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 1.3.2.2 snj * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 1.3.2.2 snj * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 1.3.2.2 snj * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 1.3.2.2 snj * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 1.3.2.2 snj * 17 1.3.2.2 snj * $Id: ah_internal.h,v 1.3.2.2 2009/08/07 06:43:30 snj Exp $ 18 1.3.2.2 snj */ 19 1.3.2.2 snj #ifndef _ATH_AH_INTERAL_H_ 20 1.3.2.2 snj #define _ATH_AH_INTERAL_H_ 21 1.3.2.2 snj /* 22 1.3.2.2 snj * Atheros Device Hardware Access Layer (HAL). 23 1.3.2.2 snj * 24 1.3.2.2 snj * Internal definitions. 25 1.3.2.2 snj */ 26 1.3.2.2 snj #define AH_NULL 0 27 1.3.2.2 snj #define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28 1.3.2.2 snj #define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 1.3.2.2 snj 30 1.3.2.2 snj #ifndef NBBY 31 1.3.2.2 snj #define NBBY 8 /* number of bits/byte */ 32 1.3.2.2 snj #endif 33 1.3.2.2 snj 34 1.3.2.2 snj #ifndef roundup 35 1.3.2.2 snj #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 36 1.3.2.2 snj #endif 37 1.3.2.2 snj #ifndef howmany 38 1.3.2.2 snj #define howmany(x, y) (((x)+((y)-1))/(y)) 39 1.3.2.2 snj #endif 40 1.3.2.2 snj 41 1.3.2.2 snj #ifndef offsetof 42 1.3.2.2 snj #define offsetof(type, field) ((size_t)(&((type *)0)->field)) 43 1.3.2.2 snj #endif 44 1.3.2.2 snj 45 1.3.2.2 snj /* 46 1.3.2.2 snj * Remove const in a way that keeps the compiler happy. 47 1.3.2.2 snj * This works for gcc but may require other magic for 48 1.3.2.2 snj * other compilers (not sure where this should reside). 49 1.3.2.2 snj * Note that uintptr_t is C99. 50 1.3.2.2 snj */ 51 1.3.2.2 snj #ifndef __DECONST 52 1.3.2.2 snj #define __DECONST(type, var) ((type)(unsigned long)(const void *)(var)) 53 1.3.2.2 snj #endif 54 1.3.2.2 snj 55 1.3.2.2 snj typedef struct { 56 1.3.2.2 snj uint16_t start; /* first register */ 57 1.3.2.2 snj uint16_t end; /* ending register or zero */ 58 1.3.2.2 snj } HAL_REGRANGE; 59 1.3.2.2 snj 60 1.3.2.2 snj /* 61 1.3.2.2 snj * Transmit power scale factor. 62 1.3.2.2 snj * 63 1.3.2.2 snj * NB: This is not public because we want to discourage the use of 64 1.3.2.2 snj * scaling; folks should use the tx power limit interface. 65 1.3.2.2 snj */ 66 1.3.2.2 snj typedef enum { 67 1.3.2.2 snj HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 68 1.3.2.2 snj HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 69 1.3.2.2 snj HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 70 1.3.2.2 snj HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 71 1.3.2.2 snj HAL_TP_SCALE_MIN = 4, /* min, but still on */ 72 1.3.2.2 snj } HAL_TP_SCALE; 73 1.3.2.2 snj 74 1.3.2.2 snj typedef enum { 75 1.3.2.2 snj HAL_CAP_RADAR = 0, /* Radar capability */ 76 1.3.2.2 snj HAL_CAP_AR = 1, /* AR capability */ 77 1.3.2.2 snj } HAL_PHYDIAG_CAPS; 78 1.3.2.2 snj 79 1.3.2.2 snj /* 80 1.3.2.2 snj * Each chip or class of chips registers to offer support. 81 1.3.2.2 snj */ 82 1.3.2.2 snj struct ath_hal_chip { 83 1.3.2.2 snj const char *name; 84 1.3.2.2 snj const char *(*probe)(uint16_t vendorid, uint16_t devid); 85 1.3.2.2 snj struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 86 1.3.2.2 snj HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 87 1.3.2.2 snj }; 88 1.3.2.2 snj #ifndef AH_CHIP 89 1.3.2.2 snj #define AH_CHIP(_name, _probe, _attach) \ 90 1.3.2.2 snj static struct ath_hal_chip name##_chip = { \ 91 1.3.2.2 snj .name = #_name, \ 92 1.3.2.2 snj .probe = _probe, \ 93 1.3.2.2 snj .attach = _attach \ 94 1.3.2.2 snj }; \ 95 1.3.2.2 snj OS_DATA_SET(ah_chips, name##_chip) 96 1.3.2.2 snj #endif 97 1.3.2.2 snj 98 1.3.2.2 snj /* 99 1.3.2.2 snj * Each RF backend registers to offer support; this is mostly 100 1.3.2.2 snj * used by multi-chip 5212 solutions. Single-chip solutions 101 1.3.2.2 snj * have a fixed idea about which RF to use. 102 1.3.2.2 snj */ 103 1.3.2.2 snj struct ath_hal_rf { 104 1.3.2.2 snj const char *name; 105 1.3.2.2 snj HAL_BOOL (*probe)(struct ath_hal *ah); 106 1.3.2.2 snj HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 107 1.3.2.2 snj }; 108 1.3.2.2 snj #ifndef AH_RF 109 1.3.2.2 snj #define AH_RF(_name, _probe, _attach) \ 110 1.3.2.2 snj static struct ath_hal_rf _name##_rf = { \ 111 1.3.2.2 snj .name = __STRING(_name), \ 112 1.3.2.2 snj .probe = _probe, \ 113 1.3.2.2 snj .attach = _attach \ 114 1.3.2.2 snj }; \ 115 1.3.2.2 snj OS_DATA_SET(ah_rfs, _name##_rf) 116 1.3.2.2 snj #endif 117 1.3.2.2 snj 118 1.3.2.2 snj struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 119 1.3.2.2 snj 120 1.3.2.2 snj /* 121 1.3.2.2 snj * Internal form of a HAL_CHANNEL. Note that the structure 122 1.3.2.2 snj * must be defined such that you can cast references to a 123 1.3.2.2 snj * HAL_CHANNEL so don't shuffle the first two members. 124 1.3.2.2 snj */ 125 1.3.2.2 snj typedef struct { 126 1.3.2.2 snj uint32_t channelFlags; 127 1.3.2.2 snj uint16_t channel; /* NB: must be first for casting */ 128 1.3.2.2 snj uint8_t privFlags; 129 1.3.2.2 snj int8_t maxRegTxPower; 130 1.3.2.2 snj int8_t maxTxPower; 131 1.3.2.2 snj int8_t minTxPower; /* as above... */ 132 1.3.2.2 snj 133 1.3.2.2 snj HAL_BOOL bssSendHere; 134 1.3.2.2 snj uint8_t gainI; 135 1.3.2.2 snj HAL_BOOL iqCalValid; 136 1.3.2.2 snj uint8_t calValid; /* bitmask of cal types */ 137 1.3.2.2 snj int8_t iCoff; 138 1.3.2.2 snj int8_t qCoff; 139 1.3.2.2 snj int16_t rawNoiseFloor; 140 1.3.2.2 snj int16_t noiseFloorAdjust; 141 1.3.2.2 snj int8_t antennaMax; 142 1.3.2.2 snj uint32_t regDmnFlags; /* Flags for channel use in reg */ 143 1.3.2.2 snj uint32_t conformanceTestLimit; /* conformance test limit from reg domain */ 144 1.3.2.2 snj uint16_t mainSpur; /* cached spur value for this cahnnel */ 145 1.3.2.2 snj } HAL_CHANNEL_INTERNAL; 146 1.3.2.2 snj 147 1.3.2.2 snj typedef struct { 148 1.3.2.2 snj uint32_t halChanSpreadSupport : 1, 149 1.3.2.2 snj halSleepAfterBeaconBroken : 1, 150 1.3.2.2 snj halCompressSupport : 1, 151 1.3.2.2 snj halBurstSupport : 1, 152 1.3.2.2 snj halFastFramesSupport : 1, 153 1.3.2.2 snj halChapTuningSupport : 1, 154 1.3.2.2 snj halTurboGSupport : 1, 155 1.3.2.2 snj halTurboPrimeSupport : 1, 156 1.3.2.2 snj halMicAesCcmSupport : 1, 157 1.3.2.2 snj halMicCkipSupport : 1, 158 1.3.2.2 snj halMicTkipSupport : 1, 159 1.3.2.2 snj halTkipMicTxRxKeySupport : 1, 160 1.3.2.2 snj halCipherAesCcmSupport : 1, 161 1.3.2.2 snj halCipherCkipSupport : 1, 162 1.3.2.2 snj halCipherTkipSupport : 1, 163 1.3.2.2 snj halPSPollBroken : 1, 164 1.3.2.2 snj halVEOLSupport : 1, 165 1.3.2.2 snj halBssIdMaskSupport : 1, 166 1.3.2.2 snj halMcastKeySrchSupport : 1, 167 1.3.2.2 snj halTsfAddSupport : 1, 168 1.3.2.2 snj halChanHalfRate : 1, 169 1.3.2.2 snj halChanQuarterRate : 1, 170 1.3.2.2 snj halHTSupport : 1, 171 1.3.2.2 snj halRfSilentSupport : 1, 172 1.3.2.2 snj halHwPhyCounterSupport : 1, 173 1.3.2.2 snj halWowSupport : 1, 174 1.3.2.2 snj halWowMatchPatternExact : 1, 175 1.3.2.2 snj halAutoSleepSupport : 1, 176 1.3.2.2 snj halFastCCSupport : 1, 177 1.3.2.2 snj halBtCoexSupport : 1; 178 1.3.2.2 snj uint32_t halRxStbcSupport : 1, 179 1.3.2.2 snj halTxStbcSupport : 1, 180 1.3.2.2 snj halGTTSupport : 1, 181 1.3.2.2 snj halCSTSupport : 1, 182 1.3.2.2 snj halRifsRxSupport : 1, 183 1.3.2.2 snj halRifsTxSupport : 1, 184 1.3.2.2 snj halExtChanDfsSupport : 1, 185 1.3.2.2 snj halForcePpmSupport : 1, 186 1.3.2.2 snj halEnhancedPmSupport : 1, 187 1.3.2.2 snj halMbssidAggrSupport : 1; 188 1.3.2.2 snj uint32_t halWirelessModes; 189 1.3.2.2 snj uint16_t halTotalQueues; 190 1.3.2.2 snj uint16_t halKeyCacheSize; 191 1.3.2.2 snj uint16_t halLow5GhzChan, halHigh5GhzChan; 192 1.3.2.2 snj uint16_t halLow2GhzChan, halHigh2GhzChan; 193 1.3.2.2 snj int halTstampPrecision; 194 1.3.2.2 snj int halRtsAggrLimit; 195 1.3.2.2 snj uint8_t halTxChainMask; 196 1.3.2.2 snj uint8_t halRxChainMask; 197 1.3.2.2 snj uint8_t halNumGpioPins; 198 1.3.2.2 snj uint8_t halNumAntCfg2GHz; 199 1.3.2.2 snj uint8_t halNumAntCfg5GHz; 200 1.3.2.2 snj } HAL_CAPABILITIES; 201 1.3.2.2 snj 202 1.3.2.2 snj /* 203 1.3.2.2 snj * The ``private area'' follows immediately after the ``public area'' 204 1.3.2.2 snj * in the data structure returned by ath_hal_attach. Private data are 205 1.3.2.2 snj * used by device-independent code such as the regulatory domain support. 206 1.3.2.2 snj * In general, code within the HAL should never depend on data in the 207 1.3.2.2 snj * public area. Instead any public data needed internally should be 208 1.3.2.2 snj * shadowed here. 209 1.3.2.2 snj * 210 1.3.2.2 snj * When declaring a device-specific ath_hal data structure this structure 211 1.3.2.2 snj * is assumed to at the front; e.g. 212 1.3.2.2 snj * 213 1.3.2.2 snj * struct ath_hal_5212 { 214 1.3.2.2 snj * struct ath_hal_private ah_priv; 215 1.3.2.2 snj * ... 216 1.3.2.2 snj * }; 217 1.3.2.2 snj * 218 1.3.2.2 snj * It might be better to manage the method pointers in this structure 219 1.3.2.2 snj * using an indirect pointer to a read-only data structure but this would 220 1.3.2.2 snj * disallow class-style method overriding. 221 1.3.2.2 snj */ 222 1.3.2.2 snj struct ath_hal_private { 223 1.3.2.2 snj struct ath_hal h; /* public area */ 224 1.3.2.2 snj 225 1.3.2.2 snj /* NB: all methods go first to simplify initialization */ 226 1.3.2.2 snj HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 227 1.3.2.2 snj uint16_t channelFlags, 228 1.3.2.2 snj uint16_t *lowChannel, uint16_t *highChannel); 229 1.3.2.2 snj u_int (*ah_getWirelessModes)(struct ath_hal*); 230 1.3.2.2 snj HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 231 1.3.2.2 snj uint16_t *data); 232 1.3.2.2 snj HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 233 1.3.2.2 snj uint16_t data); 234 1.3.2.2 snj HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio); 235 1.3.2.2 snj HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 236 1.3.2.2 snj uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 237 1.3.2.2 snj HAL_BOOL (*ah_gpioSet)(struct ath_hal *, 238 1.3.2.2 snj uint32_t gpio, uint32_t val); 239 1.3.2.2 snj void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 240 1.3.2.2 snj HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 241 1.3.2.2 snj HAL_CHANNEL *, uint32_t); 242 1.3.2.2 snj int16_t (*ah_getNfAdjust)(struct ath_hal *, 243 1.3.2.2 snj const HAL_CHANNEL_INTERNAL*); 244 1.3.2.2 snj void (*ah_getNoiseFloor)(struct ath_hal *, 245 1.3.2.2 snj int16_t nfarray[]); 246 1.3.2.2 snj 247 1.3.2.2 snj void *ah_eeprom; /* opaque EEPROM state */ 248 1.3.2.2 snj uint16_t ah_eeversion; /* EEPROM version */ 249 1.3.2.2 snj void (*ah_eepromDetach)(struct ath_hal *); 250 1.3.2.2 snj HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 251 1.3.2.2 snj HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 252 1.3.2.2 snj uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 253 1.3.2.2 snj HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 254 1.3.2.2 snj const void *args, uint32_t argsize, 255 1.3.2.2 snj void **result, uint32_t *resultsize); 256 1.3.2.2 snj 257 1.3.2.2 snj /* 258 1.3.2.2 snj * Device revision information. 259 1.3.2.2 snj */ 260 1.3.2.2 snj uint16_t ah_devid; /* PCI device ID */ 261 1.3.2.2 snj uint16_t ah_subvendorid; /* PCI subvendor ID */ 262 1.3.2.2 snj uint32_t ah_macVersion; /* MAC version id */ 263 1.3.2.2 snj uint16_t ah_macRev; /* MAC revision */ 264 1.3.2.2 snj uint16_t ah_phyRev; /* PHY revision */ 265 1.3.2.2 snj uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 266 1.3.2.2 snj uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 267 1.3.2.2 snj 268 1.3.2.2 snj 269 1.3.2.2 snj HAL_OPMODE ah_opmode; /* operating mode from reset */ 270 1.3.2.2 snj HAL_CAPABILITIES ah_caps; /* device capabilities */ 271 1.3.2.2 snj uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 272 1.3.2.2 snj int16_t ah_powerLimit; /* tx power cap */ 273 1.3.2.2 snj uint16_t ah_maxPowerLevel; /* calculated max tx power */ 274 1.3.2.2 snj u_int ah_tpScale; /* tx power scale factor */ 275 1.3.2.2 snj uint32_t ah_11nCompat; /* 11n compat controls */ 276 1.3.2.2 snj 277 1.3.2.2 snj /* 278 1.3.2.2 snj * State for regulatory domain handling. 279 1.3.2.2 snj */ 280 1.3.2.2 snj HAL_REG_DOMAIN ah_currentRD; /* Current regulatory domain */ 281 1.3.2.2 snj HAL_CTRY_CODE ah_countryCode; /* current country code */ 282 1.3.2.2 snj HAL_CHANNEL_INTERNAL ah_channels[256]; /* calculated channel list */ 283 1.3.2.2 snj u_int ah_nchan; /* valid channels in list */ 284 1.3.2.2 snj HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */ 285 1.3.2.2 snj 286 1.3.2.2 snj uint8_t ah_coverageClass; /* coverage class */ 287 1.3.2.2 snj HAL_BOOL ah_regdomainUpdate; /* regdomain is updated? */ 288 1.3.2.2 snj /* 289 1.3.2.2 snj * RF Silent handling; setup according to the EEPROM. 290 1.3.2.2 snj */ 291 1.3.2.2 snj uint16_t ah_rfsilent; /* GPIO pin + polarity */ 292 1.3.2.2 snj HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 293 1.3.2.2 snj /* 294 1.3.2.2 snj * Diagnostic support for discriminating HIUERR reports. 295 1.3.2.2 snj */ 296 1.3.2.2 snj uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 297 1.3.2.2 snj int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 298 1.3.2.2 snj }; 299 1.3.2.2 snj 300 1.3.2.2 snj #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 301 1.3.2.2 snj 302 1.3.2.2 snj #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 303 1.3.2.2 snj AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 304 1.3.2.2 snj #define ath_hal_getWirelessModes(_ah) \ 305 1.3.2.2 snj AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 306 1.3.2.2 snj #define ath_hal_eepromRead(_ah, _off, _data) \ 307 1.3.2.2 snj AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 308 1.3.2.2 snj #define ath_hal_eepromWrite(_ah, _off, _data) \ 309 1.3.2.2 snj AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 310 1.3.2.2 snj #define ath_hal_gpioCfgOutput(_ah, _gpio) \ 311 1.3.2.2 snj AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio) 312 1.3.2.2 snj #define ath_hal_gpioCfgInput(_ah, _gpio) \ 313 1.3.2.2 snj AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio) 314 1.3.2.2 snj #define ath_hal_gpioGet(_ah, _gpio) \ 315 1.3.2.2 snj AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio) 316 1.3.2.2 snj #define ath_hal_gpioSet(_ah, _gpio, _val) \ 317 1.3.2.2 snj AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val) 318 1.3.2.2 snj #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 319 1.3.2.2 snj AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 320 1.3.2.2 snj #define ath_hal_getpowerlimits(_ah, _chans, _nchan) \ 321 1.3.2.2 snj AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan) 322 1.3.2.2 snj #define ath_hal_getNfAdjust(_ah, _c) \ 323 1.3.2.2 snj AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 324 1.3.2.2 snj #define ath_hal_getNoiseFloor(_ah, _nfArray) \ 325 1.3.2.2 snj AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 326 1.3.2.2 snj 327 1.3.2.2 snj #define ath_hal_eepromDetach(_ah) \ 328 1.3.2.2 snj AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 329 1.3.2.2 snj #define ath_hal_eepromGet(_ah, _param, _val) \ 330 1.3.2.2 snj AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 331 1.3.2.2 snj #define ath_hal_eepromSet(_ah, _param, _val) \ 332 1.3.2.2 snj AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 333 1.3.2.2 snj #define ath_hal_eepromGetFlag(_ah, _param) \ 334 1.3.2.2 snj (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 335 1.3.2.2 snj #define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 336 1.3.2.2 snj AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 337 1.3.2.2 snj #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 338 1.3.2.2 snj AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 339 1.3.2.2 snj 340 1.3.2.2 snj #if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_) 341 1.3.2.2 snj /* 342 1.3.2.2 snj * Stuff that would naturally come from _ieee80211.h 343 1.3.2.2 snj */ 344 1.3.2.2 snj #define IEEE80211_ADDR_LEN 6 345 1.3.2.2 snj 346 1.3.2.2 snj #define IEEE80211_WEP_KEYLEN 5 /* 40bit */ 347 1.3.2.2 snj #define IEEE80211_WEP_IVLEN 3 /* 24bit */ 348 1.3.2.2 snj #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 349 1.3.2.2 snj #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 350 1.3.2.2 snj 351 1.3.2.2 snj #define IEEE80211_CRC_LEN 4 352 1.3.2.2 snj 353 1.3.2.2 snj #define IEEE80211_MTU 1500 354 1.3.2.2 snj #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 355 1.3.2.2 snj (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 356 1.3.2.2 snj 357 1.3.2.2 snj enum { 358 1.3.2.2 snj IEEE80211_T_DS, /* direct sequence spread spectrum */ 359 1.3.2.2 snj IEEE80211_T_FH, /* frequency hopping */ 360 1.3.2.2 snj IEEE80211_T_OFDM, /* frequency division multiplexing */ 361 1.3.2.2 snj IEEE80211_T_TURBO, /* high rate DS */ 362 1.3.2.2 snj IEEE80211_T_HT, /* HT - full GI */ 363 1.3.2.2 snj }; 364 1.3.2.2 snj #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */ 365 1.3.2.2 snj #endif /* _NET_IF_IEEE80211_H_ */ 366 1.3.2.2 snj 367 1.3.2.2 snj /* NB: these are defined privately until XR support is announced */ 368 1.3.2.2 snj enum { 369 1.3.2.2 snj ATHEROS_T_XR = IEEE80211_T_HT+1, /* extended range */ 370 1.3.2.2 snj }; 371 1.3.2.2 snj 372 1.3.2.2 snj #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 373 1.3.2.2 snj 374 1.3.2.2 snj #define INIT_AIFS 2 375 1.3.2.2 snj #define INIT_CWMIN 15 376 1.3.2.2 snj #define INIT_CWMIN_11B 31 377 1.3.2.2 snj #define INIT_CWMAX 1023 378 1.3.2.2 snj #define INIT_SH_RETRY 10 379 1.3.2.2 snj #define INIT_LG_RETRY 10 380 1.3.2.2 snj #define INIT_SSH_RETRY 32 381 1.3.2.2 snj #define INIT_SLG_RETRY 32 382 1.3.2.2 snj 383 1.3.2.2 snj typedef struct { 384 1.3.2.2 snj uint32_t tqi_ver; /* HAL TXQ verson */ 385 1.3.2.2 snj HAL_TX_QUEUE tqi_type; /* hw queue type*/ 386 1.3.2.2 snj HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 387 1.3.2.2 snj HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 388 1.3.2.2 snj uint32_t tqi_priority; 389 1.3.2.2 snj uint32_t tqi_aifs; /* aifs */ 390 1.3.2.2 snj uint32_t tqi_cwmin; /* cwMin */ 391 1.3.2.2 snj uint32_t tqi_cwmax; /* cwMax */ 392 1.3.2.2 snj uint16_t tqi_shretry; /* frame short retry limit */ 393 1.3.2.2 snj uint16_t tqi_lgretry; /* frame long retry limit */ 394 1.3.2.2 snj uint32_t tqi_cbrPeriod; 395 1.3.2.2 snj uint32_t tqi_cbrOverflowLimit; 396 1.3.2.2 snj uint32_t tqi_burstTime; 397 1.3.2.2 snj uint32_t tqi_readyTime; 398 1.3.2.2 snj uint32_t tqi_physCompBuf; 399 1.3.2.2 snj uint32_t tqi_intFlags; /* flags for internal use */ 400 1.3.2.2 snj } HAL_TX_QUEUE_INFO; 401 1.3.2.2 snj 402 1.3.2.2 snj extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 403 1.3.2.2 snj HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 404 1.3.2.2 snj extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 405 1.3.2.2 snj HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 406 1.3.2.2 snj 407 1.3.2.2 snj typedef enum { 408 1.3.2.2 snj HAL_ANI_PRESENT, /* is ANI support present */ 409 1.3.2.2 snj HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 410 1.3.2.2 snj HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 411 1.3.2.2 snj HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 412 1.3.2.2 snj HAL_ANI_FIRSTEP_LEVEL, /* set level */ 413 1.3.2.2 snj HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 414 1.3.2.2 snj HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 415 1.3.2.2 snj HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 416 1.3.2.2 snj } HAL_ANI_CMD; 417 1.3.2.2 snj 418 1.3.2.2 snj #define HAL_SPUR_VAL_MASK 0x3FFF 419 1.3.2.2 snj #define HAL_SPUR_CHAN_WIDTH 87 420 1.3.2.2 snj #define HAL_BIN_WIDTH_BASE_100HZ 3125 421 1.3.2.2 snj #define HAL_BIN_WIDTH_TURBO_100HZ 6250 422 1.3.2.2 snj #define HAL_MAX_BINS_ALLOWED 28 423 1.3.2.2 snj 424 1.3.2.2 snj /* 425 1.3.2.2 snj * A = 5GHZ|OFDM 426 1.3.2.2 snj * T = 5GHZ|OFDM|TURBO 427 1.3.2.2 snj * 428 1.3.2.2 snj * IS_CHAN_A(T) will return TRUE. This is probably 429 1.3.2.2 snj * not the default behavior we want. We should migrate to a better mask -- 430 1.3.2.2 snj * perhaps CHANNEL_ALL. 431 1.3.2.2 snj * 432 1.3.2.2 snj * For now, IS_CHAN_G() masks itself with CHANNEL_108G. 433 1.3.2.2 snj * 434 1.3.2.2 snj */ 435 1.3.2.2 snj 436 1.3.2.2 snj #define IS_CHAN_A(_c) (((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) 437 1.3.2.2 snj #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B) 438 1.3.2.2 snj #define IS_CHAN_G(_c) (((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G) 439 1.3.2.2 snj #define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G) 440 1.3.2.2 snj #define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T) 441 1.3.2.2 snj #define IS_CHAN_PUREG(_c) \ 442 1.3.2.2 snj (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) 443 1.3.2.2 snj 444 1.3.2.2 snj #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0) 445 1.3.2.2 snj #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0) 446 1.3.2.2 snj #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 447 1.3.2.2 snj #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 448 1.3.2.2 snj #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 449 1.3.2.2 snj #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) 450 1.3.2.2 snj #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 451 1.3.2.2 snj #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 452 1.3.2.2 snj 453 1.3.2.2 snj #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 454 1.3.2.2 snj 455 1.3.2.2 snj #define CHANNEL_HT40 (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS) 456 1.3.2.2 snj #define CHANNEL_HT (CHANNEL_HT20 | CHANNEL_HT40) 457 1.3.2.2 snj #define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT) != 0) 458 1.3.2.2 snj #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20) 459 1.3.2.2 snj #define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0) 460 1.3.2.2 snj 461 1.3.2.2 snj /* 462 1.3.2.2 snj * Deduce if the host cpu has big- or litt-endian byte order. 463 1.3.2.2 snj */ 464 1.3.2.2 snj static __inline__ int 465 1.3.2.2 snj isBigEndian(void) 466 1.3.2.2 snj { 467 1.3.2.2 snj union { 468 1.3.2.2 snj int32_t i; 469 1.3.2.2 snj char c[4]; 470 1.3.2.2 snj } u; 471 1.3.2.2 snj u.i = 1; 472 1.3.2.2 snj return (u.c[0] == 0); 473 1.3.2.2 snj } 474 1.3.2.2 snj 475 1.3.2.2 snj /* unalligned little endian access */ 476 1.3.2.2 snj #define LE_READ_2(p) \ 477 1.3.2.2 snj ((uint16_t) \ 478 1.3.2.2 snj ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 479 1.3.2.2 snj #define LE_READ_4(p) \ 480 1.3.2.2 snj ((uint32_t) \ 481 1.3.2.2 snj ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 482 1.3.2.2 snj (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 483 1.3.2.2 snj 484 1.3.2.2 snj /* 485 1.3.2.2 snj * Register manipulation macros that expect bit field defines 486 1.3.2.2 snj * to follow the convention that an _S suffix is appended for 487 1.3.2.2 snj * a shift count, while the field mask has no suffix. 488 1.3.2.2 snj */ 489 1.3.2.2 snj #define SM(_v, _f) (((_v) << _f##_S) & (_f)) 490 1.3.2.2 snj #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 491 1.3.2.2 snj #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 492 1.3.2.2 snj OS_REG_WRITE(_a, _r, \ 493 1.3.2.2 snj (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 494 1.3.2.2 snj #define OS_REG_SET_BIT(_a, _r, _f) \ 495 1.3.2.2 snj OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 496 1.3.2.2 snj #define OS_REG_CLR_BIT(_a, _r, _f) \ 497 1.3.2.2 snj OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 498 1.3.2.2 snj 499 1.3.2.2 snj /* 500 1.3.2.2 snj * Regulatory domain support. 501 1.3.2.2 snj */ 502 1.3.2.2 snj 503 1.3.2.2 snj /* 504 1.3.2.2 snj * Return the max allowed antenna gain based on the current 505 1.3.2.2 snj * regulatory domain. 506 1.3.2.2 snj */ 507 1.3.2.2 snj extern u_int ath_hal_getantennareduction(struct ath_hal *, 508 1.3.2.2 snj HAL_CHANNEL *, u_int twiceGain); 509 1.3.2.2 snj /* 510 1.3.2.2 snj * Return the test group for the specific channel based on 511 1.3.2.2 snj * the current regulator domain. 512 1.3.2.2 snj */ 513 1.3.2.2 snj extern u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *); 514 1.3.2.2 snj /* 515 1.3.2.2 snj * Return whether or not a noise floor check is required 516 1.3.2.2 snj * based on the current regulatory domain for the specified 517 1.3.2.2 snj * channel. 518 1.3.2.2 snj */ 519 1.3.2.2 snj extern u_int ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *); 520 1.3.2.2 snj 521 1.3.2.2 snj /* 522 1.3.2.2 snj * Map a public channel definition to the corresponding 523 1.3.2.2 snj * internal data structure. This implicitly specifies 524 1.3.2.2 snj * whether or not the specified channel is ok to use 525 1.3.2.2 snj * based on the current regulatory domain constraints. 526 1.3.2.2 snj */ 527 1.3.2.2 snj extern HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 528 1.3.2.2 snj const HAL_CHANNEL *); 529 1.3.2.2 snj 530 1.3.2.2 snj /* system-configurable parameters */ 531 1.3.2.2 snj extern int ath_hal_dma_beacon_response_time; /* in TU's */ 532 1.3.2.2 snj extern int ath_hal_sw_beacon_response_time; /* in TU's */ 533 1.3.2.2 snj extern int ath_hal_additional_swba_backoff; /* in TU's */ 534 1.3.2.2 snj 535 1.3.2.2 snj /* wait for the register contents to have the specified value */ 536 1.3.2.2 snj extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 537 1.3.2.2 snj uint32_t mask, uint32_t val); 538 1.3.2.2 snj 539 1.3.2.2 snj /* return the first n bits in val reversed */ 540 1.3.2.2 snj extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 541 1.3.2.2 snj 542 1.3.2.2 snj /* printf interfaces */ 543 1.3.2.2 snj extern void ath_hal_printf(struct ath_hal *, const char*, ...); 544 1.3.2.2 snj extern void ath_hal_vprintf(struct ath_hal *, const char*, va_list); 545 1.3.2.2 snj extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 546 1.3.2.2 snj 547 1.3.2.2 snj /* allocate and free memory */ 548 1.3.2.2 snj extern void *ath_hal_malloc(size_t); 549 1.3.2.2 snj extern void ath_hal_free(void *); 550 1.3.2.2 snj 551 1.3.2.2 snj /* common debugging interfaces */ 552 1.3.2.2 snj #ifdef AH_DEBUG 553 1.3.2.2 snj #include "ah_debug.h" 554 1.3.2.2 snj extern int ath_hal_debug; 555 1.3.2.2 snj extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...); 556 1.3.2.2 snj #else 557 1.3.2.2 snj #define HALDEBUG(_ah, __m, _fmt, ...) 558 1.3.2.2 snj #endif /* AH_DEBUG */ 559 1.3.2.2 snj 560 1.3.2.2 snj /* 561 1.3.2.2 snj * Register logging definitions shared with ardecode. 562 1.3.2.2 snj */ 563 1.3.2.2 snj #include "ah_decode.h" 564 1.3.2.2 snj 565 1.3.2.2 snj /* 566 1.3.2.2 snj * Common assertion interface. Note: it is a bad idea to generate 567 1.3.2.2 snj * an assertion failure for any recoverable event. Instead catch 568 1.3.2.2 snj * the violation and, if possible, fix it up or recover from it; either 569 1.3.2.2 snj * with an error return value or a diagnostic messages. System software 570 1.3.2.2 snj * does not panic unless the situation is hopeless. 571 1.3.2.2 snj */ 572 1.3.2.2 snj #ifdef AH_ASSERT 573 1.3.2.2 snj extern void ath_hal_assert_failed(const char* filename, 574 1.3.2.2 snj int lineno, const char* msg); 575 1.3.2.2 snj 576 1.3.2.2 snj #define HALASSERT(_x) do { \ 577 1.3.2.2 snj if (!(_x)) { \ 578 1.3.2.2 snj ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 579 1.3.2.2 snj } \ 580 1.3.2.2 snj } while (0) 581 1.3.2.2 snj #else 582 1.3.2.2 snj #define HALASSERT(_x) 583 1.3.2.2 snj #endif /* AH_ASSERT */ 584 1.3.2.2 snj 585 1.3.2.2 snj /* 586 1.3.2.2 snj * Convert between microseconds and core system clocks. 587 1.3.2.2 snj */ 588 1.3.2.2 snj extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 589 1.3.2.2 snj extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 590 1.3.2.2 snj 591 1.3.2.2 snj /* 592 1.3.2.2 snj * Generic get/set capability support. Each chip overrides 593 1.3.2.2 snj * this routine to support chip-specific capabilities. 594 1.3.2.2 snj */ 595 1.3.2.2 snj extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 596 1.3.2.2 snj HAL_CAPABILITY_TYPE type, uint32_t capability, 597 1.3.2.2 snj uint32_t *result); 598 1.3.2.2 snj extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 599 1.3.2.2 snj HAL_CAPABILITY_TYPE type, uint32_t capability, 600 1.3.2.2 snj uint32_t setting, HAL_STATUS *status); 601 1.3.2.2 snj 602 1.3.2.2 snj /* 603 1.3.2.2 snj * Diagnostic interface. This is an open-ended interface that 604 1.3.2.2 snj * is opaque to applications. Diagnostic programs use this to 605 1.3.2.2 snj * retrieve internal data structures, etc. There is no guarantee 606 1.3.2.2 snj * that calling conventions for calls other than HAL_DIAG_REVS 607 1.3.2.2 snj * are stable between HAL releases; a diagnostic application must 608 1.3.2.2 snj * use the HAL revision information to deal with ABI/API differences. 609 1.3.2.2 snj * 610 1.3.2.2 snj * NB: do not renumber these, certain codes are publicly used. 611 1.3.2.2 snj */ 612 1.3.2.2 snj enum { 613 1.3.2.2 snj HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 614 1.3.2.2 snj HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 615 1.3.2.2 snj HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 616 1.3.2.2 snj HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 617 1.3.2.2 snj HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 618 1.3.2.2 snj HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 619 1.3.2.2 snj HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 620 1.3.2.2 snj HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 621 1.3.2.2 snj HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 622 1.3.2.2 snj HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 623 1.3.2.2 snj HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 624 1.3.2.2 snj HAL_DIAG_PCDAC = 11, /* PCDAC table */ 625 1.3.2.2 snj HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 626 1.3.2.2 snj HAL_DIAG_REGS = 13, /* Registers */ 627 1.3.2.2 snj HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 628 1.3.2.2 snj HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 629 1.3.2.2 snj HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 630 1.3.2.2 snj HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 631 1.3.2.2 snj HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 632 1.3.2.2 snj /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */ 633 1.3.2.2 snj HAL_DIAG_REGREAD = 24, /* Reg reads */ 634 1.3.2.2 snj HAL_DIAG_REGWRITE = 25, /* Reg writes */ 635 1.3.2.2 snj HAL_DIAG_GET_REGBASE = 26, /* Get register base */ 636 1.3.2.2 snj HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 637 1.3.2.2 snj HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 638 1.3.2.2 snj HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 639 1.3.2.2 snj HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 640 1.3.2.2 snj HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 641 1.3.2.2 snj HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 642 1.3.2.2 snj }; 643 1.3.2.2 snj 644 1.3.2.2 snj enum { 645 1.3.2.2 snj HAL_BB_HANG_DFS = 0x0001, 646 1.3.2.2 snj HAL_BB_HANG_RIFS = 0x0002, 647 1.3.2.2 snj HAL_BB_HANG_RX_CLEAR = 0x0004, 648 1.3.2.2 snj HAL_BB_HANG_UNKNOWN = 0x0080, 649 1.3.2.2 snj 650 1.3.2.2 snj HAL_MAC_HANG_SIG1 = 0x0100, 651 1.3.2.2 snj HAL_MAC_HANG_SIG2 = 0x0200, 652 1.3.2.2 snj HAL_MAC_HANG_UNKNOWN = 0x8000, 653 1.3.2.2 snj 654 1.3.2.2 snj HAL_BB_HANGS = HAL_BB_HANG_DFS 655 1.3.2.2 snj | HAL_BB_HANG_RIFS 656 1.3.2.2 snj | HAL_BB_HANG_RX_CLEAR 657 1.3.2.2 snj | HAL_BB_HANG_UNKNOWN, 658 1.3.2.2 snj HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 659 1.3.2.2 snj | HAL_MAC_HANG_SIG2 660 1.3.2.2 snj | HAL_MAC_HANG_UNKNOWN, 661 1.3.2.2 snj }; 662 1.3.2.2 snj 663 1.3.2.2 snj /* 664 1.3.2.2 snj * Device revision information. 665 1.3.2.2 snj */ 666 1.3.2.2 snj typedef struct { 667 1.3.2.2 snj uint16_t ah_devid; /* PCI device ID */ 668 1.3.2.2 snj uint16_t ah_subvendorid; /* PCI subvendor ID */ 669 1.3.2.2 snj uint32_t ah_macVersion; /* MAC version id */ 670 1.3.2.2 snj uint16_t ah_macRev; /* MAC revision */ 671 1.3.2.2 snj uint16_t ah_phyRev; /* PHY revision */ 672 1.3.2.2 snj uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 673 1.3.2.2 snj uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 674 1.3.2.2 snj } HAL_REVS; 675 1.3.2.2 snj 676 1.3.2.2 snj /* 677 1.3.2.2 snj * Argument payload for HAL_DIAG_SETKEY. 678 1.3.2.2 snj */ 679 1.3.2.2 snj typedef struct { 680 1.3.2.2 snj HAL_KEYVAL dk_keyval; 681 1.3.2.2 snj uint16_t dk_keyix; /* key index */ 682 1.3.2.2 snj uint8_t dk_mac[IEEE80211_ADDR_LEN]; 683 1.3.2.2 snj int dk_xor; /* XOR key data */ 684 1.3.2.2 snj } HAL_DIAG_KEYVAL; 685 1.3.2.2 snj 686 1.3.2.2 snj /* 687 1.3.2.2 snj * Argument payload for HAL_DIAG_EEWRITE. 688 1.3.2.2 snj */ 689 1.3.2.2 snj typedef struct { 690 1.3.2.2 snj uint16_t ee_off; /* eeprom offset */ 691 1.3.2.2 snj uint16_t ee_data; /* write data */ 692 1.3.2.2 snj } HAL_DIAG_EEVAL; 693 1.3.2.2 snj 694 1.3.2.2 snj 695 1.3.2.2 snj typedef struct { 696 1.3.2.2 snj u_int offset; /* reg offset */ 697 1.3.2.2 snj uint32_t val; /* reg value */ 698 1.3.2.2 snj } HAL_DIAG_REGVAL; 699 1.3.2.2 snj 700 1.3.2.2 snj /* 701 1.3.2.2 snj * 11n compatibility tweaks. 702 1.3.2.2 snj */ 703 1.3.2.2 snj #define HAL_DIAG_11N_SERVICES 0x00000003 704 1.3.2.2 snj #define HAL_DIAG_11N_SERVICES_S 0 705 1.3.2.2 snj #define HAL_DIAG_11N_TXSTOMP 0x0000000c 706 1.3.2.2 snj #define HAL_DIAG_11N_TXSTOMP_S 2 707 1.3.2.2 snj 708 1.3.2.2 snj typedef struct { 709 1.3.2.2 snj int maxNoiseImmunityLevel; /* [0..4] */ 710 1.3.2.2 snj int totalSizeDesired[5]; 711 1.3.2.2 snj int coarseHigh[5]; 712 1.3.2.2 snj int coarseLow[5]; 713 1.3.2.2 snj int firpwr[5]; 714 1.3.2.2 snj 715 1.3.2.2 snj int maxSpurImmunityLevel; /* [0..7] */ 716 1.3.2.2 snj int cycPwrThr1[8]; 717 1.3.2.2 snj 718 1.3.2.2 snj int maxFirstepLevel; /* [0..2] */ 719 1.3.2.2 snj int firstep[3]; 720 1.3.2.2 snj 721 1.3.2.2 snj uint32_t ofdmTrigHigh; 722 1.3.2.2 snj uint32_t ofdmTrigLow; 723 1.3.2.2 snj int32_t cckTrigHigh; 724 1.3.2.2 snj int32_t cckTrigLow; 725 1.3.2.2 snj int32_t rssiThrLow; 726 1.3.2.2 snj int32_t rssiThrHigh; 727 1.3.2.2 snj 728 1.3.2.2 snj int period; /* update listen period */ 729 1.3.2.2 snj } HAL_ANI_PARAMS; 730 1.3.2.2 snj 731 1.3.2.2 snj extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 732 1.3.2.2 snj const void *args, uint32_t argsize, 733 1.3.2.2 snj void **result, uint32_t *resultsize); 734 1.3.2.2 snj 735 1.3.2.2 snj /* 736 1.3.2.2 snj * Setup a h/w rate table for use. 737 1.3.2.2 snj */ 738 1.3.2.2 snj extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 739 1.3.2.2 snj 740 1.3.2.2 snj /* 741 1.3.2.2 snj * Common routine for implementing getChanNoise api. 742 1.3.2.2 snj */ 743 1.3.2.2 snj extern int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan); 744 1.3.2.2 snj 745 1.3.2.2 snj /* 746 1.3.2.2 snj * Initialization support. 747 1.3.2.2 snj */ 748 1.3.2.2 snj typedef struct { 749 1.3.2.2 snj const uint32_t *data; 750 1.3.2.2 snj int rows, cols; 751 1.3.2.2 snj } HAL_INI_ARRAY; 752 1.3.2.2 snj 753 1.3.2.2 snj #define HAL_INI_INIT(_ia, _data, _cols) do { \ 754 1.3.2.2 snj (_ia)->data = (const uint32_t *)(_data); \ 755 1.3.2.2 snj (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 756 1.3.2.2 snj (_ia)->cols = (_cols); \ 757 1.3.2.2 snj } while (0) 758 1.3.2.2 snj #define HAL_INI_VAL(_ia, _r, _c) \ 759 1.3.2.2 snj ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 760 1.3.2.2 snj 761 1.3.2.2 snj /* 762 1.3.2.2 snj * OS_DELAY() does a PIO READ on the PCI bus which allows 763 1.3.2.2 snj * other cards' DMA reads to complete in the middle of our reset. 764 1.3.2.2 snj */ 765 1.3.2.2 snj #define DMA_YIELD(x) do { \ 766 1.3.2.2 snj if ((++(x) % 64) == 0) \ 767 1.3.2.2 snj OS_DELAY(1); \ 768 1.3.2.2 snj } while (0) 769 1.3.2.2 snj 770 1.3.2.2 snj #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 771 1.3.2.2 snj int r; \ 772 1.3.2.2 snj for (r = 0; r < N(regArray); r++) { \ 773 1.3.2.2 snj OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 774 1.3.2.2 snj DMA_YIELD(regWr); \ 775 1.3.2.2 snj } \ 776 1.3.2.2 snj } while (0) 777 1.3.2.2 snj 778 1.3.2.2 snj #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 779 1.3.2.2 snj int r; \ 780 1.3.2.2 snj for (r = 0; r < N(regArray); r++) { \ 781 1.3.2.2 snj OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 782 1.3.2.2 snj DMA_YIELD(regWr); \ 783 1.3.2.2 snj } \ 784 1.3.2.2 snj } while (0) 785 1.3.2.2 snj 786 1.3.2.2 snj extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 787 1.3.2.2 snj int col, int regWr); 788 1.3.2.2 snj extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 789 1.3.2.2 snj int col); 790 1.3.2.2 snj extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 791 1.3.2.2 snj const uint32_t data[], int regWr); 792 1.3.2.2 snj 793 1.3.2.2 snj #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 794 1.3.2.2 snj #endif /* _ATH_AH_INTERAL_H_ */ 795
Indexes created Sun Nov 02 07:10:05 GMT 2025