ah_regdomain.c revision 1.2.2.2
1 1.2.2.2 mjf /* 2 1.2.2.2 mjf * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 1.2.2.2 mjf * Copyright (c) 2005-2006 Atheros Communications, Inc. 4 1.2.2.2 mjf * All rights reserved. 5 1.2.2.2 mjf * 6 1.2.2.2 mjf * Permission to use, copy, modify, and/or distribute this software for any 7 1.2.2.2 mjf * purpose with or without fee is hereby granted, provided that the above 8 1.2.2.2 mjf * copyright notice and this permission notice appear in all copies. 9 1.2.2.2 mjf * 10 1.2.2.2 mjf * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 1.2.2.2 mjf * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 1.2.2.2 mjf * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 1.2.2.2 mjf * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 1.2.2.2 mjf * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 1.2.2.2 mjf * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 1.2.2.2 mjf * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 1.2.2.2 mjf * 18 1.2.2.2 mjf * $Id: ah_regdomain.c,v 1.2.2.2 2009/01/17 13:29:11 mjf Exp $ 19 1.2.2.2 mjf */ 20 1.2.2.2 mjf #include "opt_ah.h" 21 1.2.2.2 mjf 22 1.2.2.2 mjf #include "ah.h" 23 1.2.2.2 mjf #include "ah_internal.h" 24 1.2.2.2 mjf #include "ah_eeprom.h" 25 1.2.2.2 mjf #include "ah_devid.h" 26 1.2.2.2 mjf 27 1.2.2.2 mjf /* 28 1.2.2.2 mjf * XXX this code needs a audit+review 29 1.2.2.2 mjf */ 30 1.2.2.2 mjf 31 1.2.2.2 mjf /* used throughout this file... */ 32 1.2.2.2 mjf #define N(a) (sizeof (a) / sizeof (a[0])) 33 1.2.2.2 mjf 34 1.2.2.2 mjf #define HAL_MODE_11A_TURBO HAL_MODE_108A 35 1.2.2.2 mjf #define HAL_MODE_11G_TURBO HAL_MODE_108G 36 1.2.2.2 mjf 37 1.2.2.2 mjf /* 10MHz is half the 11A bandwidth used to determine upper edge freq 38 1.2.2.2 mjf of the outdoor channel */ 39 1.2.2.2 mjf #define HALF_MAXCHANBW 10 40 1.2.2.2 mjf 41 1.2.2.2 mjf /* 42 1.2.2.2 mjf * BMLEN defines the size of the bitmask used to hold frequency 43 1.2.2.2 mjf * band specifications. Note this must agree with the BM macro 44 1.2.2.2 mjf * definition that's used to setup initializers. See also further 45 1.2.2.2 mjf * comments below. 46 1.2.2.2 mjf */ 47 1.2.2.2 mjf #define BMLEN 2 /* 2 x 64 bits in each channel bitmask */ 48 1.2.2.2 mjf typedef uint64_t chanbmask_t[BMLEN]; 49 1.2.2.2 mjf 50 1.2.2.2 mjf #define W0(_a) \ 51 1.2.2.2 mjf (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0)) 52 1.2.2.2 mjf #define W1(_a) \ 53 1.2.2.2 mjf (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0)) 54 1.2.2.2 mjf #define BM1(_fa) { W0(_fa), W1(_fa) } 55 1.2.2.2 mjf #define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) } 56 1.2.2.2 mjf #define BM3(_fa, _fb, _fc) \ 57 1.2.2.2 mjf { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) } 58 1.2.2.2 mjf #define BM4(_fa, _fb, _fc, _fd) \ 59 1.2.2.2 mjf { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \ 60 1.2.2.2 mjf W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) } 61 1.2.2.2 mjf #define BM5(_fa, _fb, _fc, _fd, _fe) \ 62 1.2.2.2 mjf { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \ 63 1.2.2.2 mjf W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) } 64 1.2.2.2 mjf #define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \ 65 1.2.2.2 mjf { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \ 66 1.2.2.2 mjf W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) } 67 1.2.2.2 mjf #define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \ 68 1.2.2.2 mjf { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 69 1.2.2.2 mjf W0(_fg),\ 70 1.2.2.2 mjf W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 71 1.2.2.2 mjf W1(_fg) } 72 1.2.2.2 mjf #define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ 73 1.2.2.2 mjf { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 74 1.2.2.2 mjf W0(_fg) | W0(_fh) , \ 75 1.2.2.2 mjf W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 76 1.2.2.2 mjf W1(_fg) | W1(_fh) } 77 1.2.2.2 mjf 78 1.2.2.2 mjf /* 79 1.2.2.2 mjf * Country/Region Codes 80 1.2.2.2 mjf * Numbering from ISO 3166 81 1.2.2.2 mjf */ 82 1.2.2.2 mjf enum { 83 1.2.2.2 mjf CTRY_ALBANIA = 8, /* Albania */ 84 1.2.2.2 mjf CTRY_ALGERIA = 12, /* Algeria */ 85 1.2.2.2 mjf CTRY_ARGENTINA = 32, /* Argentina */ 86 1.2.2.2 mjf CTRY_ARMENIA = 51, /* Armenia */ 87 1.2.2.2 mjf CTRY_AUSTRALIA = 36, /* Australia */ 88 1.2.2.2 mjf CTRY_AUSTRIA = 40, /* Austria */ 89 1.2.2.2 mjf CTRY_AZERBAIJAN = 31, /* Azerbaijan */ 90 1.2.2.2 mjf CTRY_BAHRAIN = 48, /* Bahrain */ 91 1.2.2.2 mjf CTRY_BELARUS = 112, /* Belarus */ 92 1.2.2.2 mjf CTRY_BELGIUM = 56, /* Belgium */ 93 1.2.2.2 mjf CTRY_BELIZE = 84, /* Belize */ 94 1.2.2.2 mjf CTRY_BOLIVIA = 68, /* Bolivia */ 95 1.2.2.2 mjf CTRY_BRAZIL = 76, /* Brazil */ 96 1.2.2.2 mjf CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ 97 1.2.2.2 mjf CTRY_BULGARIA = 100, /* Bulgaria */ 98 1.2.2.2 mjf CTRY_CANADA = 124, /* Canada */ 99 1.2.2.2 mjf CTRY_CHILE = 152, /* Chile */ 100 1.2.2.2 mjf CTRY_CHINA = 156, /* People's Republic of China */ 101 1.2.2.2 mjf CTRY_COLOMBIA = 170, /* Colombia */ 102 1.2.2.2 mjf CTRY_COSTA_RICA = 188, /* Costa Rica */ 103 1.2.2.2 mjf CTRY_CROATIA = 191, /* Croatia */ 104 1.2.2.2 mjf CTRY_CYPRUS = 196, 105 1.2.2.2 mjf CTRY_CZECH = 203, /* Czech Republic */ 106 1.2.2.2 mjf CTRY_DENMARK = 208, /* Denmark */ 107 1.2.2.2 mjf CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ 108 1.2.2.2 mjf CTRY_ECUADOR = 218, /* Ecuador */ 109 1.2.2.2 mjf CTRY_EGYPT = 818, /* Egypt */ 110 1.2.2.2 mjf CTRY_EL_SALVADOR = 222, /* El Salvador */ 111 1.2.2.2 mjf CTRY_ESTONIA = 233, /* Estonia */ 112 1.2.2.2 mjf CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ 113 1.2.2.2 mjf CTRY_FINLAND = 246, /* Finland */ 114 1.2.2.2 mjf CTRY_FRANCE = 250, /* France */ 115 1.2.2.2 mjf CTRY_FRANCE2 = 255, /* France2 */ 116 1.2.2.2 mjf CTRY_GEORGIA = 268, /* Georgia */ 117 1.2.2.2 mjf CTRY_GERMANY = 276, /* Germany */ 118 1.2.2.2 mjf CTRY_GREECE = 300, /* Greece */ 119 1.2.2.2 mjf CTRY_GUATEMALA = 320, /* Guatemala */ 120 1.2.2.2 mjf CTRY_HONDURAS = 340, /* Honduras */ 121 1.2.2.2 mjf CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ 122 1.2.2.2 mjf CTRY_HUNGARY = 348, /* Hungary */ 123 1.2.2.2 mjf CTRY_ICELAND = 352, /* Iceland */ 124 1.2.2.2 mjf CTRY_INDIA = 356, /* India */ 125 1.2.2.2 mjf CTRY_INDONESIA = 360, /* Indonesia */ 126 1.2.2.2 mjf CTRY_IRAN = 364, /* Iran */ 127 1.2.2.2 mjf CTRY_IRAQ = 368, /* Iraq */ 128 1.2.2.2 mjf CTRY_IRELAND = 372, /* Ireland */ 129 1.2.2.2 mjf CTRY_ISRAEL = 376, /* Israel */ 130 1.2.2.2 mjf CTRY_ITALY = 380, /* Italy */ 131 1.2.2.2 mjf CTRY_JAMAICA = 388, /* Jamaica */ 132 1.2.2.2 mjf CTRY_JAPAN = 392, /* Japan */ 133 1.2.2.2 mjf CTRY_JAPAN1 = 393, /* Japan (JP1) */ 134 1.2.2.2 mjf CTRY_JAPAN2 = 394, /* Japan (JP0) */ 135 1.2.2.2 mjf CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ 136 1.2.2.2 mjf CTRY_JAPAN4 = 396, /* Japan (JE1) */ 137 1.2.2.2 mjf CTRY_JAPAN5 = 397, /* Japan (JE2) */ 138 1.2.2.2 mjf CTRY_JAPAN6 = 399, /* Japan (JP6) */ 139 1.2.2.2 mjf 140 1.2.2.2 mjf CTRY_JAPAN7 = 4007, /* Japan (J7) */ 141 1.2.2.2 mjf CTRY_JAPAN8 = 4008, /* Japan (J8) */ 142 1.2.2.2 mjf CTRY_JAPAN9 = 4009, /* Japan (J9) */ 143 1.2.2.2 mjf 144 1.2.2.2 mjf CTRY_JAPAN10 = 4010, /* Japan (J10) */ 145 1.2.2.2 mjf CTRY_JAPAN11 = 4011, /* Japan (J11) */ 146 1.2.2.2 mjf CTRY_JAPAN12 = 4012, /* Japan (J12) */ 147 1.2.2.2 mjf 148 1.2.2.2 mjf CTRY_JAPAN13 = 4013, /* Japan (J13) */ 149 1.2.2.2 mjf CTRY_JAPAN14 = 4014, /* Japan (J14) */ 150 1.2.2.2 mjf CTRY_JAPAN15 = 4015, /* Japan (J15) */ 151 1.2.2.2 mjf 152 1.2.2.2 mjf CTRY_JAPAN16 = 4016, /* Japan (J16) */ 153 1.2.2.2 mjf CTRY_JAPAN17 = 4017, /* Japan (J17) */ 154 1.2.2.2 mjf CTRY_JAPAN18 = 4018, /* Japan (J18) */ 155 1.2.2.2 mjf 156 1.2.2.2 mjf CTRY_JAPAN19 = 4019, /* Japan (J19) */ 157 1.2.2.2 mjf CTRY_JAPAN20 = 4020, /* Japan (J20) */ 158 1.2.2.2 mjf CTRY_JAPAN21 = 4021, /* Japan (J21) */ 159 1.2.2.2 mjf 160 1.2.2.2 mjf CTRY_JAPAN22 = 4022, /* Japan (J22) */ 161 1.2.2.2 mjf CTRY_JAPAN23 = 4023, /* Japan (J23) */ 162 1.2.2.2 mjf CTRY_JAPAN24 = 4024, /* Japan (J24) */ 163 1.2.2.2 mjf 164 1.2.2.2 mjf CTRY_JORDAN = 400, /* Jordan */ 165 1.2.2.2 mjf CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ 166 1.2.2.2 mjf CTRY_KENYA = 404, /* Kenya */ 167 1.2.2.2 mjf CTRY_KOREA_NORTH = 408, /* North Korea */ 168 1.2.2.2 mjf CTRY_KOREA_ROC = 410, /* South Korea */ 169 1.2.2.2 mjf CTRY_KOREA_ROC2 = 411, /* South Korea */ 170 1.2.2.2 mjf CTRY_KOREA_ROC3 = 412, /* South Korea */ 171 1.2.2.2 mjf CTRY_KUWAIT = 414, /* Kuwait */ 172 1.2.2.2 mjf CTRY_LATVIA = 428, /* Latvia */ 173 1.2.2.2 mjf CTRY_LEBANON = 422, /* Lebanon */ 174 1.2.2.2 mjf CTRY_LIBYA = 434, /* Libya */ 175 1.2.2.2 mjf CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ 176 1.2.2.2 mjf CTRY_LITHUANIA = 440, /* Lithuania */ 177 1.2.2.2 mjf CTRY_LUXEMBOURG = 442, /* Luxembourg */ 178 1.2.2.2 mjf CTRY_MACAU = 446, /* Macau */ 179 1.2.2.2 mjf CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */ 180 1.2.2.2 mjf CTRY_MALAYSIA = 458, /* Malaysia */ 181 1.2.2.2 mjf CTRY_MALTA = 470, /* Malta */ 182 1.2.2.2 mjf CTRY_MEXICO = 484, /* Mexico */ 183 1.2.2.2 mjf CTRY_MONACO = 492, /* Principality of Monaco */ 184 1.2.2.2 mjf CTRY_MOROCCO = 504, /* Morocco */ 185 1.2.2.2 mjf CTRY_NETHERLANDS = 528, /* Netherlands */ 186 1.2.2.2 mjf CTRY_NEW_ZEALAND = 554, /* New Zealand */ 187 1.2.2.2 mjf CTRY_NICARAGUA = 558, /* Nicaragua */ 188 1.2.2.2 mjf CTRY_NORWAY = 578, /* Norway */ 189 1.2.2.2 mjf CTRY_OMAN = 512, /* Oman */ 190 1.2.2.2 mjf CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ 191 1.2.2.2 mjf CTRY_PANAMA = 591, /* Panama */ 192 1.2.2.2 mjf CTRY_PARAGUAY = 600, /* Paraguay */ 193 1.2.2.2 mjf CTRY_PERU = 604, /* Peru */ 194 1.2.2.2 mjf CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ 195 1.2.2.2 mjf CTRY_POLAND = 616, /* Poland */ 196 1.2.2.2 mjf CTRY_PORTUGAL = 620, /* Portugal */ 197 1.2.2.2 mjf CTRY_PUERTO_RICO = 630, /* Puerto Rico */ 198 1.2.2.2 mjf CTRY_QATAR = 634, /* Qatar */ 199 1.2.2.2 mjf CTRY_ROMANIA = 642, /* Romania */ 200 1.2.2.2 mjf CTRY_RUSSIA = 643, /* Russia */ 201 1.2.2.2 mjf CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ 202 1.2.2.2 mjf CTRY_SINGAPORE = 702, /* Singapore */ 203 1.2.2.2 mjf CTRY_SLOVAKIA = 703, /* Slovak Republic */ 204 1.2.2.2 mjf CTRY_SLOVENIA = 705, /* Slovenia */ 205 1.2.2.2 mjf CTRY_SOUTH_AFRICA = 710, /* South Africa */ 206 1.2.2.2 mjf CTRY_SPAIN = 724, /* Spain */ 207 1.2.2.2 mjf CTRY_SR9 = 5000, /* Ubiquiti SR9 (900MHz/GSM) */ 208 1.2.2.2 mjf CTRY_SWEDEN = 752, /* Sweden */ 209 1.2.2.2 mjf CTRY_SWITZERLAND = 756, /* Switzerland */ 210 1.2.2.2 mjf CTRY_SYRIA = 760, /* Syria */ 211 1.2.2.2 mjf CTRY_TAIWAN = 158, /* Taiwan */ 212 1.2.2.2 mjf CTRY_THAILAND = 764, /* Thailand */ 213 1.2.2.2 mjf CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ 214 1.2.2.2 mjf CTRY_TUNISIA = 788, /* Tunisia */ 215 1.2.2.2 mjf CTRY_TURKEY = 792, /* Turkey */ 216 1.2.2.2 mjf CTRY_UAE = 784, /* U.A.E. */ 217 1.2.2.2 mjf CTRY_UKRAINE = 804, /* Ukraine */ 218 1.2.2.2 mjf CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ 219 1.2.2.2 mjf CTRY_UNITED_STATES = 840, /* United States */ 220 1.2.2.2 mjf CTRY_UNITED_STATES_FCC49 = 842, /* United States (Public Safety)*/ 221 1.2.2.2 mjf CTRY_URUGUAY = 858, /* Uruguay */ 222 1.2.2.2 mjf CTRY_UZBEKISTAN = 860, /* Uzbekistan */ 223 1.2.2.2 mjf CTRY_VENEZUELA = 862, /* Venezuela */ 224 1.2.2.2 mjf CTRY_VIET_NAM = 704, /* Viet Nam */ 225 1.2.2.2 mjf CTRY_XR9 = 5001, /* Ubiquiti XR9 (900MHz/GSM) */ 226 1.2.2.2 mjf CTRY_GZ901 = 5002, /* Zcomax GZ-901 (900MHz/GSM) */ 227 1.2.2.2 mjf CTRY_YEMEN = 887, /* Yemen */ 228 1.2.2.2 mjf CTRY_ZIMBABWE = 716 /* Zimbabwe */ 229 1.2.2.2 mjf }; 230 1.2.2.2 mjf 231 1.2.2.2 mjf 232 1.2.2.2 mjf /* 233 1.2.2.2 mjf * Mask to check whether a domain is a multidomain or a single domain 234 1.2.2.2 mjf */ 235 1.2.2.2 mjf #define MULTI_DOMAIN_MASK 0xFF00 236 1.2.2.2 mjf 237 1.2.2.2 mjf /* 238 1.2.2.2 mjf * Enumerated Regulatory Domain Information 8 bit values indicate that 239 1.2.2.2 mjf * the regdomain is really a pair of unitary regdomains. 12 bit values 240 1.2.2.2 mjf * are the real unitary regdomains and are the only ones which have the 241 1.2.2.2 mjf * frequency bitmasks and flags set. 242 1.2.2.2 mjf */ 243 1.2.2.2 mjf enum { 244 1.2.2.2 mjf /* 245 1.2.2.2 mjf * The following regulatory domain definitions are 246 1.2.2.2 mjf * found in the EEPROM. Each regulatory domain 247 1.2.2.2 mjf * can operate in either a 5GHz or 2.4GHz wireless mode or 248 1.2.2.2 mjf * both 5GHz and 2.4GHz wireless modes. 249 1.2.2.2 mjf * In general, the value holds no special 250 1.2.2.2 mjf * meaning and is used to decode into either specific 251 1.2.2.2 mjf * 2.4GHz or 5GHz wireless mode for that particular 252 1.2.2.2 mjf * regulatory domain. 253 1.2.2.2 mjf */ 254 1.2.2.2 mjf NO_ENUMRD = 0x00, 255 1.2.2.2 mjf NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */ 256 1.2.2.2 mjf NULL1_ETSIB = 0x07, /* Israel */ 257 1.2.2.2 mjf NULL1_ETSIC = 0x08, 258 1.2.2.2 mjf FCC1_FCCA = 0x10, /* USA */ 259 1.2.2.2 mjf FCC1_WORLD = 0x11, /* Hong Kong */ 260 1.2.2.2 mjf FCC4_FCCA = 0x12, /* USA - Public Safety */ 261 1.2.2.2 mjf FCC5_FCCB = 0x13, /* USA w/ 1/2 and 1/4 width channels */ 262 1.2.2.2 mjf 263 1.2.2.2 mjf FCC2_FCCA = 0x20, /* Canada */ 264 1.2.2.2 mjf FCC2_WORLD = 0x21, /* Australia & HK */ 265 1.2.2.2 mjf FCC2_ETSIC = 0x22, 266 1.2.2.2 mjf FRANCE_RES = 0x31, /* Legacy France for OEM */ 267 1.2.2.2 mjf FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */ 268 1.2.2.2 mjf FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */ 269 1.2.2.2 mjf 270 1.2.2.2 mjf ETSI1_WORLD = 0x37, 271 1.2.2.2 mjf ETSI3_ETSIA = 0x32, /* France (optional) */ 272 1.2.2.2 mjf ETSI2_WORLD = 0x35, /* Hungary & others */ 273 1.2.2.2 mjf ETSI3_WORLD = 0x36, /* France & others */ 274 1.2.2.2 mjf ETSI4_WORLD = 0x30, 275 1.2.2.2 mjf ETSI4_ETSIC = 0x38, 276 1.2.2.2 mjf ETSI5_WORLD = 0x39, 277 1.2.2.2 mjf ETSI6_WORLD = 0x34, /* Bulgaria */ 278 1.2.2.2 mjf ETSI_RESERVED = 0x33, /* Reserved (Do not used) */ 279 1.2.2.2 mjf 280 1.2.2.2 mjf MKK1_MKKA = 0x40, /* Japan (JP1) */ 281 1.2.2.2 mjf MKK1_MKKB = 0x41, /* Japan (JP0) */ 282 1.2.2.2 mjf APL4_WORLD = 0x42, /* Singapore */ 283 1.2.2.2 mjf MKK2_MKKA = 0x43, /* Japan with 4.9G channels */ 284 1.2.2.2 mjf APL_RESERVED = 0x44, /* Reserved (Do not used) */ 285 1.2.2.2 mjf APL2_WORLD = 0x45, /* Korea */ 286 1.2.2.2 mjf APL2_APLC = 0x46, 287 1.2.2.2 mjf APL3_WORLD = 0x47, 288 1.2.2.2 mjf MKK1_FCCA = 0x48, /* Japan (JP1-1) */ 289 1.2.2.2 mjf APL2_APLD = 0x49, /* Korea with 2.3G channels */ 290 1.2.2.2 mjf MKK1_MKKA1 = 0x4A, /* Japan (JE1) */ 291 1.2.2.2 mjf MKK1_MKKA2 = 0x4B, /* Japan (JE2) */ 292 1.2.2.2 mjf MKK1_MKKC = 0x4C, /* Japan (MKK1_MKKA,except Ch14) */ 293 1.2.2.2 mjf 294 1.2.2.2 mjf APL3_FCCA = 0x50, 295 1.2.2.2 mjf APL1_WORLD = 0x52, /* Latin America */ 296 1.2.2.2 mjf APL1_FCCA = 0x53, 297 1.2.2.2 mjf APL1_APLA = 0x54, 298 1.2.2.2 mjf APL1_ETSIC = 0x55, 299 1.2.2.2 mjf APL2_ETSIC = 0x56, /* Venezuela */ 300 1.2.2.2 mjf APL5_WORLD = 0x58, /* Chile */ 301 1.2.2.2 mjf APL6_WORLD = 0x5B, /* Singapore */ 302 1.2.2.2 mjf APL7_FCCA = 0x5C, /* Taiwan 5.47 Band */ 303 1.2.2.2 mjf APL8_WORLD = 0x5D, /* Malaysia 5GHz */ 304 1.2.2.2 mjf APL9_WORLD = 0x5E, /* Korea 5GHz */ 305 1.2.2.2 mjf 306 1.2.2.2 mjf /* 307 1.2.2.2 mjf * World mode SKUs 308 1.2.2.2 mjf */ 309 1.2.2.2 mjf WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */ 310 1.2.2.2 mjf WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */ 311 1.2.2.2 mjf WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */ 312 1.2.2.2 mjf WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */ 313 1.2.2.2 mjf WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */ 314 1.2.2.2 mjf WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */ 315 1.2.2.2 mjf 316 1.2.2.2 mjf WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */ 317 1.2.2.2 mjf WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */ 318 1.2.2.2 mjf EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */ 319 1.2.2.2 mjf 320 1.2.2.2 mjf WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */ 321 1.2.2.2 mjf WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */ 322 1.2.2.2 mjf 323 1.2.2.2 mjf MKK3_MKKB = 0x80, /* Japan UNI-1 even + MKKB */ 324 1.2.2.2 mjf MKK3_MKKA2 = 0x81, /* Japan UNI-1 even + MKKA2 */ 325 1.2.2.2 mjf MKK3_MKKC = 0x82, /* Japan UNI-1 even + MKKC */ 326 1.2.2.2 mjf 327 1.2.2.2 mjf MKK4_MKKB = 0x83, /* Japan UNI-1 even + UNI-2 + MKKB */ 328 1.2.2.2 mjf MKK4_MKKA2 = 0x84, /* Japan UNI-1 even + UNI-2 + MKKA2 */ 329 1.2.2.2 mjf MKK4_MKKC = 0x85, /* Japan UNI-1 even + UNI-2 + MKKC */ 330 1.2.2.2 mjf 331 1.2.2.2 mjf MKK5_MKKB = 0x86, /* Japan UNI-1 even + UNI-2 + mid-band + MKKB */ 332 1.2.2.2 mjf MKK5_MKKA2 = 0x87, /* Japan UNI-1 even + UNI-2 + mid-band + MKKA2 */ 333 1.2.2.2 mjf MKK5_MKKC = 0x88, /* Japan UNI-1 even + UNI-2 + mid-band + MKKC */ 334 1.2.2.2 mjf 335 1.2.2.2 mjf MKK6_MKKB = 0x89, /* Japan UNI-1 even + UNI-1 odd MKKB */ 336 1.2.2.2 mjf MKK6_MKKA2 = 0x8A, /* Japan UNI-1 even + UNI-1 odd + MKKA2 */ 337 1.2.2.2 mjf MKK6_MKKC = 0x8B, /* Japan UNI-1 even + UNI-1 odd + MKKC */ 338 1.2.2.2 mjf 339 1.2.2.2 mjf MKK7_MKKB = 0x8C, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKB */ 340 1.2.2.2 mjf MKK7_MKKA2 = 0x8D, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA2 */ 341 1.2.2.2 mjf MKK7_MKKC = 0x8E, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKC */ 342 1.2.2.2 mjf 343 1.2.2.2 mjf MKK8_MKKB = 0x8F, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKB */ 344 1.2.2.2 mjf MKK8_MKKA2 = 0x90, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKA2 */ 345 1.2.2.2 mjf MKK8_MKKC = 0x91, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKC */ 346 1.2.2.2 mjf 347 1.2.2.2 mjf /* Following definitions are used only by s/w to map old 348 1.2.2.2 mjf * Japan SKUs. 349 1.2.2.2 mjf */ 350 1.2.2.2 mjf MKK3_MKKA = 0xF0, /* Japan UNI-1 even + MKKA */ 351 1.2.2.2 mjf MKK3_MKKA1 = 0xF1, /* Japan UNI-1 even + MKKA1 */ 352 1.2.2.2 mjf MKK3_FCCA = 0xF2, /* Japan UNI-1 even + FCCA */ 353 1.2.2.2 mjf MKK4_MKKA = 0xF3, /* Japan UNI-1 even + UNI-2 + MKKA */ 354 1.2.2.2 mjf MKK4_MKKA1 = 0xF4, /* Japan UNI-1 even + UNI-2 + MKKA1 */ 355 1.2.2.2 mjf MKK4_FCCA = 0xF5, /* Japan UNI-1 even + UNI-2 + FCCA */ 356 1.2.2.2 mjf MKK9_MKKA = 0xF6, /* Japan UNI-1 even + 4.9GHz */ 357 1.2.2.2 mjf MKK10_MKKA = 0xF7, /* Japan UNI-1 even + UNI-2 + 4.9GHz */ 358 1.2.2.2 mjf 359 1.2.2.2 mjf /* 360 1.2.2.2 mjf * Regulator domains ending in a number (e.g. APL1, 361 1.2.2.2 mjf * MK1, ETSI4, etc) apply to 5GHz channel and power 362 1.2.2.2 mjf * information. Regulator domains ending in a letter 363 1.2.2.2 mjf * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and 364 1.2.2.2 mjf * power information. 365 1.2.2.2 mjf */ 366 1.2.2.2 mjf APL1 = 0x0150, /* LAT & Asia */ 367 1.2.2.2 mjf APL2 = 0x0250, /* LAT & Asia */ 368 1.2.2.2 mjf APL3 = 0x0350, /* Taiwan */ 369 1.2.2.2 mjf APL4 = 0x0450, /* Jordan */ 370 1.2.2.2 mjf APL5 = 0x0550, /* Chile */ 371 1.2.2.2 mjf APL6 = 0x0650, /* Singapore */ 372 1.2.2.2 mjf APL8 = 0x0850, /* Malaysia */ 373 1.2.2.2 mjf APL9 = 0x0950, /* Korea (South) ROC 3 */ 374 1.2.2.2 mjf 375 1.2.2.2 mjf ETSI1 = 0x0130, /* Europe & others */ 376 1.2.2.2 mjf ETSI2 = 0x0230, /* Europe & others */ 377 1.2.2.2 mjf ETSI3 = 0x0330, /* Europe & others */ 378 1.2.2.2 mjf ETSI4 = 0x0430, /* Europe & others */ 379 1.2.2.2 mjf ETSI5 = 0x0530, /* Europe & others */ 380 1.2.2.2 mjf ETSI6 = 0x0630, /* Europe & others */ 381 1.2.2.2 mjf ETSIA = 0x0A30, /* France */ 382 1.2.2.2 mjf ETSIB = 0x0B30, /* Israel */ 383 1.2.2.2 mjf ETSIC = 0x0C30, /* Latin America */ 384 1.2.2.2 mjf 385 1.2.2.2 mjf FCC1 = 0x0110, /* US & others */ 386 1.2.2.2 mjf FCC2 = 0x0120, /* Canada, Australia & New Zealand */ 387 1.2.2.2 mjf FCC3 = 0x0160, /* US w/new middle band & DFS */ 388 1.2.2.2 mjf FCC4 = 0x0165, /* US Public Safety */ 389 1.2.2.2 mjf FCC5 = 0x0166, /* US w/ 1/2 and 1/4 width channels */ 390 1.2.2.2 mjf FCCA = 0x0A10, 391 1.2.2.2 mjf FCCB = 0x0A11, /* US w/ 1/2 and 1/4 width channels */ 392 1.2.2.2 mjf 393 1.2.2.2 mjf APLD = 0x0D50, /* South Korea */ 394 1.2.2.2 mjf 395 1.2.2.2 mjf MKK1 = 0x0140, /* Japan (UNI-1 odd)*/ 396 1.2.2.2 mjf MKK2 = 0x0240, /* Japan (4.9 GHz + UNI-1 odd) */ 397 1.2.2.2 mjf MKK3 = 0x0340, /* Japan (UNI-1 even) */ 398 1.2.2.2 mjf MKK4 = 0x0440, /* Japan (UNI-1 even + UNI-2) */ 399 1.2.2.2 mjf MKK5 = 0x0540, /* Japan (UNI-1 even + UNI-2 + mid-band) */ 400 1.2.2.2 mjf MKK6 = 0x0640, /* Japan (UNI-1 odd + UNI-1 even) */ 401 1.2.2.2 mjf MKK7 = 0x0740, /* Japan (UNI-1 odd + UNI-1 even + UNI-2 */ 402 1.2.2.2 mjf MKK8 = 0x0840, /* Japan (UNI-1 odd + UNI-1 even + UNI-2 + mid-band) */ 403 1.2.2.2 mjf MKK9 = 0x0940, /* Japan (UNI-1 even + 4.9 GHZ) */ 404 1.2.2.2 mjf MKK10 = 0x0B40, /* Japan (UNI-1 even + UNI-2 + 4.9 GHZ) */ 405 1.2.2.2 mjf MKKA = 0x0A40, /* Japan */ 406 1.2.2.2 mjf MKKC = 0x0A50, 407 1.2.2.2 mjf 408 1.2.2.2 mjf NULL1 = 0x0198, 409 1.2.2.2 mjf WORLD = 0x0199, 410 1.2.2.2 mjf SR9_WORLD = 0x0298, 411 1.2.2.2 mjf XR9_WORLD = 0x0299, 412 1.2.2.2 mjf GZ901_WORLD = 0x029a, 413 1.2.2.2 mjf DEBUG_REG_DMN = 0x01ff, 414 1.2.2.2 mjf }; 415 1.2.2.2 mjf 416 1.2.2.2 mjf #define WORLD_SKU_MASK 0x00F0 417 1.2.2.2 mjf #define WORLD_SKU_PREFIX 0x0060 418 1.2.2.2 mjf 419 1.2.2.2 mjf enum { /* conformance test limits */ 420 1.2.2.2 mjf FCC = 0x10, 421 1.2.2.2 mjf MKK = 0x40, 422 1.2.2.2 mjf ETSI = 0x30, 423 1.2.2.2 mjf }; 424 1.2.2.2 mjf 425 1.2.2.2 mjf /* 426 1.2.2.2 mjf * The following are flags for different requirements per reg domain. 427 1.2.2.2 mjf * These requirements are either inhereted from the reg domain pair or 428 1.2.2.2 mjf * from the unitary reg domain if the reg domain pair flags value is 0 429 1.2.2.2 mjf */ 430 1.2.2.2 mjf enum { 431 1.2.2.2 mjf NO_REQ = 0x00000000, /* NB: must be zero */ 432 1.2.2.2 mjf DISALLOW_ADHOC_11A = 0x00000001, 433 1.2.2.2 mjf DISALLOW_ADHOC_11A_TURB = 0x00000002, 434 1.2.2.2 mjf NEED_NFC = 0x00000004, 435 1.2.2.2 mjf ADHOC_PER_11D = 0x00000008, /* Start Ad-Hoc mode */ 436 1.2.2.2 mjf ADHOC_NO_11A = 0x00000010, 437 1.2.2.2 mjf LIMIT_FRAME_4MS = 0x00000020, /* 4msec limit on frame length*/ 438 1.2.2.2 mjf NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */ 439 1.2.2.2 mjf }; 440 1.2.2.2 mjf 441 1.2.2.2 mjf /* 442 1.2.2.2 mjf * The following describe the bit masks for different passive scan 443 1.2.2.2 mjf * capability/requirements per regdomain. 444 1.2.2.2 mjf */ 445 1.2.2.2 mjf #define NO_PSCAN 0x0ULL /* NB: must be zero */ 446 1.2.2.2 mjf #define PSCAN_FCC 0x0000000000000001ULL 447 1.2.2.2 mjf #define PSCAN_FCC_T 0x0000000000000002ULL 448 1.2.2.2 mjf #define PSCAN_ETSI 0x0000000000000004ULL 449 1.2.2.2 mjf #define PSCAN_MKK1 0x0000000000000008ULL 450 1.2.2.2 mjf #define PSCAN_MKK2 0x0000000000000010ULL 451 1.2.2.2 mjf #define PSCAN_MKKA 0x0000000000000020ULL 452 1.2.2.2 mjf #define PSCAN_MKKA_G 0x0000000000000040ULL 453 1.2.2.2 mjf #define PSCAN_ETSIA 0x0000000000000080ULL 454 1.2.2.2 mjf #define PSCAN_ETSIB 0x0000000000000100ULL 455 1.2.2.2 mjf #define PSCAN_ETSIC 0x0000000000000200ULL 456 1.2.2.2 mjf #define PSCAN_WWR 0x0000000000000400ULL 457 1.2.2.2 mjf #define PSCAN_MKKA1 0x0000000000000800ULL 458 1.2.2.2 mjf #define PSCAN_MKKA1_G 0x0000000000001000ULL 459 1.2.2.2 mjf #define PSCAN_MKKA2 0x0000000000002000ULL 460 1.2.2.2 mjf #define PSCAN_MKKA2_G 0x0000000000004000ULL 461 1.2.2.2 mjf #define PSCAN_MKK3 0x0000000000008000ULL 462 1.2.2.2 mjf #define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL 463 1.2.2.2 mjf #define IS_ECM_CHAN 0x8000000000000000ULL 464 1.2.2.2 mjf 465 1.2.2.2 mjf /* 466 1.2.2.2 mjf * THE following table is the mapping of regdomain pairs specified by 467 1.2.2.2 mjf * an 8 bit regdomain value to the individual unitary reg domains 468 1.2.2.2 mjf */ 469 1.2.2.2 mjf typedef struct { 470 1.2.2.2 mjf HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */ 471 1.2.2.2 mjf HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */ 472 1.2.2.2 mjf HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */ 473 1.2.2.2 mjf uint32_t flags5GHz; /* Requirements flags (AdHoc 474 1.2.2.2 mjf disallow, noise floor cal needed, 475 1.2.2.2 mjf etc) */ 476 1.2.2.2 mjf uint32_t flags2GHz; /* Requirements flags (AdHoc 477 1.2.2.2 mjf disallow, noise floor cal needed, 478 1.2.2.2 mjf etc) */ 479 1.2.2.2 mjf uint64_t pscanMask; /* Passive Scan flags which 480 1.2.2.2 mjf can override unitary domain 481 1.2.2.2 mjf passive scan flags. This 482 1.2.2.2 mjf value is used as a mask on 483 1.2.2.2 mjf the unitary flags*/ 484 1.2.2.2 mjf uint16_t singleCC; /* Country code of single country if 485 1.2.2.2 mjf a one-on-one mapping exists */ 486 1.2.2.2 mjf } REG_DMN_PAIR_MAPPING; 487 1.2.2.2 mjf 488 1.2.2.2 mjf static REG_DMN_PAIR_MAPPING regDomainPairs[] = { 489 1.2.2.2 mjf {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 490 1.2.2.2 mjf {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 491 1.2.2.2 mjf {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 492 1.2.2.2 mjf {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 493 1.2.2.2 mjf 494 1.2.2.2 mjf {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 495 1.2.2.2 mjf {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 496 1.2.2.2 mjf {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 497 1.2.2.2 mjf {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 498 1.2.2.2 mjf {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 499 1.2.2.2 mjf {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 500 1.2.2.2 mjf {FCC5_FCCB, FCC5, FCCB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 501 1.2.2.2 mjf 502 1.2.2.2 mjf {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 503 1.2.2.2 mjf {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 504 1.2.2.2 mjf {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 505 1.2.2.2 mjf {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 506 1.2.2.2 mjf {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 507 1.2.2.2 mjf {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 508 1.2.2.2 mjf 509 1.2.2.2 mjf {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 510 1.2.2.2 mjf {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 511 1.2.2.2 mjf 512 1.2.2.2 mjf {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 513 1.2.2.2 mjf {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 514 1.2.2.2 mjf {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 515 1.2.2.2 mjf {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 516 1.2.2.2 mjf {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 517 1.2.2.2 mjf {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 518 1.2.2.2 mjf {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 519 1.2.2.2 mjf {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 520 1.2.2.2 mjf {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 521 1.2.2.2 mjf {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 522 1.2.2.2 mjf 523 1.2.2.2 mjf {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 524 1.2.2.2 mjf {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 525 1.2.2.2 mjf {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 526 1.2.2.2 mjf {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 527 1.2.2.2 mjf 528 1.2.2.2 mjf {MKK1_MKKA, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN }, 529 1.2.2.2 mjf {MKK1_MKKB, MKK1, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 }, 530 1.2.2.2 mjf {MKK1_FCCA, MKK1, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 }, 531 1.2.2.2 mjf {MKK1_MKKA1, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 }, 532 1.2.2.2 mjf {MKK1_MKKA2, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 }, 533 1.2.2.2 mjf {MKK1_MKKC, MKK1, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 }, 534 1.2.2.2 mjf 535 1.2.2.2 mjf /* MKK2 */ 536 1.2.2.2 mjf {MKK2_MKKA, MKK2, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 }, 537 1.2.2.2 mjf 538 1.2.2.2 mjf /* MKK3 */ 539 1.2.2.2 mjf {MKK3_MKKA, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC , PSCAN_MKKA, 0 }, 540 1.2.2.2 mjf {MKK3_MKKB, MKK3, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 }, 541 1.2.2.2 mjf {MKK3_MKKA1, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, 0 }, 542 1.2.2.2 mjf {MKK3_MKKA2,MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 }, 543 1.2.2.2 mjf {MKK3_MKKC, MKK3, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 }, 544 1.2.2.2 mjf {MKK3_FCCA, MKK3, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, 0 }, 545 1.2.2.2 mjf 546 1.2.2.2 mjf /* MKK4 */ 547 1.2.2.2 mjf {MKK4_MKKB, MKK4, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 }, 548 1.2.2.2 mjf {MKK4_MKKA1, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, 0 }, 549 1.2.2.2 mjf {MKK4_MKKA2, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 |PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 }, 550 1.2.2.2 mjf {MKK4_MKKC, MKK4, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 }, 551 1.2.2.2 mjf {MKK4_FCCA, MKK4, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, 0 }, 552 1.2.2.2 mjf 553 1.2.2.2 mjf /* MKK5 */ 554 1.2.2.2 mjf {MKK5_MKKB, MKK5, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 }, 555 1.2.2.2 mjf {MKK5_MKKA2,MKK5, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 }, 556 1.2.2.2 mjf {MKK5_MKKC, MKK5, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 }, 557 1.2.2.2 mjf 558 1.2.2.2 mjf /* MKK6 */ 559 1.2.2.2 mjf {MKK6_MKKB, MKK6, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 }, 560 1.2.2.2 mjf {MKK6_MKKA2, MKK6, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 }, 561 1.2.2.2 mjf {MKK6_MKKC, MKK6, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 }, 562 1.2.2.2 mjf 563 1.2.2.2 mjf /* MKK7 */ 564 1.2.2.2 mjf {MKK7_MKKB, MKK7, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 }, 565 1.2.2.2 mjf {MKK7_MKKA2, MKK7, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 }, 566 1.2.2.2 mjf {MKK7_MKKC, MKK7, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 }, 567 1.2.2.2 mjf 568 1.2.2.2 mjf /* MKK8 */ 569 1.2.2.2 mjf {MKK8_MKKB, MKK8, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 }, 570 1.2.2.2 mjf {MKK8_MKKA2,MKK8, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 }, 571 1.2.2.2 mjf {MKK8_MKKC, MKK8, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 }, 572 1.2.2.2 mjf 573 1.2.2.2 mjf {MKK9_MKKA, MKK9, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 0 }, 574 1.2.2.2 mjf {MKK10_MKKA, MKK10, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 0 }, 575 1.2.2.2 mjf 576 1.2.2.2 mjf /* These are super domains */ 577 1.2.2.2 mjf {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 578 1.2.2.2 mjf {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 579 1.2.2.2 mjf {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 580 1.2.2.2 mjf {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 581 1.2.2.2 mjf {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 582 1.2.2.2 mjf {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 583 1.2.2.2 mjf {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 584 1.2.2.2 mjf {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 585 1.2.2.2 mjf {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 586 1.2.2.2 mjf {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 587 1.2.2.2 mjf {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 588 1.2.2.2 mjf {SR9_WORLD, NULL1, SR9_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_SR9 }, 589 1.2.2.2 mjf {XR9_WORLD, NULL1, XR9_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_XR9 }, 590 1.2.2.2 mjf {GZ901_WORLD, NULL1, GZ901_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_GZ901 }, 591 1.2.2.2 mjf }; 592 1.2.2.2 mjf 593 1.2.2.2 mjf /* 594 1.2.2.2 mjf * The following tables are the master list for all different freqeuncy 595 1.2.2.2 mjf * bands with the complete matrix of all possible flags and settings 596 1.2.2.2 mjf * for each band if it is used in ANY reg domain. 597 1.2.2.2 mjf */ 598 1.2.2.2 mjf 599 1.2.2.2 mjf #define DEF_REGDMN FCC1_FCCA 600 1.2.2.2 mjf #define DEF_DMN_5 FCC1 601 1.2.2.2 mjf #define DEF_DMN_2 FCCA 602 1.2.2.2 mjf #define COUNTRY_ERD_FLAG 0x8000 603 1.2.2.2 mjf #define WORLDWIDE_ROAMING_FLAG 0x4000 604 1.2.2.2 mjf #define SUPER_DOMAIN_MASK 0x0fff 605 1.2.2.2 mjf #define COUNTRY_CODE_MASK 0x3fff 606 1.2.2.2 mjf 607 1.2.2.2 mjf #define YES AH_TRUE 608 1.2.2.2 mjf #define NO AH_FALSE 609 1.2.2.2 mjf 610 1.2.2.2 mjf typedef struct { 611 1.2.2.2 mjf HAL_CTRY_CODE countryCode; 612 1.2.2.2 mjf HAL_REG_DOMAIN regDmnEnum; 613 1.2.2.2 mjf HAL_BOOL allow11g; 614 1.2.2.2 mjf HAL_BOOL allow11aTurbo; 615 1.2.2.2 mjf HAL_BOOL allow11gTurbo; 616 1.2.2.2 mjf HAL_BOOL allow11ng20; 617 1.2.2.2 mjf HAL_BOOL allow11ng40; 618 1.2.2.2 mjf HAL_BOOL allow11na20; 619 1.2.2.2 mjf HAL_BOOL allow11na40; 620 1.2.2.2 mjf uint16_t outdoorChanStart; 621 1.2.2.2 mjf } COUNTRY_CODE_TO_ENUM_RD; 622 1.2.2.2 mjf 623 1.2.2.2 mjf static COUNTRY_CODE_TO_ENUM_RD allCountries[] = { 624 1.2.2.2 mjf {CTRY_DEBUG, NO_ENUMRD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 625 1.2.2.2 mjf {CTRY_DEFAULT, DEF_REGDMN, YES, YES, YES, YES,YES, YES,YES, 7000 }, 626 1.2.2.2 mjf {CTRY_ALBANIA, NULL1_WORLD, YES, NO, YES, YES, NO, NO, NO, 7000 }, 627 1.2.2.2 mjf {CTRY_ALGERIA, NULL1_WORLD, YES, NO, YES, YES, NO, NO, NO, 7000 }, 628 1.2.2.2 mjf {CTRY_ARGENTINA, APL3_WORLD, NO, NO, NO, NO, NO, NO, NO, 7000 }, 629 1.2.2.2 mjf {CTRY_ARMENIA, ETSI4_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 630 1.2.2.2 mjf {CTRY_AUSTRALIA, FCC2_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 631 1.2.2.2 mjf {CTRY_AUSTRIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 632 1.2.2.2 mjf {CTRY_AZERBAIJAN, ETSI4_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 633 1.2.2.2 mjf {CTRY_BAHRAIN, APL6_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 634 1.2.2.2 mjf {CTRY_BELARUS, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 635 1.2.2.2 mjf {CTRY_BELGIUM, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 636 1.2.2.2 mjf {CTRY_BELIZE, APL1_ETSIC, YES, YES, YES, YES,YES, YES,YES, 7000 }, 637 1.2.2.2 mjf {CTRY_BOLIVIA, APL1_ETSIC, YES, YES, YES, YES,YES, YES,YES, 7000 }, 638 1.2.2.2 mjf {CTRY_BRAZIL, FCC3_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 }, 639 1.2.2.2 mjf {CTRY_BRUNEI_DARUSSALAM,APL1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 640 1.2.2.2 mjf {CTRY_BULGARIA, ETSI6_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 641 1.2.2.2 mjf {CTRY_CANADA, FCC2_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 }, 642 1.2.2.2 mjf {CTRY_CHILE, APL6_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 643 1.2.2.2 mjf {CTRY_CHINA, APL1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 644 1.2.2.2 mjf {CTRY_COLOMBIA, FCC1_FCCA, YES, NO, YES, YES,YES, YES, NO, 7000 }, 645 1.2.2.2 mjf {CTRY_COSTA_RICA, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 646 1.2.2.2 mjf {CTRY_CROATIA, ETSI3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 647 1.2.2.2 mjf {CTRY_CYPRUS, ETSI1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 648 1.2.2.2 mjf {CTRY_CZECH, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 649 1.2.2.2 mjf {CTRY_DENMARK, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 650 1.2.2.2 mjf {CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 }, 651 1.2.2.2 mjf {CTRY_ECUADOR, NULL1_WORLD, NO, NO, NO, NO, NO, NO, NO, 7000 }, 652 1.2.2.2 mjf {CTRY_EGYPT, ETSI3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 653 1.2.2.2 mjf {CTRY_EL_SALVADOR, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 654 1.2.2.2 mjf {CTRY_ESTONIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 655 1.2.2.2 mjf {CTRY_FINLAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 656 1.2.2.2 mjf {CTRY_FRANCE, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 657 1.2.2.2 mjf {CTRY_FRANCE2, ETSI3_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 658 1.2.2.2 mjf {CTRY_GEORGIA, ETSI4_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 659 1.2.2.2 mjf {CTRY_GERMANY, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 660 1.2.2.2 mjf {CTRY_GREECE, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 661 1.2.2.2 mjf {CTRY_GUATEMALA, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 }, 662 1.2.2.2 mjf {CTRY_GZ901, GZ901_WORLD, YES, NO, NO, NO, NO, NO, NO, 7000 }, 663 1.2.2.2 mjf {CTRY_HONDURAS, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 664 1.2.2.2 mjf {CTRY_HONG_KONG, FCC2_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 665 1.2.2.2 mjf {CTRY_HUNGARY, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 666 1.2.2.2 mjf {CTRY_ICELAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 667 1.2.2.2 mjf {CTRY_INDIA, APL6_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 668 1.2.2.2 mjf {CTRY_INDONESIA, APL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 669 1.2.2.2 mjf {CTRY_IRAN, APL1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 670 1.2.2.2 mjf {CTRY_IRELAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 671 1.2.2.2 mjf {CTRY_ISRAEL, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 672 1.2.2.2 mjf {CTRY_ITALY, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 673 1.2.2.2 mjf {CTRY_JAPAN, MKK1_MKKA, YES, NO, NO, YES, NO, YES, NO, 7000 }, 674 1.2.2.2 mjf {CTRY_JAPAN1, MKK1_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 }, 675 1.2.2.2 mjf {CTRY_JAPAN2, MKK1_FCCA, YES, NO, NO, NO, NO, NO, NO, 7000 }, 676 1.2.2.2 mjf {CTRY_JAPAN3, MKK2_MKKA, YES, NO, NO, NO, NO, NO, NO, 7000 }, 677 1.2.2.2 mjf {CTRY_JAPAN4, MKK1_MKKA1, YES, NO, NO, NO, NO, NO, NO, 7000 }, 678 1.2.2.2 mjf {CTRY_JAPAN5, MKK1_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 }, 679 1.2.2.2 mjf {CTRY_JAPAN6, MKK1_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 }, 680 1.2.2.2 mjf 681 1.2.2.2 mjf {CTRY_JAPAN7, MKK3_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 }, 682 1.2.2.2 mjf {CTRY_JAPAN8, MKK3_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 }, 683 1.2.2.2 mjf {CTRY_JAPAN9, MKK3_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 }, 684 1.2.2.2 mjf 685 1.2.2.2 mjf {CTRY_JAPAN10, MKK4_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 }, 686 1.2.2.2 mjf {CTRY_JAPAN11, MKK4_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 }, 687 1.2.2.2 mjf {CTRY_JAPAN12, MKK4_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 }, 688 1.2.2.2 mjf 689 1.2.2.2 mjf {CTRY_JAPAN13, MKK5_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 }, 690 1.2.2.2 mjf {CTRY_JAPAN14, MKK5_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 }, 691 1.2.2.2 mjf {CTRY_JAPAN15, MKK5_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 }, 692 1.2.2.2 mjf 693 1.2.2.2 mjf {CTRY_JAPAN16, MKK6_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 }, 694 1.2.2.2 mjf {CTRY_JAPAN17, MKK6_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 }, 695 1.2.2.2 mjf {CTRY_JAPAN18, MKK6_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 }, 696 1.2.2.2 mjf 697 1.2.2.2 mjf {CTRY_JAPAN19, MKK7_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 }, 698 1.2.2.2 mjf {CTRY_JAPAN20, MKK7_MKKA2, YES, NO, NO, YES, NO, YES, NO, 7000 }, 699 1.2.2.2 mjf {CTRY_JAPAN21, MKK7_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 }, 700 1.2.2.2 mjf 701 1.2.2.2 mjf {CTRY_JAPAN22, MKK8_MKKB, YES, NO, NO, NO, NO, NO, NO, 7000 }, 702 1.2.2.2 mjf {CTRY_JAPAN23, MKK8_MKKA2, YES, NO, NO, NO, NO, NO, NO, 7000 }, 703 1.2.2.2 mjf {CTRY_JAPAN24, MKK8_MKKC, YES, NO, NO, NO, NO, NO, NO, 7000 }, 704 1.2.2.2 mjf 705 1.2.2.2 mjf {CTRY_JORDAN, APL4_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 706 1.2.2.2 mjf {CTRY_KAZAKHSTAN, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 707 1.2.2.2 mjf {CTRY_KOREA_NORTH, APL2_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 708 1.2.2.2 mjf {CTRY_KOREA_ROC, APL2_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 }, 709 1.2.2.2 mjf {CTRY_KOREA_ROC2, APL2_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 }, 710 1.2.2.2 mjf {CTRY_KOREA_ROC3, APL9_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 }, 711 1.2.2.2 mjf {CTRY_KUWAIT, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 712 1.2.2.2 mjf {CTRY_LATVIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 713 1.2.2.2 mjf {CTRY_LEBANON, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 714 1.2.2.2 mjf {CTRY_LIECHTENSTEIN,ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 715 1.2.2.2 mjf {CTRY_LITHUANIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 716 1.2.2.2 mjf {CTRY_LUXEMBOURG, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 717 1.2.2.2 mjf {CTRY_MACAU, FCC2_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 718 1.2.2.2 mjf {CTRY_MACEDONIA, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 719 1.2.2.2 mjf {CTRY_MALAYSIA, APL8_WORLD, YES, NO, NO, YES, NO, YES, NO, 7000 }, 720 1.2.2.2 mjf {CTRY_MALTA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 721 1.2.2.2 mjf {CTRY_MEXICO, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 }, 722 1.2.2.2 mjf {CTRY_MONACO, ETSI4_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 723 1.2.2.2 mjf {CTRY_MOROCCO, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 724 1.2.2.2 mjf {CTRY_NETHERLANDS, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 725 1.2.2.2 mjf {CTRY_NEW_ZEALAND, FCC2_ETSIC, YES, NO, YES, YES,YES, YES,YES, 7000 }, 726 1.2.2.2 mjf {CTRY_NORWAY, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 727 1.2.2.2 mjf {CTRY_OMAN, APL6_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 728 1.2.2.2 mjf {CTRY_PAKISTAN, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 729 1.2.2.2 mjf {CTRY_PANAMA, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 }, 730 1.2.2.2 mjf {CTRY_PERU, APL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 731 1.2.2.2 mjf {CTRY_PHILIPPINES, FCC3_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 732 1.2.2.2 mjf {CTRY_POLAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 733 1.2.2.2 mjf {CTRY_PORTUGAL, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 734 1.2.2.2 mjf {CTRY_PUERTO_RICO, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 }, 735 1.2.2.2 mjf {CTRY_QATAR, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 736 1.2.2.2 mjf {CTRY_ROMANIA, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 737 1.2.2.2 mjf {CTRY_RUSSIA, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 738 1.2.2.2 mjf {CTRY_SAUDI_ARABIA,FCC2_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 739 1.2.2.2 mjf {CTRY_SINGAPORE, APL6_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 }, 740 1.2.2.2 mjf {CTRY_SLOVAKIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 741 1.2.2.2 mjf {CTRY_SLOVENIA, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 742 1.2.2.2 mjf {CTRY_SOUTH_AFRICA,FCC3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 743 1.2.2.2 mjf {CTRY_SPAIN, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 744 1.2.2.2 mjf {CTRY_SR9, SR9_WORLD, YES, NO, NO, NO, NO, NO, NO, 7000 }, 745 1.2.2.2 mjf {CTRY_SWEDEN, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 746 1.2.2.2 mjf {CTRY_SWITZERLAND, ETSI1_WORLD, YES, NO, YES, YES,YES, YES,YES, 7000 }, 747 1.2.2.2 mjf {CTRY_SYRIA, NULL1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 748 1.2.2.2 mjf {CTRY_TAIWAN, APL3_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 }, 749 1.2.2.2 mjf {CTRY_THAILAND, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 750 1.2.2.2 mjf {CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD,YES, NO, YES, YES,YES, YES, NO, 7000 }, 751 1.2.2.2 mjf {CTRY_TUNISIA, ETSI3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 752 1.2.2.2 mjf {CTRY_TURKEY, ETSI3_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 753 1.2.2.2 mjf {CTRY_UKRAINE, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 754 1.2.2.2 mjf {CTRY_UAE, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 755 1.2.2.2 mjf {CTRY_UNITED_KINGDOM, ETSI1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 756 1.2.2.2 mjf {CTRY_UNITED_STATES, FCC1_FCCA, YES, YES, YES, YES,YES, YES,YES, 5825 }, 757 1.2.2.2 mjf {CTRY_UNITED_STATES_FCC49,FCC4_FCCA,YES, YES, YES, YES,YES, YES,YES, 7000 }, 758 1.2.2.2 mjf {CTRY_URUGUAY, FCC1_WORLD, YES, NO, YES, YES,YES, YES, NO, 7000 }, 759 1.2.2.2 mjf {CTRY_UZBEKISTAN, FCC3_FCCA, YES, YES, YES, YES,YES, YES,YES, 7000 }, 760 1.2.2.2 mjf {CTRY_VENEZUELA, APL2_ETSIC, YES, NO, YES, YES,YES, YES, NO, 7000 }, 761 1.2.2.2 mjf {CTRY_VIET_NAM, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 762 1.2.2.2 mjf {CTRY_XR9, XR9_WORLD, YES, NO, NO, NO, NO, NO, NO, 7000 }, 763 1.2.2.2 mjf {CTRY_YEMEN, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 }, 764 1.2.2.2 mjf {CTRY_ZIMBABWE, NULL1_WORLD, YES, NO, YES, YES,YES, NO, NO, 7000 } 765 1.2.2.2 mjf }; 766 1.2.2.2 mjf 767 1.2.2.2 mjf /* Bit masks for DFS per regdomain */ 768 1.2.2.2 mjf enum { 769 1.2.2.2 mjf NO_DFS = 0x0000000000000000ULL, /* NB: must be zero */ 770 1.2.2.2 mjf DFS_FCC3 = 0x0000000000000001ULL, 771 1.2.2.2 mjf DFS_ETSI = 0x0000000000000002ULL, 772 1.2.2.2 mjf DFS_MKK4 = 0x0000000000000004ULL, 773 1.2.2.2 mjf }; 774 1.2.2.2 mjf 775 1.2.2.2 mjf #define AFTER(x) ((x)+1) 776 1.2.2.2 mjf 777 1.2.2.2 mjf /* 778 1.2.2.2 mjf * Frequency band collections are defined using bitmasks. Each bit 779 1.2.2.2 mjf * in a mask is the index of an entry in one of the following tables. 780 1.2.2.2 mjf * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit 781 1.2.2.2 mjf * vectors must be enlarged or the tables split somehow (e.g. split 782 1.2.2.2 mjf * 1/2 and 1/4 rate channels into a separate table). 783 1.2.2.2 mjf * 784 1.2.2.2 mjf * Beware of ordering; the indices are defined relative to the preceding 785 1.2.2.2 mjf * entry so if things get off there will be confusion. A good way to 786 1.2.2.2 mjf * check the indices is to collect them in a switch statement in a stub 787 1.2.2.2 mjf * function so the compiler checks for duplicates. 788 1.2.2.2 mjf */ 789 1.2.2.2 mjf 790 1.2.2.2 mjf typedef struct { 791 1.2.2.2 mjf uint16_t lowChannel; /* Low channel center in MHz */ 792 1.2.2.2 mjf uint16_t highChannel; /* High Channel center in MHz */ 793 1.2.2.2 mjf uint8_t powerDfs; /* Max power (dBm) for channel 794 1.2.2.2 mjf range when using DFS */ 795 1.2.2.2 mjf uint8_t antennaMax; /* Max allowed antenna gain */ 796 1.2.2.2 mjf uint8_t channelBW; /* Bandwidth of the channel */ 797 1.2.2.2 mjf uint8_t channelSep; /* Channel separation within 798 1.2.2.2 mjf the band */ 799 1.2.2.2 mjf uint64_t useDfs; /* Use DFS in the RegDomain 800 1.2.2.2 mjf if corresponding bit is set */ 801 1.2.2.2 mjf uint64_t usePassScan; /* Use Passive Scan in the RegDomain 802 1.2.2.2 mjf if corresponding bit is set */ 803 1.2.2.2 mjf uint8_t regClassId; /* Regulatory class id */ 804 1.2.2.2 mjf } REG_DMN_FREQ_BAND; 805 1.2.2.2 mjf 806 1.2.2.2 mjf /* 807 1.2.2.2 mjf * 5GHz 11A channel tags 808 1.2.2.2 mjf */ 809 1.2.2.2 mjf static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { 810 1.2.2.2 mjf { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16 }, 811 1.2.2.2 mjf #define F1_4915_4925 0 812 1.2.2.2 mjf { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16 }, 813 1.2.2.2 mjf #define F1_4935_4945 AFTER(F1_4915_4925) 814 1.2.2.2 mjf { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7 }, 815 1.2.2.2 mjf #define F1_4920_4980 AFTER(F1_4935_4945) 816 1.2.2.2 mjf { 4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC, 0 }, 817 1.2.2.2 mjf #define F1_4942_4987 AFTER(F1_4920_4980) 818 1.2.2.2 mjf { 4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC, 0 }, 819 1.2.2.2 mjf #define F1_4945_4985 AFTER(F1_4942_4987) 820 1.2.2.2 mjf { 4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC, 0 }, 821 1.2.2.2 mjf #define F1_4950_4980 AFTER(F1_4945_4985) 822 1.2.2.2 mjf { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12 }, 823 1.2.2.2 mjf #define F1_5035_5040 AFTER(F1_4950_4980) 824 1.2.2.2 mjf { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2 }, 825 1.2.2.2 mjf #define F1_5040_5080 AFTER(F1_5035_5040) 826 1.2.2.2 mjf { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12 }, 827 1.2.2.2 mjf #define F1_5055_5055 AFTER(F1_5040_5080) 828 1.2.2.2 mjf 829 1.2.2.2 mjf { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0 }, 830 1.2.2.2 mjf #define F1_5120_5240 AFTER(F1_5055_5055) 831 1.2.2.2 mjf { 5120, 5240, 5, 6, 10, 10, NO_DFS, NO_PSCAN, 0 }, 832 1.2.2.2 mjf #define F2_5120_5240 AFTER(F1_5120_5240) 833 1.2.2.2 mjf { 5120, 5240, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0 }, 834 1.2.2.2 mjf #define F3_5120_5240 AFTER(F2_5120_5240) 835 1.2.2.2 mjf 836 1.2.2.2 mjf { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1 }, 837 1.2.2.2 mjf #define F1_5170_5230 AFTER(F3_5120_5240) 838 1.2.2.2 mjf { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1 }, 839 1.2.2.2 mjf #define F2_5170_5230 AFTER(F1_5170_5230) 840 1.2.2.2 mjf 841 1.2.2.2 mjf { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 }, 842 1.2.2.2 mjf #define F1_5180_5240 AFTER(F2_5170_5230) 843 1.2.2.2 mjf { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC, 1 }, 844 1.2.2.2 mjf #define F2_5180_5240 AFTER(F1_5180_5240) 845 1.2.2.2 mjf { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 }, 846 1.2.2.2 mjf #define F3_5180_5240 AFTER(F2_5180_5240) 847 1.2.2.2 mjf { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 }, 848 1.2.2.2 mjf #define F4_5180_5240 AFTER(F3_5180_5240) 849 1.2.2.2 mjf { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 }, 850 1.2.2.2 mjf #define F5_5180_5240 AFTER(F4_5180_5240) 851 1.2.2.2 mjf { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0 }, 852 1.2.2.2 mjf #define F6_5180_5240 AFTER(F5_5180_5240) 853 1.2.2.2 mjf { 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC, 1 }, 854 1.2.2.2 mjf #define F7_5180_5240 AFTER(F6_5180_5240) 855 1.2.2.2 mjf { 5180, 5240, 17, 6, 20, 5, NO_DFS, PSCAN_FCC, 1 }, 856 1.2.2.2 mjf #define F8_5180_5240 AFTER(F7_5180_5240) 857 1.2.2.2 mjf 858 1.2.2.2 mjf { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 }, 859 1.2.2.2 mjf #define F1_5180_5320 AFTER(F8_5180_5240) 860 1.2.2.2 mjf 861 1.2.2.2 mjf { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0 }, 862 1.2.2.2 mjf #define F1_5240_5280 AFTER(F1_5180_5320) 863 1.2.2.2 mjf 864 1.2.2.2 mjf { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 }, 865 1.2.2.2 mjf #define F1_5260_5280 AFTER(F1_5240_5280) 866 1.2.2.2 mjf 867 1.2.2.2 mjf { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 }, 868 1.2.2.2 mjf #define F1_5260_5320 AFTER(F1_5260_5280) 869 1.2.2.2 mjf 870 1.2.2.2 mjf { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 , 0 }, 871 1.2.2.2 mjf #define F2_5260_5320 AFTER(F1_5260_5320) 872 1.2.2.2 mjf 873 1.2.2.2 mjf { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 }, 874 1.2.2.2 mjf #define F3_5260_5320 AFTER(F2_5260_5320) 875 1.2.2.2 mjf { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 }, 876 1.2.2.2 mjf #define F4_5260_5320 AFTER(F3_5260_5320) 877 1.2.2.2 mjf { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 }, 878 1.2.2.2 mjf #define F5_5260_5320 AFTER(F4_5260_5320) 879 1.2.2.2 mjf { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 }, 880 1.2.2.2 mjf #define F6_5260_5320 AFTER(F5_5260_5320) 881 1.2.2.2 mjf { 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 }, 882 1.2.2.2 mjf #define F7_5260_5320 AFTER(F6_5260_5320) 883 1.2.2.2 mjf { 5260, 5320, 23, 6, 20, 5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 }, 884 1.2.2.2 mjf #define F8_5260_5320 AFTER(F7_5260_5320) 885 1.2.2.2 mjf 886 1.2.2.2 mjf { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 }, 887 1.2.2.2 mjf #define F1_5260_5700 AFTER(F8_5260_5320) 888 1.2.2.2 mjf { 5260, 5700, 5, 6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 }, 889 1.2.2.2 mjf #define F2_5260_5700 AFTER(F1_5260_5700) 890 1.2.2.2 mjf { 5260, 5700, 5, 6, 5, 5, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 }, 891 1.2.2.2 mjf #define F3_5260_5700 AFTER(F2_5260_5700) 892 1.2.2.2 mjf 893 1.2.2.2 mjf { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 }, 894 1.2.2.2 mjf #define F1_5280_5320 AFTER(F3_5260_5700) 895 1.2.2.2 mjf 896 1.2.2.2 mjf { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 }, 897 1.2.2.2 mjf #define F1_5500_5620 AFTER(F1_5280_5320) 898 1.2.2.2 mjf 899 1.2.2.2 mjf { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4 }, 900 1.2.2.2 mjf #define F1_5500_5700 AFTER(F1_5500_5620) 901 1.2.2.2 mjf { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 }, 902 1.2.2.2 mjf #define F2_5500_5700 AFTER(F1_5500_5700) 903 1.2.2.2 mjf { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 }, 904 1.2.2.2 mjf #define F3_5500_5700 AFTER(F2_5500_5700) 905 1.2.2.2 mjf { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0 }, 906 1.2.2.2 mjf #define F4_5500_5700 AFTER(F3_5500_5700) 907 1.2.2.2 mjf 908 1.2.2.2 mjf { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0 }, 909 1.2.2.2 mjf #define F1_5745_5805 AFTER(F4_5500_5700) 910 1.2.2.2 mjf { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 }, 911 1.2.2.2 mjf #define F2_5745_5805 AFTER(F1_5745_5805) 912 1.2.2.2 mjf { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 }, 913 1.2.2.2 mjf #define F3_5745_5805 AFTER(F2_5745_5805) 914 1.2.2.2 mjf { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0 }, 915 1.2.2.2 mjf #define F1_5745_5825 AFTER(F3_5745_5805) 916 1.2.2.2 mjf { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0 }, 917 1.2.2.2 mjf #define F2_5745_5825 AFTER(F1_5745_5825) 918 1.2.2.2 mjf { 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0 }, 919 1.2.2.2 mjf #define F3_5745_5825 AFTER(F2_5745_5825) 920 1.2.2.2 mjf { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 }, 921 1.2.2.2 mjf #define F4_5745_5825 AFTER(F3_5745_5825) 922 1.2.2.2 mjf { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3 }, 923 1.2.2.2 mjf #define F5_5745_5825 AFTER(F4_5745_5825) 924 1.2.2.2 mjf { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 }, 925 1.2.2.2 mjf #define F6_5745_5825 AFTER(F5_5745_5825) 926 1.2.2.2 mjf { 5745, 5825, 5, 6, 10, 10, NO_DFS, NO_PSCAN, 0 }, 927 1.2.2.2 mjf #define F7_5745_5825 AFTER(F6_5745_5825) 928 1.2.2.2 mjf { 5745, 5825, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0 }, 929 1.2.2.2 mjf #define F8_5745_5825 AFTER(F7_5745_5825) 930 1.2.2.2 mjf { 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN, 3 }, 931 1.2.2.2 mjf #define F9_5745_5825 AFTER(F8_5745_5825) 932 1.2.2.2 mjf { 5745, 5825, 30, 6, 20, 5, NO_DFS, NO_PSCAN, 3 }, 933 1.2.2.2 mjf #define F10_5745_5825 AFTER(F9_5745_5825) 934 1.2.2.2 mjf 935 1.2.2.2 mjf /* 936 1.2.2.2 mjf * Below are the world roaming channels 937 1.2.2.2 mjf * All WWR domains have no power limit, instead use the card's CTL 938 1.2.2.2 mjf * or max power settings. 939 1.2.2.2 mjf */ 940 1.2.2.2 mjf { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 }, 941 1.2.2.2 mjf #define W1_4920_4980 AFTER(F10_5745_5825) 942 1.2.2.2 mjf { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 }, 943 1.2.2.2 mjf #define W1_5040_5080 AFTER(W1_4920_4980) 944 1.2.2.2 mjf { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 }, 945 1.2.2.2 mjf #define W1_5170_5230 AFTER(W1_5040_5080) 946 1.2.2.2 mjf { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 }, 947 1.2.2.2 mjf #define W1_5180_5240 AFTER(W1_5170_5230) 948 1.2.2.2 mjf { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 }, 949 1.2.2.2 mjf #define W1_5260_5320 AFTER(W1_5180_5240) 950 1.2.2.2 mjf { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 }, 951 1.2.2.2 mjf #define W1_5745_5825 AFTER(W1_5260_5320) 952 1.2.2.2 mjf { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 }, 953 1.2.2.2 mjf #define W1_5500_5700 AFTER(W1_5745_5825) 954 1.2.2.2 mjf { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 }, 955 1.2.2.2 mjf #define W2_5260_5320 AFTER(W1_5500_5700) 956 1.2.2.2 mjf { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 }, 957 1.2.2.2 mjf #define W2_5180_5240 AFTER(W2_5260_5320) 958 1.2.2.2 mjf { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 }, 959 1.2.2.2 mjf #define W2_5825_5825 AFTER(W2_5180_5240) 960 1.2.2.2 mjf }; 961 1.2.2.2 mjf 962 1.2.2.2 mjf /* 963 1.2.2.2 mjf * 5GHz Turbo (dynamic & static) tags 964 1.2.2.2 mjf */ 965 1.2.2.2 mjf static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { 966 1.2.2.2 mjf { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 967 1.2.2.2 mjf #define T1_5130_5210 0 968 1.2.2.2 mjf { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0}, 969 1.2.2.2 mjf #define T1_5250_5330 AFTER(T1_5130_5210) 970 1.2.2.2 mjf { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 971 1.2.2.2 mjf #define T1_5370_5490 AFTER(T1_5250_5330) 972 1.2.2.2 mjf { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0}, 973 1.2.2.2 mjf #define T1_5530_5650 AFTER(T1_5370_5490) 974 1.2.2.2 mjf 975 1.2.2.2 mjf { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 976 1.2.2.2 mjf #define T1_5150_5190 AFTER(T1_5530_5650) 977 1.2.2.2 mjf { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0}, 978 1.2.2.2 mjf #define T1_5230_5310 AFTER(T1_5150_5190) 979 1.2.2.2 mjf { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 980 1.2.2.2 mjf #define T1_5350_5470 AFTER(T1_5230_5310) 981 1.2.2.2 mjf { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0}, 982 1.2.2.2 mjf #define T1_5510_5670 AFTER(T1_5350_5470) 983 1.2.2.2 mjf 984 1.2.2.2 mjf { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 985 1.2.2.2 mjf #define T1_5200_5240 AFTER(T1_5510_5670) 986 1.2.2.2 mjf { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 987 1.2.2.2 mjf #define T2_5200_5240 AFTER(T1_5200_5240) 988 1.2.2.2 mjf { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 989 1.2.2.2 mjf #define T1_5210_5210 AFTER(T2_5200_5240) 990 1.2.2.2 mjf { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0}, 991 1.2.2.2 mjf #define T2_5210_5210 AFTER(T1_5210_5210) 992 1.2.2.2 mjf 993 1.2.2.2 mjf { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0}, 994 1.2.2.2 mjf #define T1_5280_5280 AFTER(T2_5210_5210) 995 1.2.2.2 mjf { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0}, 996 1.2.2.2 mjf #define T2_5280_5280 AFTER(T1_5280_5280) 997 1.2.2.2 mjf { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0}, 998 1.2.2.2 mjf #define T1_5250_5250 AFTER(T2_5280_5280) 999 1.2.2.2 mjf { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0}, 1000 1.2.2.2 mjf #define T1_5290_5290 AFTER(T1_5250_5250) 1001 1.2.2.2 mjf { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0}, 1002 1.2.2.2 mjf #define T1_5250_5290 AFTER(T1_5290_5290) 1003 1.2.2.2 mjf { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0}, 1004 1.2.2.2 mjf #define T2_5250_5290 AFTER(T1_5250_5290) 1005 1.2.2.2 mjf 1006 1.2.2.2 mjf { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0}, 1007 1.2.2.2 mjf #define T1_5540_5660 AFTER(T2_5250_5290) 1008 1.2.2.2 mjf { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0}, 1009 1.2.2.2 mjf #define T1_5760_5800 AFTER(T1_5540_5660) 1010 1.2.2.2 mjf { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 1011 1.2.2.2 mjf #define T2_5760_5800 AFTER(T1_5760_5800) 1012 1.2.2.2 mjf 1013 1.2.2.2 mjf { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 1014 1.2.2.2 mjf #define T1_5765_5805 AFTER(T2_5760_5800) 1015 1.2.2.2 mjf 1016 1.2.2.2 mjf /* 1017 1.2.2.2 mjf * Below are the WWR frequencies 1018 1.2.2.2 mjf */ 1019 1.2.2.2 mjf { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0}, 1020 1.2.2.2 mjf #define WT1_5210_5250 AFTER(T1_5765_5805) 1021 1.2.2.2 mjf { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0}, 1022 1.2.2.2 mjf #define WT1_5290_5290 AFTER(WT1_5210_5250) 1023 1.2.2.2 mjf { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0}, 1024 1.2.2.2 mjf #define WT1_5540_5660 AFTER(WT1_5290_5290) 1025 1.2.2.2 mjf { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR, 0}, 1026 1.2.2.2 mjf #define WT1_5760_5800 AFTER(WT1_5540_5660) 1027 1.2.2.2 mjf }; 1028 1.2.2.2 mjf 1029 1.2.2.2 mjf /* 1030 1.2.2.2 mjf * 2GHz 11b channel tags 1031 1.2.2.2 mjf */ 1032 1.2.2.2 mjf static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = { 1033 1.2.2.2 mjf { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1034 1.2.2.2 mjf #define F1_2312_2372 0 1035 1.2.2.2 mjf { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1036 1.2.2.2 mjf #define F2_2312_2372 AFTER(F1_2312_2372) 1037 1.2.2.2 mjf 1038 1.2.2.2 mjf { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1039 1.2.2.2 mjf #define F1_2412_2472 AFTER(F2_2312_2372) 1040 1.2.2.2 mjf { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0}, 1041 1.2.2.2 mjf #define F2_2412_2472 AFTER(F1_2412_2472) 1042 1.2.2.2 mjf { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1043 1.2.2.2 mjf #define F3_2412_2472 AFTER(F2_2412_2472) 1044 1.2.2.2 mjf 1045 1.2.2.2 mjf { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1046 1.2.2.2 mjf #define F1_2412_2462 AFTER(F3_2412_2472) 1047 1.2.2.2 mjf { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0}, 1048 1.2.2.2 mjf #define F2_2412_2462 AFTER(F1_2412_2462) 1049 1.2.2.2 mjf 1050 1.2.2.2 mjf { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1051 1.2.2.2 mjf #define F1_2432_2442 AFTER(F2_2412_2462) 1052 1.2.2.2 mjf 1053 1.2.2.2 mjf { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1054 1.2.2.2 mjf #define F1_2457_2472 AFTER(F1_2432_2442) 1055 1.2.2.2 mjf 1056 1.2.2.2 mjf { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0}, 1057 1.2.2.2 mjf #define F1_2467_2472 AFTER(F1_2457_2472) 1058 1.2.2.2 mjf 1059 1.2.2.2 mjf { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1060 1.2.2.2 mjf #define F1_2484_2484 AFTER(F1_2467_2472) 1061 1.2.2.2 mjf { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0}, 1062 1.2.2.2 mjf #define F2_2484_2484 AFTER(F1_2484_2484) 1063 1.2.2.2 mjf 1064 1.2.2.2 mjf { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1065 1.2.2.2 mjf #define F1_2512_2732 AFTER(F2_2484_2484) 1066 1.2.2.2 mjf 1067 1.2.2.2 mjf /* 1068 1.2.2.2 mjf * WWR have powers opened up to 20dBm. 1069 1.2.2.2 mjf * Limits should often come from CTL/Max powers 1070 1.2.2.2 mjf */ 1071 1.2.2.2 mjf { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1072 1.2.2.2 mjf #define W1_2312_2372 AFTER(F1_2512_2732) 1073 1.2.2.2 mjf { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1074 1.2.2.2 mjf #define W1_2412_2412 AFTER(W1_2312_2372) 1075 1.2.2.2 mjf { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1076 1.2.2.2 mjf #define W1_2417_2432 AFTER(W1_2412_2412) 1077 1.2.2.2 mjf { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1078 1.2.2.2 mjf #define W1_2437_2442 AFTER(W1_2417_2432) 1079 1.2.2.2 mjf { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1080 1.2.2.2 mjf #define W1_2447_2457 AFTER(W1_2437_2442) 1081 1.2.2.2 mjf { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1082 1.2.2.2 mjf #define W1_2462_2462 AFTER(W1_2447_2457) 1083 1.2.2.2 mjf { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, 1084 1.2.2.2 mjf #define W1_2467_2467 AFTER(W1_2462_2462) 1085 1.2.2.2 mjf { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, 1086 1.2.2.2 mjf #define W2_2467_2467 AFTER(W1_2467_2467) 1087 1.2.2.2 mjf { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, 1088 1.2.2.2 mjf #define W1_2472_2472 AFTER(W2_2467_2467) 1089 1.2.2.2 mjf { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, 1090 1.2.2.2 mjf #define W2_2472_2472 AFTER(W1_2472_2472) 1091 1.2.2.2 mjf { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, 1092 1.2.2.2 mjf #define W1_2484_2484 AFTER(W2_2472_2472) 1093 1.2.2.2 mjf { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, 1094 1.2.2.2 mjf #define W2_2484_2484 AFTER(W1_2484_2484) 1095 1.2.2.2 mjf }; 1096 1.2.2.2 mjf 1097 1.2.2.2 mjf /* 1098 1.2.2.2 mjf * 2GHz 11g channel tags 1099 1.2.2.2 mjf */ 1100 1.2.2.2 mjf static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = { 1101 1.2.2.2 mjf { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1102 1.2.2.2 mjf #define G1_2312_2372 0 1103 1.2.2.2 mjf { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1104 1.2.2.2 mjf #define G2_2312_2372 AFTER(G1_2312_2372) 1105 1.2.2.2 mjf { 2312, 2372, 5, 6, 10, 5, NO_DFS, NO_PSCAN, 0}, 1106 1.2.2.2 mjf #define G3_2312_2372 AFTER(G2_2312_2372) 1107 1.2.2.2 mjf { 2312, 2372, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0}, 1108 1.2.2.2 mjf #define G4_2312_2372 AFTER(G3_2312_2372) 1109 1.2.2.2 mjf 1110 1.2.2.2 mjf { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1111 1.2.2.2 mjf #define G1_2412_2472 AFTER(G4_2312_2372) 1112 1.2.2.2 mjf { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0}, 1113 1.2.2.2 mjf #define G2_2412_2472 AFTER(G1_2412_2472) 1114 1.2.2.2 mjf { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1115 1.2.2.2 mjf #define G3_2412_2472 AFTER(G2_2412_2472) 1116 1.2.2.2 mjf { 2412, 2472, 5, 6, 10, 5, NO_DFS, NO_PSCAN, 0}, 1117 1.2.2.2 mjf #define G4_2412_2472 AFTER(G3_2412_2472) 1118 1.2.2.2 mjf { 2412, 2472, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0}, 1119 1.2.2.2 mjf #define G5_2412_2472 AFTER(G4_2412_2472) 1120 1.2.2.2 mjf 1121 1.2.2.2 mjf { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1122 1.2.2.2 mjf #define G1_2412_2462 AFTER(G5_2412_2472) 1123 1.2.2.2 mjf { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0}, 1124 1.2.2.2 mjf #define G2_2412_2462 AFTER(G1_2412_2462) 1125 1.2.2.2 mjf { 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN, 0}, 1126 1.2.2.2 mjf #define G3_2412_2462 AFTER(G2_2412_2462) 1127 1.2.2.2 mjf { 2412, 2462, 27, 6, 5, 5, NO_DFS, NO_PSCAN, 0}, 1128 1.2.2.2 mjf #define G4_2412_2462 AFTER(G3_2412_2462) 1129 1.2.2.2 mjf 1130 1.2.2.2 mjf { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1131 1.2.2.2 mjf #define G1_2432_2442 AFTER(G4_2412_2462) 1132 1.2.2.2 mjf 1133 1.2.2.2 mjf { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1134 1.2.2.2 mjf #define G1_2457_2472 AFTER(G1_2432_2442) 1135 1.2.2.2 mjf 1136 1.2.2.2 mjf { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0}, 1137 1.2.2.2 mjf #define G1_2512_2732 AFTER(G1_2457_2472) 1138 1.2.2.2 mjf { 2512, 2732, 5, 6, 10, 5, NO_DFS, NO_PSCAN, 0}, 1139 1.2.2.2 mjf #define G2_2512_2732 AFTER(G1_2512_2732) 1140 1.2.2.2 mjf { 2512, 2732, 5, 6, 5, 5, NO_DFS, NO_PSCAN, 0}, 1141 1.2.2.2 mjf #define G3_2512_2732 AFTER(G2_2512_2732) 1142 1.2.2.2 mjf 1143 1.2.2.2 mjf { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0 }, 1144 1.2.2.2 mjf #define G1_2467_2472 AFTER(G3_2512_2732) 1145 1.2.2.2 mjf 1146 1.2.2.2 mjf /* 1147 1.2.2.2 mjf * WWR open up the power to 20dBm 1148 1.2.2.2 mjf */ 1149 1.2.2.2 mjf { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1150 1.2.2.2 mjf #define WG1_2312_2372 AFTER(G1_2467_2472) 1151 1.2.2.2 mjf { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1152 1.2.2.2 mjf #define WG1_2412_2412 AFTER(WG1_2312_2372) 1153 1.2.2.2 mjf { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1154 1.2.2.2 mjf #define WG1_2417_2432 AFTER(WG1_2412_2412) 1155 1.2.2.2 mjf { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1156 1.2.2.2 mjf #define WG1_2437_2442 AFTER(WG1_2417_2432) 1157 1.2.2.2 mjf { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1158 1.2.2.2 mjf #define WG1_2447_2457 AFTER(WG1_2437_2442) 1159 1.2.2.2 mjf { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0}, 1160 1.2.2.2 mjf #define WG1_2462_2462 AFTER(WG1_2447_2457) 1161 1.2.2.2 mjf { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, 1162 1.2.2.2 mjf #define WG1_2467_2467 AFTER(WG1_2462_2462) 1163 1.2.2.2 mjf { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, 1164 1.2.2.2 mjf #define WG2_2467_2467 AFTER(WG1_2467_2467) 1165 1.2.2.2 mjf { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0}, 1166 1.2.2.2 mjf #define WG1_2472_2472 AFTER(WG2_2467_2467) 1167 1.2.2.2 mjf { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0}, 1168 1.2.2.2 mjf #define WG2_2472_2472 AFTER(WG1_2472_2472) 1169 1.2.2.2 mjf 1170 1.2.2.2 mjf /* 1171 1.2.2.2 mjf * Mapping for 900MHz cards like Ubiquiti SR9 and XR9 1172 1.2.2.2 mjf * and ZComax GZ-901. 1173 1.2.2.2 mjf */ 1174 1.2.2.2 mjf { 2422, 2437, 30, 0, 5, 5, NO_DFS, PSCAN_FCC, 0 }, 1175 1.2.2.2 mjf #define S1_907_922_5 AFTER(WG2_2472_2472) 1176 1.2.2.2 mjf { 2422, 2437, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 }, 1177 1.2.2.2 mjf #define S1_907_922_10 AFTER(S1_907_922_5) 1178 1.2.2.2 mjf { 2427, 2432, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 }, 1179 1.2.2.2 mjf #define S1_912_917 AFTER(S1_907_922_10) 1180 1.2.2.2 mjf { 2427, 2442, 30, 0, 5, 5, NO_DFS, PSCAN_FCC, 0 }, 1181 1.2.2.2 mjf #define S2_907_922_5 AFTER(S1_912_917) 1182 1.2.2.2 mjf { 2427, 2442, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 }, 1183 1.2.2.2 mjf #define S2_907_922_10 AFTER(S2_907_922_5) 1184 1.2.2.2 mjf { 2432, 2437, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 }, 1185 1.2.2.2 mjf #define S2_912_917 AFTER(S2_907_922_10) 1186 1.2.2.2 mjf { 2452, 2467, 30, 0, 5, 5, NO_DFS, PSCAN_FCC, 0 }, 1187 1.2.2.2 mjf #define S1_908_923_5 AFTER(S2_912_917) 1188 1.2.2.2 mjf { 2457, 2467, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 }, 1189 1.2.2.2 mjf #define S1_913_918_10 AFTER(S1_908_923_5) 1190 1.2.2.2 mjf { 2457, 2467, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 }, 1191 1.2.2.2 mjf #define S1_913_918 AFTER(S1_913_918_10) 1192 1.2.2.2 mjf }; 1193 1.2.2.2 mjf 1194 1.2.2.2 mjf /* 1195 1.2.2.2 mjf * 2GHz Dynamic turbo tags 1196 1.2.2.2 mjf */ 1197 1.2.2.2 mjf static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = { 1198 1.2.2.2 mjf { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 1199 1.2.2.2 mjf #define T1_2312_2372 0 1200 1.2.2.2 mjf { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 1201 1.2.2.2 mjf #define T1_2437_2437 AFTER(T1_2312_2372) 1202 1.2.2.2 mjf { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 1203 1.2.2.2 mjf #define T2_2437_2437 AFTER(T1_2437_2437) 1204 1.2.2.2 mjf { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR, 0}, 1205 1.2.2.2 mjf #define T3_2437_2437 AFTER(T2_2437_2437) 1206 1.2.2.2 mjf { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0}, 1207 1.2.2.2 mjf #define T1_2512_2732 AFTER(T3_2437_2437) 1208 1.2.2.2 mjf }; 1209 1.2.2.2 mjf 1210 1.2.2.2 mjf typedef struct regDomain { 1211 1.2.2.2 mjf uint16_t regDmnEnum; /* value from EnumRd table */ 1212 1.2.2.2 mjf uint8_t conformanceTestLimit; 1213 1.2.2.2 mjf uint32_t flags; /* Requirement flags (AdHoc disallow, 1214 1.2.2.2 mjf noise floor cal needed, etc) */ 1215 1.2.2.2 mjf uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */ 1216 1.2.2.2 mjf uint64_t pscan; /* Bitmask for passive scan */ 1217 1.2.2.2 mjf chanbmask_t chan11a; /* 11a channels */ 1218 1.2.2.2 mjf chanbmask_t chan11a_turbo; /* 11a static turbo channels */ 1219 1.2.2.2 mjf chanbmask_t chan11a_dyn_turbo; /* 11a dynamic turbo channels */ 1220 1.2.2.2 mjf chanbmask_t chan11a_half; /* 11a 1/2 width channels */ 1221 1.2.2.2 mjf chanbmask_t chan11a_quarter; /* 11a 1/4 width channels */ 1222 1.2.2.2 mjf chanbmask_t chan11b; /* 11b channels */ 1223 1.2.2.2 mjf chanbmask_t chan11g; /* 11g channels */ 1224 1.2.2.2 mjf chanbmask_t chan11g_turbo; /* 11g dynamic turbo channels */ 1225 1.2.2.2 mjf chanbmask_t chan11g_half; /* 11g 1/2 width channels */ 1226 1.2.2.2 mjf chanbmask_t chan11g_quarter; /* 11g 1/4 width channels */ 1227 1.2.2.2 mjf } REG_DOMAIN; 1228 1.2.2.2 mjf 1229 1.2.2.2 mjf static REG_DOMAIN regDomains[] = { 1230 1.2.2.2 mjf 1231 1.2.2.2 mjf {.regDmnEnum = DEBUG_REG_DMN, 1232 1.2.2.2 mjf .conformanceTestLimit = FCC, 1233 1.2.2.2 mjf .dfsMask = DFS_FCC3, 1234 1.2.2.2 mjf .chan11a = BM3(F1_5120_5240, F1_5260_5700, F1_5745_5825), 1235 1.2.2.2 mjf .chan11a_half = BM3(F2_5120_5240, F2_5260_5700, F7_5745_5825), 1236 1.2.2.2 mjf .chan11a_quarter = BM3(F3_5120_5240, F3_5260_5700, F8_5745_5825), 1237 1.2.2.2 mjf .chan11a_turbo = BM8(T1_5130_5210, 1238 1.2.2.2 mjf T1_5250_5330, 1239 1.2.2.2 mjf T1_5370_5490, 1240 1.2.2.2 mjf T1_5530_5650, 1241 1.2.2.2 mjf T1_5150_5190, 1242 1.2.2.2 mjf T1_5230_5310, 1243 1.2.2.2 mjf T1_5350_5470, 1244 1.2.2.2 mjf T1_5510_5670), 1245 1.2.2.2 mjf .chan11a_dyn_turbo = BM4(T1_5200_5240, 1246 1.2.2.2 mjf T1_5280_5280, 1247 1.2.2.2 mjf T1_5540_5660, 1248 1.2.2.2 mjf T1_5765_5805), 1249 1.2.2.2 mjf .chan11b = BM4(F1_2312_2372, 1250 1.2.2.2 mjf F1_2412_2472, 1251 1.2.2.2 mjf F1_2484_2484, 1252 1.2.2.2 mjf F1_2512_2732), 1253 1.2.2.2 mjf .chan11g = BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732), 1254 1.2.2.2 mjf .chan11g_turbo = BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732), 1255 1.2.2.2 mjf .chan11g_half = BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732), 1256 1.2.2.2 mjf .chan11g_quarter = BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732), 1257 1.2.2.2 mjf }, 1258 1.2.2.2 mjf 1259 1.2.2.2 mjf {.regDmnEnum = APL1, 1260 1.2.2.2 mjf .conformanceTestLimit = FCC, 1261 1.2.2.2 mjf .chan11a = BM1(F4_5745_5825), 1262 1.2.2.2 mjf }, 1263 1.2.2.2 mjf 1264 1.2.2.2 mjf {.regDmnEnum = APL2, 1265 1.2.2.2 mjf .conformanceTestLimit = FCC, 1266 1.2.2.2 mjf .chan11a = BM1(F1_5745_5805), 1267 1.2.2.2 mjf }, 1268 1.2.2.2 mjf 1269 1.2.2.2 mjf {.regDmnEnum = APL3, 1270 1.2.2.2 mjf .conformanceTestLimit = FCC, 1271 1.2.2.2 mjf .chan11a = BM2(F1_5280_5320, F2_5745_5805), 1272 1.2.2.2 mjf }, 1273 1.2.2.2 mjf 1274 1.2.2.2 mjf {.regDmnEnum = APL4, 1275 1.2.2.2 mjf .conformanceTestLimit = FCC, 1276 1.2.2.2 mjf .chan11a = BM2(F4_5180_5240, F3_5745_5825), 1277 1.2.2.2 mjf }, 1278 1.2.2.2 mjf 1279 1.2.2.2 mjf {.regDmnEnum = APL5, 1280 1.2.2.2 mjf .conformanceTestLimit = FCC, 1281 1.2.2.2 mjf .chan11a = BM1(F2_5745_5825), 1282 1.2.2.2 mjf }, 1283 1.2.2.2 mjf 1284 1.2.2.2 mjf {.regDmnEnum = APL6, 1285 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1286 1.2.2.2 mjf .dfsMask = DFS_ETSI, 1287 1.2.2.2 mjf .pscan = PSCAN_FCC_T | PSCAN_FCC, 1288 1.2.2.2 mjf .chan11a = BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825), 1289 1.2.2.2 mjf .chan11a_turbo = BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800), 1290 1.2.2.2 mjf }, 1291 1.2.2.2 mjf 1292 1.2.2.2 mjf {.regDmnEnum = APL8, 1293 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1294 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 1295 1.2.2.2 mjf .chan11a = BM2(F6_5260_5320, F4_5745_5825), 1296 1.2.2.2 mjf }, 1297 1.2.2.2 mjf 1298 1.2.2.2 mjf {.regDmnEnum = APL9, 1299 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1300 1.2.2.2 mjf .dfsMask = DFS_ETSI, 1301 1.2.2.2 mjf .pscan = PSCAN_ETSI, 1302 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 1303 1.2.2.2 mjf .chan11a = BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805), 1304 1.2.2.2 mjf }, 1305 1.2.2.2 mjf 1306 1.2.2.2 mjf {.regDmnEnum = ETSI1, 1307 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1308 1.2.2.2 mjf .dfsMask = DFS_ETSI, 1309 1.2.2.2 mjf .pscan = PSCAN_ETSI, 1310 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1311 1.2.2.2 mjf .chan11a = BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700), 1312 1.2.2.2 mjf }, 1313 1.2.2.2 mjf 1314 1.2.2.2 mjf {.regDmnEnum = ETSI2, 1315 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1316 1.2.2.2 mjf .dfsMask = DFS_ETSI, 1317 1.2.2.2 mjf .pscan = PSCAN_ETSI, 1318 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1319 1.2.2.2 mjf .chan11a = BM1(F3_5180_5240), 1320 1.2.2.2 mjf }, 1321 1.2.2.2 mjf 1322 1.2.2.2 mjf {.regDmnEnum = ETSI3, 1323 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1324 1.2.2.2 mjf .dfsMask = DFS_ETSI, 1325 1.2.2.2 mjf .pscan = PSCAN_ETSI, 1326 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1327 1.2.2.2 mjf .chan11a = BM2(W2_5180_5240, F2_5260_5320), 1328 1.2.2.2 mjf }, 1329 1.2.2.2 mjf 1330 1.2.2.2 mjf {.regDmnEnum = ETSI4, 1331 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1332 1.2.2.2 mjf .dfsMask = DFS_ETSI, 1333 1.2.2.2 mjf .pscan = PSCAN_ETSI, 1334 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1335 1.2.2.2 mjf .chan11a = BM2(F3_5180_5240, F1_5260_5320), 1336 1.2.2.2 mjf }, 1337 1.2.2.2 mjf 1338 1.2.2.2 mjf {.regDmnEnum = ETSI5, 1339 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1340 1.2.2.2 mjf .dfsMask = DFS_ETSI, 1341 1.2.2.2 mjf .pscan = PSCAN_ETSI, 1342 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1343 1.2.2.2 mjf .chan11a = BM1(F1_5180_5240), 1344 1.2.2.2 mjf }, 1345 1.2.2.2 mjf 1346 1.2.2.2 mjf {.regDmnEnum = ETSI6, 1347 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1348 1.2.2.2 mjf .dfsMask = DFS_ETSI, 1349 1.2.2.2 mjf .pscan = PSCAN_ETSI, 1350 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1351 1.2.2.2 mjf .chan11a = BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700), 1352 1.2.2.2 mjf }, 1353 1.2.2.2 mjf 1354 1.2.2.2 mjf {.regDmnEnum = FCC1, 1355 1.2.2.2 mjf .conformanceTestLimit = FCC, 1356 1.2.2.2 mjf .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 1357 1.2.2.2 mjf .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 1358 1.2.2.2 mjf .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 1359 1.2.2.2 mjf }, 1360 1.2.2.2 mjf 1361 1.2.2.2 mjf {.regDmnEnum = FCC2, 1362 1.2.2.2 mjf .conformanceTestLimit = FCC, 1363 1.2.2.2 mjf .chan11a = BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825), 1364 1.2.2.2 mjf .chan11a_dyn_turbo = BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805), 1365 1.2.2.2 mjf }, 1366 1.2.2.2 mjf 1367 1.2.2.2 mjf {.regDmnEnum = FCC3, 1368 1.2.2.2 mjf .conformanceTestLimit = FCC, 1369 1.2.2.2 mjf .dfsMask = DFS_FCC3, 1370 1.2.2.2 mjf .pscan = PSCAN_FCC | PSCAN_FCC_T, 1371 1.2.2.2 mjf .chan11a = BM4(F2_5180_5240, 1372 1.2.2.2 mjf F3_5260_5320, 1373 1.2.2.2 mjf F1_5500_5700, 1374 1.2.2.2 mjf F5_5745_5825), 1375 1.2.2.2 mjf .chan11a_turbo = BM4(T1_5210_5210, 1376 1.2.2.2 mjf T1_5250_5250, 1377 1.2.2.2 mjf T1_5290_5290, 1378 1.2.2.2 mjf T2_5760_5800), 1379 1.2.2.2 mjf .chan11a_dyn_turbo = BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660), 1380 1.2.2.2 mjf }, 1381 1.2.2.2 mjf 1382 1.2.2.2 mjf {.regDmnEnum = FCC4, 1383 1.2.2.2 mjf .conformanceTestLimit = FCC, 1384 1.2.2.2 mjf .dfsMask = DFS_FCC3, 1385 1.2.2.2 mjf .pscan = PSCAN_FCC | PSCAN_FCC_T, 1386 1.2.2.2 mjf .chan11a = BM1(F1_4950_4980), 1387 1.2.2.2 mjf .chan11a_half = BM1(F1_4945_4985), 1388 1.2.2.2 mjf .chan11a_quarter = BM1(F1_4942_4987), 1389 1.2.2.2 mjf }, 1390 1.2.2.2 mjf 1391 1.2.2.2 mjf /* FCC1 w/ 1/2 and 1/4 width channels */ 1392 1.2.2.2 mjf {.regDmnEnum = FCC5, 1393 1.2.2.2 mjf .conformanceTestLimit = FCC, 1394 1.2.2.2 mjf .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 1395 1.2.2.2 mjf .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 1396 1.2.2.2 mjf .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 1397 1.2.2.2 mjf .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 1398 1.2.2.2 mjf .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 1399 1.2.2.2 mjf }, 1400 1.2.2.2 mjf 1401 1.2.2.2 mjf {.regDmnEnum = MKK1, 1402 1.2.2.2 mjf .conformanceTestLimit = MKK, 1403 1.2.2.2 mjf .pscan = PSCAN_MKK1, 1404 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1405 1.2.2.2 mjf .chan11a = BM1(F1_5170_5230), 1406 1.2.2.2 mjf }, 1407 1.2.2.2 mjf 1408 1.2.2.2 mjf {.regDmnEnum = MKK2, 1409 1.2.2.2 mjf .conformanceTestLimit = MKK, 1410 1.2.2.2 mjf .pscan = PSCAN_MKK2, 1411 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1412 1.2.2.2 mjf .chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230), 1413 1.2.2.2 mjf .chan11a_half = BM4(F1_4915_4925, 1414 1.2.2.2 mjf F1_4935_4945, 1415 1.2.2.2 mjf F1_5035_5040, 1416 1.2.2.2 mjf F1_5055_5055), 1417 1.2.2.2 mjf }, 1418 1.2.2.2 mjf 1419 1.2.2.2 mjf /* UNI-1 even */ 1420 1.2.2.2 mjf {.regDmnEnum = MKK3, 1421 1.2.2.2 mjf .conformanceTestLimit = MKK, 1422 1.2.2.2 mjf .pscan = PSCAN_MKK3, 1423 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1424 1.2.2.2 mjf .chan11a = BM1(F4_5180_5240), 1425 1.2.2.2 mjf }, 1426 1.2.2.2 mjf 1427 1.2.2.2 mjf /* UNI-1 even + UNI-2 */ 1428 1.2.2.2 mjf {.regDmnEnum = MKK4, 1429 1.2.2.2 mjf .conformanceTestLimit = MKK, 1430 1.2.2.2 mjf .dfsMask = DFS_MKK4, 1431 1.2.2.2 mjf .pscan = PSCAN_MKK3, 1432 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1433 1.2.2.2 mjf .chan11a = BM2(F4_5180_5240, F2_5260_5320), 1434 1.2.2.2 mjf }, 1435 1.2.2.2 mjf 1436 1.2.2.2 mjf /* UNI-1 even + UNI-2 + mid-band */ 1437 1.2.2.2 mjf {.regDmnEnum = MKK5, 1438 1.2.2.2 mjf .conformanceTestLimit = MKK, 1439 1.2.2.2 mjf .dfsMask = DFS_MKK4, 1440 1.2.2.2 mjf .pscan = PSCAN_MKK3, 1441 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1442 1.2.2.2 mjf .chan11a = BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700), 1443 1.2.2.2 mjf }, 1444 1.2.2.2 mjf 1445 1.2.2.2 mjf /* UNI-1 odd + even */ 1446 1.2.2.2 mjf {.regDmnEnum = MKK6, 1447 1.2.2.2 mjf .conformanceTestLimit = MKK, 1448 1.2.2.2 mjf .pscan = PSCAN_MKK1, 1449 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1450 1.2.2.2 mjf .chan11a = BM2(F2_5170_5230, F4_5180_5240), 1451 1.2.2.2 mjf }, 1452 1.2.2.2 mjf 1453 1.2.2.2 mjf /* UNI-1 odd + UNI-1 even + UNI-2 */ 1454 1.2.2.2 mjf {.regDmnEnum = MKK7, 1455 1.2.2.2 mjf .conformanceTestLimit = MKK, 1456 1.2.2.2 mjf .dfsMask = DFS_MKK4, 1457 1.2.2.2 mjf .pscan = PSCAN_MKK1 | PSCAN_MKK3, 1458 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1459 1.2.2.2 mjf .chan11a = BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320), 1460 1.2.2.2 mjf }, 1461 1.2.2.2 mjf 1462 1.2.2.2 mjf /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ 1463 1.2.2.2 mjf {.regDmnEnum = MKK8, 1464 1.2.2.2 mjf .conformanceTestLimit = MKK, 1465 1.2.2.2 mjf .dfsMask = DFS_MKK4, 1466 1.2.2.2 mjf .pscan = PSCAN_MKK1 | PSCAN_MKK3, 1467 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1468 1.2.2.2 mjf .chan11a = BM4(F1_5170_5230, 1469 1.2.2.2 mjf F4_5180_5240, 1470 1.2.2.2 mjf F2_5260_5320, 1471 1.2.2.2 mjf F4_5500_5700), 1472 1.2.2.2 mjf }, 1473 1.2.2.2 mjf 1474 1.2.2.2 mjf /* UNI-1 even + 4.9 GHZ */ 1475 1.2.2.2 mjf {.regDmnEnum = MKK9, 1476 1.2.2.2 mjf .conformanceTestLimit = MKK, 1477 1.2.2.2 mjf .pscan = PSCAN_MKK3, 1478 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1479 1.2.2.2 mjf .chan11a = BM7(F1_4915_4925, 1480 1.2.2.2 mjf F1_4935_4945, 1481 1.2.2.2 mjf F1_4920_4980, 1482 1.2.2.2 mjf F1_5035_5040, 1483 1.2.2.2 mjf F1_5055_5055, 1484 1.2.2.2 mjf F1_5040_5080, 1485 1.2.2.2 mjf F4_5180_5240), 1486 1.2.2.2 mjf }, 1487 1.2.2.2 mjf 1488 1.2.2.2 mjf /* UNI-1 even + UNI-2 + 4.9 GHZ */ 1489 1.2.2.2 mjf {.regDmnEnum = MKK10, 1490 1.2.2.2 mjf .conformanceTestLimit = MKK, 1491 1.2.2.2 mjf .dfsMask = DFS_MKK4, 1492 1.2.2.2 mjf .pscan = PSCAN_MKK3, 1493 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1494 1.2.2.2 mjf .chan11a = BM8(F1_4915_4925, 1495 1.2.2.2 mjf F1_4935_4945, 1496 1.2.2.2 mjf F1_4920_4980, 1497 1.2.2.2 mjf F1_5035_5040, 1498 1.2.2.2 mjf F1_5055_5055, 1499 1.2.2.2 mjf F1_5040_5080, 1500 1.2.2.2 mjf F4_5180_5240, 1501 1.2.2.2 mjf F2_5260_5320), 1502 1.2.2.2 mjf }, 1503 1.2.2.2 mjf 1504 1.2.2.2 mjf /* Defined here to use when 2G channels are authorised for country K2 */ 1505 1.2.2.2 mjf {.regDmnEnum = APLD, 1506 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1507 1.2.2.2 mjf .chan11b = BM2(F2_2312_2372,F2_2412_2472), 1508 1.2.2.2 mjf .chan11g = BM2(G2_2312_2372,G2_2412_2472), 1509 1.2.2.2 mjf }, 1510 1.2.2.2 mjf 1511 1.2.2.2 mjf {.regDmnEnum = ETSIA, 1512 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1513 1.2.2.2 mjf .pscan = PSCAN_ETSIA, 1514 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1515 1.2.2.2 mjf .chan11b = BM1(F1_2457_2472), 1516 1.2.2.2 mjf .chan11g = BM1(G1_2457_2472), 1517 1.2.2.2 mjf .chan11g_turbo = BM1(T2_2437_2437) 1518 1.2.2.2 mjf }, 1519 1.2.2.2 mjf 1520 1.2.2.2 mjf {.regDmnEnum = ETSIB, 1521 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1522 1.2.2.2 mjf .pscan = PSCAN_ETSIB, 1523 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1524 1.2.2.2 mjf .chan11b = BM1(F1_2432_2442), 1525 1.2.2.2 mjf .chan11g = BM1(G1_2432_2442), 1526 1.2.2.2 mjf .chan11g_turbo = BM1(T2_2437_2437) 1527 1.2.2.2 mjf }, 1528 1.2.2.2 mjf 1529 1.2.2.2 mjf {.regDmnEnum = ETSIC, 1530 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1531 1.2.2.2 mjf .pscan = PSCAN_ETSIC, 1532 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1533 1.2.2.2 mjf .chan11b = BM1(F3_2412_2472), 1534 1.2.2.2 mjf .chan11g = BM1(G3_2412_2472), 1535 1.2.2.2 mjf .chan11g_turbo = BM1(T2_2437_2437) 1536 1.2.2.2 mjf }, 1537 1.2.2.2 mjf 1538 1.2.2.2 mjf {.regDmnEnum = FCCA, 1539 1.2.2.2 mjf .conformanceTestLimit = FCC, 1540 1.2.2.2 mjf .chan11b = BM1(F1_2412_2462), 1541 1.2.2.2 mjf .chan11g = BM1(G1_2412_2462), 1542 1.2.2.2 mjf .chan11g_turbo = BM1(T2_2437_2437), 1543 1.2.2.2 mjf }, 1544 1.2.2.2 mjf 1545 1.2.2.2 mjf /* FCCA w/ 1/2 and 1/4 width channels */ 1546 1.2.2.2 mjf {.regDmnEnum = FCCB, 1547 1.2.2.2 mjf .conformanceTestLimit = FCC, 1548 1.2.2.2 mjf .chan11b = BM1(F1_2412_2462), 1549 1.2.2.2 mjf .chan11g = BM1(G1_2412_2462), 1550 1.2.2.2 mjf .chan11g_turbo = BM1(T2_2437_2437), 1551 1.2.2.2 mjf .chan11g_half = BM1(G3_2412_2462), 1552 1.2.2.2 mjf .chan11g_quarter = BM1(G4_2412_2462), 1553 1.2.2.2 mjf }, 1554 1.2.2.2 mjf 1555 1.2.2.2 mjf {.regDmnEnum = MKKA, 1556 1.2.2.2 mjf .conformanceTestLimit = MKK, 1557 1.2.2.2 mjf .pscan = PSCAN_MKKA | PSCAN_MKKA_G 1558 1.2.2.2 mjf | PSCAN_MKKA1 | PSCAN_MKKA1_G 1559 1.2.2.2 mjf | PSCAN_MKKA2 | PSCAN_MKKA2_G, 1560 1.2.2.2 mjf .flags = DISALLOW_ADHOC_11A_TURB, 1561 1.2.2.2 mjf .chan11b = BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484), 1562 1.2.2.2 mjf .chan11g = BM2(G2_2412_2462, G1_2467_2472), 1563 1.2.2.2 mjf .chan11g_turbo = BM1(T2_2437_2437) 1564 1.2.2.2 mjf }, 1565 1.2.2.2 mjf 1566 1.2.2.2 mjf {.regDmnEnum = MKKC, 1567 1.2.2.2 mjf .conformanceTestLimit = MKK, 1568 1.2.2.2 mjf .chan11b = BM1(F2_2412_2472), 1569 1.2.2.2 mjf .chan11g = BM1(G2_2412_2472), 1570 1.2.2.2 mjf .chan11g_turbo = BM1(T2_2437_2437) 1571 1.2.2.2 mjf }, 1572 1.2.2.2 mjf 1573 1.2.2.2 mjf {.regDmnEnum = WORLD, 1574 1.2.2.2 mjf .conformanceTestLimit = ETSI, 1575 1.2.2.2 mjf .chan11b = BM1(F2_2412_2472), 1576 1.2.2.2 mjf .chan11g = BM1(G2_2412_2472), 1577 1.2.2.2 mjf .chan11g_turbo = BM1(T2_2437_2437) 1578 1.2.2.2 mjf }, 1579 1.2.2.2 mjf 1580 1.2.2.2 mjf {.regDmnEnum = WOR0_WORLD, 1581 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1582 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1583 1.2.2.2 mjf .pscan = PSCAN_WWR, 1584 1.2.2.2 mjf .flags = ADHOC_PER_11D, 1585 1.2.2.2 mjf .chan11a = BM5(W1_5260_5320, 1586 1.2.2.2 mjf W1_5180_5240, 1587 1.2.2.2 mjf W1_5170_5230, 1588 1.2.2.2 mjf W1_5745_5825, 1589 1.2.2.2 mjf W1_5500_5700), 1590 1.2.2.2 mjf .chan11a_turbo = BM3(WT1_5210_5250, 1591 1.2.2.2 mjf WT1_5290_5290, 1592 1.2.2.2 mjf WT1_5760_5800), 1593 1.2.2.2 mjf .chan11b = BM8(W1_2412_2412, 1594 1.2.2.2 mjf W1_2437_2442, 1595 1.2.2.2 mjf W1_2462_2462, 1596 1.2.2.2 mjf W1_2472_2472, 1597 1.2.2.2 mjf W1_2417_2432, 1598 1.2.2.2 mjf W1_2447_2457, 1599 1.2.2.2 mjf W1_2467_2467, 1600 1.2.2.2 mjf W1_2484_2484), 1601 1.2.2.2 mjf .chan11g = BM7(WG1_2412_2412, 1602 1.2.2.2 mjf WG1_2437_2442, 1603 1.2.2.2 mjf WG1_2462_2462, 1604 1.2.2.2 mjf WG1_2472_2472, 1605 1.2.2.2 mjf WG1_2417_2432, 1606 1.2.2.2 mjf WG1_2447_2457, 1607 1.2.2.2 mjf WG1_2467_2467), 1608 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437) 1609 1.2.2.2 mjf }, 1610 1.2.2.2 mjf 1611 1.2.2.2 mjf {.regDmnEnum = WOR01_WORLD, 1612 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1613 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1614 1.2.2.2 mjf .pscan = PSCAN_WWR, 1615 1.2.2.2 mjf .flags = ADHOC_PER_11D, 1616 1.2.2.2 mjf .chan11a = BM5(W1_5260_5320, 1617 1.2.2.2 mjf W1_5180_5240, 1618 1.2.2.2 mjf W1_5170_5230, 1619 1.2.2.2 mjf W1_5745_5825, 1620 1.2.2.2 mjf W1_5500_5700), 1621 1.2.2.2 mjf .chan11a_turbo = BM3(WT1_5210_5250, 1622 1.2.2.2 mjf WT1_5290_5290, 1623 1.2.2.2 mjf WT1_5760_5800), 1624 1.2.2.2 mjf .chan11b = BM5(W1_2412_2412, 1625 1.2.2.2 mjf W1_2437_2442, 1626 1.2.2.2 mjf W1_2462_2462, 1627 1.2.2.2 mjf W1_2417_2432, 1628 1.2.2.2 mjf W1_2447_2457), 1629 1.2.2.2 mjf .chan11g = BM5(WG1_2412_2412, 1630 1.2.2.2 mjf WG1_2437_2442, 1631 1.2.2.2 mjf WG1_2462_2462, 1632 1.2.2.2 mjf WG1_2417_2432, 1633 1.2.2.2 mjf WG1_2447_2457), 1634 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1635 1.2.2.2 mjf 1636 1.2.2.2 mjf {.regDmnEnum = WOR02_WORLD, 1637 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1638 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1639 1.2.2.2 mjf .pscan = PSCAN_WWR, 1640 1.2.2.2 mjf .flags = ADHOC_PER_11D, 1641 1.2.2.2 mjf .chan11a = BM5(W1_5260_5320, 1642 1.2.2.2 mjf W1_5180_5240, 1643 1.2.2.2 mjf W1_5170_5230, 1644 1.2.2.2 mjf W1_5745_5825, 1645 1.2.2.2 mjf W1_5500_5700), 1646 1.2.2.2 mjf .chan11a_turbo = BM3(WT1_5210_5250, 1647 1.2.2.2 mjf WT1_5290_5290, 1648 1.2.2.2 mjf WT1_5760_5800), 1649 1.2.2.2 mjf .chan11b = BM7(W1_2412_2412, 1650 1.2.2.2 mjf W1_2437_2442, 1651 1.2.2.2 mjf W1_2462_2462, 1652 1.2.2.2 mjf W1_2472_2472, 1653 1.2.2.2 mjf W1_2417_2432, 1654 1.2.2.2 mjf W1_2447_2457, 1655 1.2.2.2 mjf W1_2467_2467), 1656 1.2.2.2 mjf .chan11g = BM7(WG1_2412_2412, 1657 1.2.2.2 mjf WG1_2437_2442, 1658 1.2.2.2 mjf WG1_2462_2462, 1659 1.2.2.2 mjf WG1_2472_2472, 1660 1.2.2.2 mjf WG1_2417_2432, 1661 1.2.2.2 mjf WG1_2447_2457, 1662 1.2.2.2 mjf WG1_2467_2467), 1663 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1664 1.2.2.2 mjf 1665 1.2.2.2 mjf {.regDmnEnum = EU1_WORLD, 1666 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1667 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1668 1.2.2.2 mjf .pscan = PSCAN_WWR, 1669 1.2.2.2 mjf .flags = ADHOC_PER_11D, 1670 1.2.2.2 mjf .chan11a = BM5(W1_5260_5320, 1671 1.2.2.2 mjf W1_5180_5240, 1672 1.2.2.2 mjf W1_5170_5230, 1673 1.2.2.2 mjf W1_5745_5825, 1674 1.2.2.2 mjf W1_5500_5700), 1675 1.2.2.2 mjf .chan11a_turbo = BM3(WT1_5210_5250, 1676 1.2.2.2 mjf WT1_5290_5290, 1677 1.2.2.2 mjf WT1_5760_5800), 1678 1.2.2.2 mjf .chan11b = BM7(W1_2412_2412, 1679 1.2.2.2 mjf W1_2437_2442, 1680 1.2.2.2 mjf W1_2462_2462, 1681 1.2.2.2 mjf W2_2472_2472, 1682 1.2.2.2 mjf W1_2417_2432, 1683 1.2.2.2 mjf W1_2447_2457, 1684 1.2.2.2 mjf W2_2467_2467), 1685 1.2.2.2 mjf .chan11g = BM7(WG1_2412_2412, 1686 1.2.2.2 mjf WG1_2437_2442, 1687 1.2.2.2 mjf WG1_2462_2462, 1688 1.2.2.2 mjf WG2_2472_2472, 1689 1.2.2.2 mjf WG1_2417_2432, 1690 1.2.2.2 mjf WG1_2447_2457, 1691 1.2.2.2 mjf WG2_2467_2467), 1692 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1693 1.2.2.2 mjf 1694 1.2.2.2 mjf {.regDmnEnum = WOR1_WORLD, 1695 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1696 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1697 1.2.2.2 mjf .pscan = PSCAN_WWR, 1698 1.2.2.2 mjf .flags = ADHOC_NO_11A, 1699 1.2.2.2 mjf .chan11a = BM5(W1_5260_5320, 1700 1.2.2.2 mjf W1_5180_5240, 1701 1.2.2.2 mjf W1_5170_5230, 1702 1.2.2.2 mjf W1_5745_5825, 1703 1.2.2.2 mjf W1_5500_5700), 1704 1.2.2.2 mjf .chan11b = BM8(W1_2412_2412, 1705 1.2.2.2 mjf W1_2437_2442, 1706 1.2.2.2 mjf W1_2462_2462, 1707 1.2.2.2 mjf W1_2472_2472, 1708 1.2.2.2 mjf W1_2417_2432, 1709 1.2.2.2 mjf W1_2447_2457, 1710 1.2.2.2 mjf W1_2467_2467, 1711 1.2.2.2 mjf W1_2484_2484), 1712 1.2.2.2 mjf .chan11g = BM7(WG1_2412_2412, 1713 1.2.2.2 mjf WG1_2437_2442, 1714 1.2.2.2 mjf WG1_2462_2462, 1715 1.2.2.2 mjf WG1_2472_2472, 1716 1.2.2.2 mjf WG1_2417_2432, 1717 1.2.2.2 mjf WG1_2447_2457, 1718 1.2.2.2 mjf WG1_2467_2467), 1719 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437) 1720 1.2.2.2 mjf }, 1721 1.2.2.2 mjf 1722 1.2.2.2 mjf {.regDmnEnum = WOR2_WORLD, 1723 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1724 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1725 1.2.2.2 mjf .pscan = PSCAN_WWR, 1726 1.2.2.2 mjf .flags = ADHOC_NO_11A, 1727 1.2.2.2 mjf .chan11a = BM5(W1_5260_5320, 1728 1.2.2.2 mjf W1_5180_5240, 1729 1.2.2.2 mjf W1_5170_5230, 1730 1.2.2.2 mjf W1_5745_5825, 1731 1.2.2.2 mjf W1_5500_5700), 1732 1.2.2.2 mjf .chan11a_turbo = BM3(WT1_5210_5250, 1733 1.2.2.2 mjf WT1_5290_5290, 1734 1.2.2.2 mjf WT1_5760_5800), 1735 1.2.2.2 mjf .chan11b = BM8(W1_2412_2412, 1736 1.2.2.2 mjf W1_2437_2442, 1737 1.2.2.2 mjf W1_2462_2462, 1738 1.2.2.2 mjf W1_2472_2472, 1739 1.2.2.2 mjf W1_2417_2432, 1740 1.2.2.2 mjf W1_2447_2457, 1741 1.2.2.2 mjf W1_2467_2467, 1742 1.2.2.2 mjf W1_2484_2484), 1743 1.2.2.2 mjf .chan11g = BM7(WG1_2412_2412, 1744 1.2.2.2 mjf WG1_2437_2442, 1745 1.2.2.2 mjf WG1_2462_2462, 1746 1.2.2.2 mjf WG1_2472_2472, 1747 1.2.2.2 mjf WG1_2417_2432, 1748 1.2.2.2 mjf WG1_2447_2457, 1749 1.2.2.2 mjf WG1_2467_2467), 1750 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1751 1.2.2.2 mjf 1752 1.2.2.2 mjf {.regDmnEnum = WOR3_WORLD, 1753 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1754 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1755 1.2.2.2 mjf .pscan = PSCAN_WWR, 1756 1.2.2.2 mjf .flags = ADHOC_PER_11D, 1757 1.2.2.2 mjf .chan11a = BM4(W1_5260_5320, 1758 1.2.2.2 mjf W1_5180_5240, 1759 1.2.2.2 mjf W1_5170_5230, 1760 1.2.2.2 mjf W1_5745_5825), 1761 1.2.2.2 mjf .chan11a_turbo = BM3(WT1_5210_5250, 1762 1.2.2.2 mjf WT1_5290_5290, 1763 1.2.2.2 mjf WT1_5760_5800), 1764 1.2.2.2 mjf .chan11b = BM7(W1_2412_2412, 1765 1.2.2.2 mjf W1_2437_2442, 1766 1.2.2.2 mjf W1_2462_2462, 1767 1.2.2.2 mjf W1_2472_2472, 1768 1.2.2.2 mjf W1_2417_2432, 1769 1.2.2.2 mjf W1_2447_2457, 1770 1.2.2.2 mjf W1_2467_2467), 1771 1.2.2.2 mjf .chan11g = BM7(WG1_2412_2412, 1772 1.2.2.2 mjf WG1_2437_2442, 1773 1.2.2.2 mjf WG1_2462_2462, 1774 1.2.2.2 mjf WG1_2472_2472, 1775 1.2.2.2 mjf WG1_2417_2432, 1776 1.2.2.2 mjf WG1_2447_2457, 1777 1.2.2.2 mjf WG1_2467_2467), 1778 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1779 1.2.2.2 mjf 1780 1.2.2.2 mjf {.regDmnEnum = WOR4_WORLD, 1781 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1782 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1783 1.2.2.2 mjf .pscan = PSCAN_WWR, 1784 1.2.2.2 mjf .flags = ADHOC_NO_11A, 1785 1.2.2.2 mjf .chan11a = BM4(W2_5260_5320, 1786 1.2.2.2 mjf W2_5180_5240, 1787 1.2.2.2 mjf F2_5745_5805, 1788 1.2.2.2 mjf W2_5825_5825), 1789 1.2.2.2 mjf .chan11a_turbo = BM3(WT1_5210_5250, 1790 1.2.2.2 mjf WT1_5290_5290, 1791 1.2.2.2 mjf WT1_5760_5800), 1792 1.2.2.2 mjf .chan11b = BM5(W1_2412_2412, 1793 1.2.2.2 mjf W1_2437_2442, 1794 1.2.2.2 mjf W1_2462_2462, 1795 1.2.2.2 mjf W1_2417_2432, 1796 1.2.2.2 mjf W1_2447_2457), 1797 1.2.2.2 mjf .chan11g = BM5(WG1_2412_2412, 1798 1.2.2.2 mjf WG1_2437_2442, 1799 1.2.2.2 mjf WG1_2462_2462, 1800 1.2.2.2 mjf WG1_2417_2432, 1801 1.2.2.2 mjf WG1_2447_2457), 1802 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1803 1.2.2.2 mjf 1804 1.2.2.2 mjf {.regDmnEnum = WOR5_ETSIC, 1805 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1806 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1807 1.2.2.2 mjf .pscan = PSCAN_WWR, 1808 1.2.2.2 mjf .flags = ADHOC_NO_11A, 1809 1.2.2.2 mjf .chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825), 1810 1.2.2.2 mjf .chan11b = BM7(W1_2412_2412, 1811 1.2.2.2 mjf W1_2437_2442, 1812 1.2.2.2 mjf W1_2462_2462, 1813 1.2.2.2 mjf W2_2472_2472, 1814 1.2.2.2 mjf W1_2417_2432, 1815 1.2.2.2 mjf W1_2447_2457, 1816 1.2.2.2 mjf W2_2467_2467), 1817 1.2.2.2 mjf .chan11g = BM7(WG1_2412_2412, 1818 1.2.2.2 mjf WG1_2437_2442, 1819 1.2.2.2 mjf WG1_2462_2462, 1820 1.2.2.2 mjf WG2_2472_2472, 1821 1.2.2.2 mjf WG1_2417_2432, 1822 1.2.2.2 mjf WG1_2447_2457, 1823 1.2.2.2 mjf WG2_2467_2467), 1824 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1825 1.2.2.2 mjf 1826 1.2.2.2 mjf {.regDmnEnum = WOR9_WORLD, 1827 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1828 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1829 1.2.2.2 mjf .pscan = PSCAN_WWR, 1830 1.2.2.2 mjf .flags = ADHOC_NO_11A, 1831 1.2.2.2 mjf .chan11a = BM4(W1_5260_5320, 1832 1.2.2.2 mjf W1_5180_5240, 1833 1.2.2.2 mjf W1_5745_5825, 1834 1.2.2.2 mjf W1_5500_5700), 1835 1.2.2.2 mjf .chan11a_turbo = BM3(WT1_5210_5250, 1836 1.2.2.2 mjf WT1_5290_5290, 1837 1.2.2.2 mjf WT1_5760_5800), 1838 1.2.2.2 mjf .chan11b = BM5(W1_2412_2412, 1839 1.2.2.2 mjf W1_2437_2442, 1840 1.2.2.2 mjf W1_2462_2462, 1841 1.2.2.2 mjf W1_2417_2432, 1842 1.2.2.2 mjf W1_2447_2457), 1843 1.2.2.2 mjf .chan11g = BM5(WG1_2412_2412, 1844 1.2.2.2 mjf WG1_2437_2442, 1845 1.2.2.2 mjf WG1_2462_2462, 1846 1.2.2.2 mjf WG1_2417_2432, 1847 1.2.2.2 mjf WG1_2447_2457), 1848 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1849 1.2.2.2 mjf 1850 1.2.2.2 mjf {.regDmnEnum = WORA_WORLD, 1851 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1852 1.2.2.2 mjf .dfsMask = DFS_FCC3 | DFS_ETSI, 1853 1.2.2.2 mjf .pscan = PSCAN_WWR, 1854 1.2.2.2 mjf .flags = ADHOC_NO_11A, 1855 1.2.2.2 mjf .chan11a = BM4(W1_5260_5320, 1856 1.2.2.2 mjf W1_5180_5240, 1857 1.2.2.2 mjf W1_5745_5825, 1858 1.2.2.2 mjf W1_5500_5700), 1859 1.2.2.2 mjf .chan11b = BM7(W1_2412_2412, 1860 1.2.2.2 mjf W1_2437_2442, 1861 1.2.2.2 mjf W1_2462_2462, 1862 1.2.2.2 mjf W1_2472_2472, 1863 1.2.2.2 mjf W1_2417_2432, 1864 1.2.2.2 mjf W1_2447_2457, 1865 1.2.2.2 mjf W1_2467_2467), 1866 1.2.2.2 mjf .chan11g = BM7(WG1_2412_2412, 1867 1.2.2.2 mjf WG1_2437_2442, 1868 1.2.2.2 mjf WG1_2462_2462, 1869 1.2.2.2 mjf WG1_2472_2472, 1870 1.2.2.2 mjf WG1_2417_2432, 1871 1.2.2.2 mjf WG1_2447_2457, 1872 1.2.2.2 mjf WG1_2467_2467), 1873 1.2.2.2 mjf .chan11g_turbo = BM1(T3_2437_2437)}, 1874 1.2.2.2 mjf 1875 1.2.2.2 mjf {.regDmnEnum = SR9_WORLD, 1876 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1877 1.2.2.2 mjf .pscan = PSCAN_FCC | PSCAN_FCC_T, 1878 1.2.2.2 mjf .chan11g = BM1(S1_912_917), 1879 1.2.2.2 mjf .chan11g_half = BM1(S1_907_922_10), 1880 1.2.2.2 mjf .chan11g_quarter = BM1(S1_907_922_5), 1881 1.2.2.2 mjf }, 1882 1.2.2.2 mjf 1883 1.2.2.2 mjf {.regDmnEnum = XR9_WORLD, 1884 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1885 1.2.2.2 mjf .pscan = PSCAN_FCC | PSCAN_FCC_T, 1886 1.2.2.2 mjf .chan11g = BM1(S2_912_917), 1887 1.2.2.2 mjf .chan11g_half = BM1(S2_907_922_10), 1888 1.2.2.2 mjf .chan11g_quarter = BM1(S2_907_922_5), 1889 1.2.2.2 mjf }, 1890 1.2.2.2 mjf 1891 1.2.2.2 mjf {.regDmnEnum = GZ901_WORLD, 1892 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1893 1.2.2.2 mjf .pscan = PSCAN_FCC | PSCAN_FCC_T, 1894 1.2.2.2 mjf .chan11g = BM1(S1_913_918), 1895 1.2.2.2 mjf .chan11g_half = BM1(S1_913_918_10), 1896 1.2.2.2 mjf .chan11g_quarter = BM1(S1_908_923_5), 1897 1.2.2.2 mjf }, 1898 1.2.2.2 mjf 1899 1.2.2.2 mjf {.regDmnEnum = NULL1, 1900 1.2.2.2 mjf .conformanceTestLimit = NO_CTL, 1901 1.2.2.2 mjf } 1902 1.2.2.2 mjf }; 1903 1.2.2.2 mjf 1904 1.2.2.2 mjf struct cmode { 1905 1.2.2.2 mjf u_int mode; 1906 1.2.2.2 mjf u_int flags; 1907 1.2.2.2 mjf }; 1908 1.2.2.2 mjf 1909 1.2.2.2 mjf static const struct cmode modes[] = { 1910 1.2.2.2 mjf { HAL_MODE_TURBO, CHANNEL_ST}, /* NB: 11a Static Turbo */ 1911 1.2.2.2 mjf { HAL_MODE_11A, CHANNEL_A}, 1912 1.2.2.2 mjf { HAL_MODE_11B, CHANNEL_B}, 1913 1.2.2.2 mjf { HAL_MODE_11G, CHANNEL_G}, 1914 1.2.2.2 mjf { HAL_MODE_11G_TURBO, CHANNEL_108G}, 1915 1.2.2.2 mjf { HAL_MODE_11A_TURBO, CHANNEL_108A}, 1916 1.2.2.2 mjf { HAL_MODE_11A_QUARTER_RATE, CHANNEL_A | CHANNEL_QUARTER}, 1917 1.2.2.2 mjf { HAL_MODE_11A_HALF_RATE, CHANNEL_A | CHANNEL_HALF}, 1918 1.2.2.2 mjf { HAL_MODE_11G_QUARTER_RATE, CHANNEL_G | CHANNEL_QUARTER}, 1919 1.2.2.2 mjf { HAL_MODE_11G_HALF_RATE, CHANNEL_G | CHANNEL_HALF}, 1920 1.2.2.2 mjf { HAL_MODE_11NG_HT20, CHANNEL_G_HT20}, 1921 1.2.2.2 mjf { HAL_MODE_11NG_HT40PLUS, CHANNEL_G_HT40PLUS}, 1922 1.2.2.2 mjf { HAL_MODE_11NG_HT40MINUS, CHANNEL_G_HT40MINUS}, 1923 1.2.2.2 mjf { HAL_MODE_11NA_HT20, CHANNEL_A_HT20}, 1924 1.2.2.2 mjf { HAL_MODE_11NA_HT40PLUS, CHANNEL_A_HT40PLUS}, 1925 1.2.2.2 mjf { HAL_MODE_11NA_HT40MINUS, CHANNEL_A_HT40MINUS}, 1926 1.2.2.2 mjf }; 1927 1.2.2.2 mjf 1928 1.2.2.2 mjf static int 1929 1.2.2.2 mjf chansort(const void *a, const void *b) 1930 1.2.2.2 mjf { 1931 1.2.2.2 mjf #define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) 1932 1.2.2.2 mjf const HAL_CHANNEL_INTERNAL *ca = a; 1933 1.2.2.2 mjf const HAL_CHANNEL_INTERNAL *cb = b; 1934 1.2.2.2 mjf 1935 1.2.2.2 mjf return (ca->channel == cb->channel) ? 1936 1.2.2.2 mjf (ca->channelFlags & CHAN_FLAGS) - 1937 1.2.2.2 mjf (cb->channelFlags & CHAN_FLAGS) : 1938 1.2.2.2 mjf ca->channel - cb->channel; 1939 1.2.2.2 mjf #undef CHAN_FLAGS 1940 1.2.2.2 mjf } 1941 1.2.2.2 mjf typedef int ath_hal_cmp_t(const void *, const void *); 1942 1.2.2.2 mjf static void ath_hal_sort(void *a, size_t n, size_t es, ath_hal_cmp_t *cmp); 1943 1.2.2.2 mjf static COUNTRY_CODE_TO_ENUM_RD* findCountry(HAL_CTRY_CODE countryCode); 1944 1.2.2.2 mjf static HAL_BOOL getWmRD(struct ath_hal *ah, COUNTRY_CODE_TO_ENUM_RD *country, uint16_t channelFlag, REG_DOMAIN *rd); 1945 1.2.2.2 mjf 1946 1.2.2.2 mjf 1947 1.2.2.2 mjf static uint16_t 1948 1.2.2.2 mjf getEepromRD(struct ath_hal *ah) 1949 1.2.2.2 mjf { 1950 1.2.2.2 mjf return AH_PRIVATE(ah)->ah_currentRD &~ WORLDWIDE_ROAMING_FLAG; 1951 1.2.2.2 mjf } 1952 1.2.2.2 mjf 1953 1.2.2.2 mjf /* 1954 1.2.2.2 mjf * Test to see if the bitmask array is all zeros 1955 1.2.2.2 mjf */ 1956 1.2.2.2 mjf static HAL_BOOL 1957 1.2.2.2 mjf isChanBitMaskZero(const uint64_t *bitmask) 1958 1.2.2.2 mjf { 1959 1.2.2.2 mjf #if BMLEN > 2 1960 1.2.2.2 mjf #error "add more cases" 1961 1.2.2.2 mjf #endif 1962 1.2.2.2 mjf #if BMLEN > 1 1963 1.2.2.2 mjf if (bitmask[1] != 0) 1964 1.2.2.2 mjf return AH_FALSE; 1965 1.2.2.2 mjf #endif 1966 1.2.2.2 mjf return (bitmask[0] == 0); 1967 1.2.2.2 mjf } 1968 1.2.2.2 mjf 1969 1.2.2.2 mjf /* 1970 1.2.2.2 mjf * Return whether or not the regulatory domain/country in EEPROM 1971 1.2.2.2 mjf * is acceptable. 1972 1.2.2.2 mjf */ 1973 1.2.2.2 mjf static HAL_BOOL 1974 1.2.2.2 mjf isEepromValid(struct ath_hal *ah) 1975 1.2.2.2 mjf { 1976 1.2.2.2 mjf uint16_t rd = getEepromRD(ah); 1977 1.2.2.2 mjf int i; 1978 1.2.2.2 mjf 1979 1.2.2.2 mjf if (rd & COUNTRY_ERD_FLAG) { 1980 1.2.2.2 mjf uint16_t cc = rd &~ COUNTRY_ERD_FLAG; 1981 1.2.2.2 mjf for (i = 0; i < N(allCountries); i++) 1982 1.2.2.2 mjf if (allCountries[i].countryCode == cc) 1983 1.2.2.2 mjf return AH_TRUE; 1984 1.2.2.2 mjf } else { 1985 1.2.2.2 mjf for (i = 0; i < N(regDomainPairs); i++) 1986 1.2.2.2 mjf if (regDomainPairs[i].regDmnEnum == rd) 1987 1.2.2.2 mjf return AH_TRUE; 1988 1.2.2.2 mjf } 1989 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1990 1.2.2.2 mjf "%s: invalid regulatory domain/country code 0x%x\n", __func__, rd); 1991 1.2.2.2 mjf return AH_FALSE; 1992 1.2.2.2 mjf } 1993 1.2.2.2 mjf 1994 1.2.2.2 mjf /* 1995 1.2.2.2 mjf * Returns whether or not the specified country code 1996 1.2.2.2 mjf * is allowed by the EEPROM setting 1997 1.2.2.2 mjf */ 1998 1.2.2.2 mjf static HAL_BOOL 1999 1.2.2.2 mjf isCountryCodeValid(struct ath_hal *ah, HAL_CTRY_CODE cc) 2000 1.2.2.2 mjf { 2001 1.2.2.2 mjf uint16_t rd; 2002 1.2.2.2 mjf 2003 1.2.2.2 mjf /* Default setting requires no checks */ 2004 1.2.2.2 mjf if (cc == CTRY_DEFAULT) 2005 1.2.2.2 mjf return AH_TRUE; 2006 1.2.2.2 mjf #ifdef AH_DEBUG_COUNTRY 2007 1.2.2.2 mjf if (cc == CTRY_DEBUG) 2008 1.2.2.2 mjf return AH_TRUE; 2009 1.2.2.2 mjf #endif 2010 1.2.2.2 mjf rd = getEepromRD(ah); 2011 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: EEPROM regdomain 0x%x\n", 2012 1.2.2.2 mjf __func__, rd); 2013 1.2.2.2 mjf 2014 1.2.2.2 mjf if (rd & COUNTRY_ERD_FLAG) { 2015 1.2.2.2 mjf /* EEP setting is a country - config shall match */ 2016 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2017 1.2.2.2 mjf "%s: EEPROM setting is country code %u\n", __func__, 2018 1.2.2.2 mjf rd &~ COUNTRY_ERD_FLAG); 2019 1.2.2.2 mjf return (cc == (rd & ~COUNTRY_ERD_FLAG)); 2020 1.2.2.2 mjf } else if (rd == DEBUG_REG_DMN || rd == NO_ENUMRD) { 2021 1.2.2.2 mjf /* Set to Debug or AllowAnyCountry mode - allow any setting */ 2022 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: rd %d allowed\n", 2023 1.2.2.2 mjf __func__, rd); 2024 1.2.2.2 mjf return AH_TRUE; 2025 1.2.2.2 mjf #ifdef AH_SUPPORT_11D 2026 1.2.2.2 mjf } else if ((rd & WORLD_SKU_MASK) == WORLD_SKU_PREFIX) { 2027 1.2.2.2 mjf int i; 2028 1.2.2.2 mjf for (i=0; i < N(allCountries); i++) { 2029 1.2.2.2 mjf if (cc == allCountries[i].countryCode) 2030 1.2.2.2 mjf return AH_TRUE; 2031 1.2.2.2 mjf } 2032 1.2.2.2 mjf #endif 2033 1.2.2.2 mjf } else { 2034 1.2.2.2 mjf int i; 2035 1.2.2.2 mjf for (i = 0; i < N(allCountries); i++) { 2036 1.2.2.2 mjf if (cc == allCountries[i].countryCode && 2037 1.2.2.2 mjf allCountries[i].regDmnEnum == rd) 2038 1.2.2.2 mjf return AH_TRUE; 2039 1.2.2.2 mjf } 2040 1.2.2.2 mjf } 2041 1.2.2.2 mjf return AH_FALSE; 2042 1.2.2.2 mjf } 2043 1.2.2.2 mjf 2044 1.2.2.2 mjf /* 2045 1.2.2.2 mjf * Return the mask of available modes based on the hardware 2046 1.2.2.2 mjf * capabilities and the specified country code and reg domain. 2047 1.2.2.2 mjf */ 2048 1.2.2.2 mjf static u_int 2049 1.2.2.2 mjf ath_hal_getwmodesnreg(struct ath_hal *ah, 2050 1.2.2.2 mjf const COUNTRY_CODE_TO_ENUM_RD *country, const REG_DOMAIN *rd5GHz) 2051 1.2.2.2 mjf { 2052 1.2.2.2 mjf #define HAL_MODE_11G_ALL \ 2053 1.2.2.2 mjf (HAL_MODE_11G | HAL_MODE_11G_TURBO | HAL_MODE_11G_QUARTER_RATE | \ 2054 1.2.2.2 mjf HAL_MODE_11G_HALF_RATE) 2055 1.2.2.2 mjf #define HAL_MODE_11A_ALL \ 2056 1.2.2.2 mjf (HAL_MODE_11A | HAL_MODE_11A_TURBO | HAL_MODE_TURBO | \ 2057 1.2.2.2 mjf HAL_MODE_11A_QUARTER_RATE | HAL_MODE_11A_HALF_RATE) 2058 1.2.2.2 mjf u_int modesAvail; 2059 1.2.2.2 mjf 2060 1.2.2.2 mjf /* Get modes that HW is capable of */ 2061 1.2.2.2 mjf modesAvail = ath_hal_getWirelessModes(ah); 2062 1.2.2.2 mjf 2063 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2064 1.2.2.2 mjf "%s: wireless modes 0x%x cc %u rd %u\n", 2065 1.2.2.2 mjf __func__, modesAvail, country->countryCode, country->regDmnEnum); 2066 1.2.2.2 mjf 2067 1.2.2.2 mjf /* Check country regulations for allowed modes */ 2068 1.2.2.2 mjf if (!country->allow11g && (modesAvail & HAL_MODE_11G_ALL)) { 2069 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2070 1.2.2.2 mjf "%s: disallow all 11g\n", __func__); 2071 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11G_ALL; 2072 1.2.2.2 mjf } 2073 1.2.2.2 mjf if (isChanBitMaskZero(rd5GHz->chan11a) && 2074 1.2.2.2 mjf (modesAvail & HAL_MODE_11A_ALL)) { 2075 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2076 1.2.2.2 mjf "%s: disallow all 11a\n", __func__); 2077 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11A_ALL; 2078 1.2.2.2 mjf } 2079 1.2.2.2 mjf if ((modesAvail & (HAL_MODE_11A_TURBO | HAL_MODE_TURBO)) && 2080 1.2.2.2 mjf !country->allow11aTurbo) { 2081 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2082 1.2.2.2 mjf "%s: disallow 11aTurbo\n", __func__); 2083 1.2.2.2 mjf modesAvail &= ~(HAL_MODE_11A_TURBO | HAL_MODE_TURBO); 2084 1.2.2.2 mjf } 2085 1.2.2.2 mjf if ((modesAvail & HAL_MODE_11G_TURBO) && !country->allow11gTurbo) { 2086 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2087 1.2.2.2 mjf "%s: disallow 11gTurbo\n", __func__); 2088 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11G_TURBO; 2089 1.2.2.2 mjf } 2090 1.2.2.2 mjf 2091 1.2.2.2 mjf /* Check 11n operation */ 2092 1.2.2.2 mjf if ((modesAvail & HAL_MODE_11NG_HT20) && !country->allow11ng20) { 2093 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2094 1.2.2.2 mjf "%s: disallow 11g HT20\n", __func__); 2095 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11NG_HT20; 2096 1.2.2.2 mjf } 2097 1.2.2.2 mjf if ((modesAvail & HAL_MODE_11NA_HT20) && !country->allow11na20) { 2098 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2099 1.2.2.2 mjf "%s: disallow 11a HT20\n", __func__); 2100 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11NA_HT20; 2101 1.2.2.2 mjf } 2102 1.2.2.2 mjf if ((modesAvail & HAL_MODE_11NG_HT40PLUS) && !country->allow11ng40) { 2103 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2104 1.2.2.2 mjf "%s: disallow 11g HT40+\n", __func__); 2105 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11NG_HT40PLUS; 2106 1.2.2.2 mjf } 2107 1.2.2.2 mjf if ((modesAvail & HAL_MODE_11NG_HT40MINUS) && !country->allow11ng40) { 2108 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2109 1.2.2.2 mjf "%s: disallow 11g HT40-\n", __func__); 2110 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11NG_HT40MINUS; 2111 1.2.2.2 mjf } 2112 1.2.2.2 mjf if ((modesAvail & HAL_MODE_11NA_HT40PLUS) && !country->allow11na40) { 2113 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2114 1.2.2.2 mjf "%s: disallow 11a HT40+\n", __func__); 2115 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11NA_HT40PLUS; 2116 1.2.2.2 mjf } 2117 1.2.2.2 mjf if ((modesAvail & HAL_MODE_11NA_HT40MINUS) && !country->allow11na40) { 2118 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2119 1.2.2.2 mjf "%s: disallow 11a HT40-\n", __func__); 2120 1.2.2.2 mjf modesAvail &= ~HAL_MODE_11NA_HT40MINUS; 2121 1.2.2.2 mjf } 2122 1.2.2.2 mjf 2123 1.2.2.2 mjf return modesAvail; 2124 1.2.2.2 mjf #undef HAL_MODE_11A_ALL 2125 1.2.2.2 mjf #undef HAL_MODE_11G_ALL 2126 1.2.2.2 mjf } 2127 1.2.2.2 mjf 2128 1.2.2.2 mjf /* 2129 1.2.2.2 mjf * Return the mask of available modes based on the hardware 2130 1.2.2.2 mjf * capabilities and the specified country code. 2131 1.2.2.2 mjf */ 2132 1.2.2.2 mjf 2133 1.2.2.2 mjf u_int 2134 1.2.2.2 mjf ath_hal_getwirelessmodes(struct ath_hal *ah, HAL_CTRY_CODE cc) 2135 1.2.2.2 mjf { 2136 1.2.2.2 mjf COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL; 2137 1.2.2.2 mjf u_int mode = 0; 2138 1.2.2.2 mjf REG_DOMAIN rd; 2139 1.2.2.2 mjf 2140 1.2.2.2 mjf country = findCountry(cc); 2141 1.2.2.2 mjf if (country != AH_NULL) { 2142 1.2.2.2 mjf if (getWmRD(ah, country, ~CHANNEL_2GHZ, &rd)) 2143 1.2.2.2 mjf mode = ath_hal_getwmodesnreg(ah, country, &rd); 2144 1.2.2.2 mjf } 2145 1.2.2.2 mjf return mode; 2146 1.2.2.2 mjf } 2147 1.2.2.2 mjf 2148 1.2.2.2 mjf /* 2149 1.2.2.2 mjf * Return if device is public safety. 2150 1.2.2.2 mjf */ 2151 1.2.2.2 mjf HAL_BOOL 2152 1.2.2.2 mjf ath_hal_ispublicsafetysku(struct ath_hal *ah) 2153 1.2.2.2 mjf { 2154 1.2.2.2 mjf uint16_t rd = getEepromRD(ah); 2155 1.2.2.2 mjf 2156 1.2.2.2 mjf switch (rd) { 2157 1.2.2.2 mjf case FCC4_FCCA: 2158 1.2.2.2 mjf case CTRY_UNITED_STATES_FCC49 | COUNTRY_ERD_FLAG: 2159 1.2.2.2 mjf return AH_TRUE; 2160 1.2.2.2 mjf case DEBUG_REG_DMN: 2161 1.2.2.2 mjf case NO_ENUMRD: 2162 1.2.2.2 mjf if (AH_PRIVATE(ah)->ah_countryCode == CTRY_UNITED_STATES_FCC49) 2163 1.2.2.2 mjf return AH_TRUE; 2164 1.2.2.2 mjf break; 2165 1.2.2.2 mjf } 2166 1.2.2.2 mjf return AH_FALSE; 2167 1.2.2.2 mjf } 2168 1.2.2.2 mjf 2169 1.2.2.2 mjf /* 2170 1.2.2.2 mjf * Return if device is actually operating in 900 MHz band. 2171 1.2.2.2 mjf */ 2172 1.2.2.2 mjf HAL_BOOL 2173 1.2.2.2 mjf ath_hal_isgsmsku(struct ath_hal *ah) 2174 1.2.2.2 mjf { 2175 1.2.2.2 mjf uint16_t rd = getEepromRD(ah); 2176 1.2.2.2 mjf 2177 1.2.2.2 mjf switch (rd) { 2178 1.2.2.2 mjf case SR9_WORLD: 2179 1.2.2.2 mjf case XR9_WORLD: 2180 1.2.2.2 mjf case GZ901_WORLD: 2181 1.2.2.2 mjf case CTRY_SR9 | COUNTRY_ERD_FLAG: 2182 1.2.2.2 mjf case CTRY_XR9 | COUNTRY_ERD_FLAG: 2183 1.2.2.2 mjf case CTRY_GZ901 | COUNTRY_ERD_FLAG: 2184 1.2.2.2 mjf return AH_TRUE; 2185 1.2.2.2 mjf case DEBUG_REG_DMN: 2186 1.2.2.2 mjf case NO_ENUMRD: 2187 1.2.2.2 mjf return AH_PRIVATE(ah)->ah_countryCode == CTRY_SR9 2188 1.2.2.2 mjf || AH_PRIVATE(ah)->ah_countryCode == CTRY_XR9 2189 1.2.2.2 mjf || AH_PRIVATE(ah)->ah_countryCode == CTRY_GZ901 2190 1.2.2.2 mjf ; 2191 1.2.2.2 mjf } 2192 1.2.2.2 mjf return AH_FALSE; 2193 1.2.2.2 mjf } 2194 1.2.2.2 mjf 2195 1.2.2.2 mjf /* 2196 1.2.2.2 mjf * Find the pointer to the country element in the country table 2197 1.2.2.2 mjf * corresponding to the country code 2198 1.2.2.2 mjf */ 2199 1.2.2.2 mjf static COUNTRY_CODE_TO_ENUM_RD* 2200 1.2.2.2 mjf findCountry(HAL_CTRY_CODE countryCode) 2201 1.2.2.2 mjf { 2202 1.2.2.2 mjf int i; 2203 1.2.2.2 mjf 2204 1.2.2.2 mjf for (i = 0; i < N(allCountries); i++) { 2205 1.2.2.2 mjf if (allCountries[i].countryCode == countryCode) 2206 1.2.2.2 mjf return &allCountries[i]; 2207 1.2.2.2 mjf } 2208 1.2.2.2 mjf return AH_NULL; /* Not found */ 2209 1.2.2.2 mjf } 2210 1.2.2.2 mjf 2211 1.2.2.2 mjf /* 2212 1.2.2.2 mjf * Calculate a default country based on the EEPROM setting. 2213 1.2.2.2 mjf */ 2214 1.2.2.2 mjf static HAL_CTRY_CODE 2215 1.2.2.2 mjf getDefaultCountry(struct ath_hal *ah) 2216 1.2.2.2 mjf { 2217 1.2.2.2 mjf uint16_t rd; 2218 1.2.2.2 mjf int i; 2219 1.2.2.2 mjf 2220 1.2.2.2 mjf rd = getEepromRD(ah); 2221 1.2.2.2 mjf if (rd & COUNTRY_ERD_FLAG) { 2222 1.2.2.2 mjf COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL; 2223 1.2.2.2 mjf uint16_t cc = rd & ~COUNTRY_ERD_FLAG; 2224 1.2.2.2 mjf 2225 1.2.2.2 mjf country = findCountry(cc); 2226 1.2.2.2 mjf if (country != AH_NULL) 2227 1.2.2.2 mjf return cc; 2228 1.2.2.2 mjf } 2229 1.2.2.2 mjf /* 2230 1.2.2.2 mjf * Check reg domains that have only one country 2231 1.2.2.2 mjf */ 2232 1.2.2.2 mjf for (i = 0; i < N(regDomainPairs); i++) 2233 1.2.2.2 mjf if (regDomainPairs[i].regDmnEnum == rd) { 2234 1.2.2.2 mjf if (regDomainPairs[i].singleCC != 0) 2235 1.2.2.2 mjf return regDomainPairs[i].singleCC; 2236 1.2.2.2 mjf else 2237 1.2.2.2 mjf i = N(regDomainPairs); 2238 1.2.2.2 mjf } 2239 1.2.2.2 mjf return CTRY_DEFAULT; 2240 1.2.2.2 mjf } 2241 1.2.2.2 mjf 2242 1.2.2.2 mjf static HAL_BOOL 2243 1.2.2.2 mjf isValidRegDmn(int regDmn, REG_DOMAIN *rd) 2244 1.2.2.2 mjf { 2245 1.2.2.2 mjf int i; 2246 1.2.2.2 mjf 2247 1.2.2.2 mjf for (i = 0; i < N(regDomains); i++) { 2248 1.2.2.2 mjf if (regDomains[i].regDmnEnum == regDmn) { 2249 1.2.2.2 mjf if (rd != AH_NULL) { 2250 1.2.2.2 mjf OS_MEMCPY(rd, ®Domains[i], 2251 1.2.2.2 mjf sizeof(REG_DOMAIN)); 2252 1.2.2.2 mjf } 2253 1.2.2.2 mjf return AH_TRUE; 2254 1.2.2.2 mjf } 2255 1.2.2.2 mjf } 2256 1.2.2.2 mjf return AH_FALSE; 2257 1.2.2.2 mjf } 2258 1.2.2.2 mjf 2259 1.2.2.2 mjf static HAL_BOOL 2260 1.2.2.2 mjf isValidRegDmnPair(int regDmnPair) 2261 1.2.2.2 mjf { 2262 1.2.2.2 mjf int i; 2263 1.2.2.2 mjf 2264 1.2.2.2 mjf if (regDmnPair == NO_ENUMRD) 2265 1.2.2.2 mjf return AH_FALSE; 2266 1.2.2.2 mjf for (i = 0; i < N(regDomainPairs); i++) { 2267 1.2.2.2 mjf if (regDomainPairs[i].regDmnEnum == regDmnPair) 2268 1.2.2.2 mjf return AH_TRUE; 2269 1.2.2.2 mjf } 2270 1.2.2.2 mjf return AH_FALSE; 2271 1.2.2.2 mjf } 2272 1.2.2.2 mjf 2273 1.2.2.2 mjf /* 2274 1.2.2.2 mjf * Return the Wireless Mode Regulatory Domain based 2275 1.2.2.2 mjf * on the country code and the wireless mode. 2276 1.2.2.2 mjf */ 2277 1.2.2.2 mjf static HAL_BOOL 2278 1.2.2.2 mjf getWmRD(struct ath_hal *ah, COUNTRY_CODE_TO_ENUM_RD *country, 2279 1.2.2.2 mjf uint16_t channelFlag, REG_DOMAIN *rd) 2280 1.2.2.2 mjf { 2281 1.2.2.2 mjf int regDmn; 2282 1.2.2.2 mjf REG_DMN_PAIR_MAPPING *regPair; 2283 1.2.2.2 mjf uint64_t flags; 2284 1.2.2.2 mjf 2285 1.2.2.2 mjf if (country->countryCode == CTRY_DEFAULT) { 2286 1.2.2.2 mjf uint16_t rdnum = getEepromRD(ah); 2287 1.2.2.2 mjf 2288 1.2.2.2 mjf if ((rdnum & COUNTRY_ERD_FLAG) == 0) { 2289 1.2.2.2 mjf if (isValidRegDmn(rdnum, AH_NULL) || 2290 1.2.2.2 mjf isValidRegDmnPair(rdnum)) 2291 1.2.2.2 mjf regDmn = rdnum; 2292 1.2.2.2 mjf else 2293 1.2.2.2 mjf regDmn = country->regDmnEnum; 2294 1.2.2.2 mjf } else 2295 1.2.2.2 mjf regDmn = country->regDmnEnum; 2296 1.2.2.2 mjf } else 2297 1.2.2.2 mjf regDmn = country->regDmnEnum; 2298 1.2.2.2 mjf regPair = AH_NULL; 2299 1.2.2.2 mjf flags = NO_REQ; 2300 1.2.2.2 mjf if ((regDmn & MULTI_DOMAIN_MASK) == 0) { 2301 1.2.2.2 mjf int i; 2302 1.2.2.2 mjf 2303 1.2.2.2 mjf for (i = 0; i < N(regDomainPairs); i++) { 2304 1.2.2.2 mjf if (regDomainPairs[i].regDmnEnum == regDmn) { 2305 1.2.2.2 mjf regPair = ®DomainPairs[i]; 2306 1.2.2.2 mjf break; 2307 1.2.2.2 mjf } 2308 1.2.2.2 mjf } 2309 1.2.2.2 mjf if (regPair == AH_NULL) { 2310 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2311 1.2.2.2 mjf "%s: Failed to find reg domain pair %u\n", 2312 1.2.2.2 mjf __func__, regDmn); 2313 1.2.2.2 mjf return AH_FALSE; 2314 1.2.2.2 mjf } 2315 1.2.2.2 mjf if (channelFlag & CHANNEL_2GHZ) { 2316 1.2.2.2 mjf regDmn = regPair->regDmn2GHz; 2317 1.2.2.2 mjf flags = regPair->flags2GHz; 2318 1.2.2.2 mjf } else { 2319 1.2.2.2 mjf regDmn = regPair->regDmn5GHz; 2320 1.2.2.2 mjf flags = regPair->flags5GHz; 2321 1.2.2.2 mjf } 2322 1.2.2.2 mjf } 2323 1.2.2.2 mjf 2324 1.2.2.2 mjf /* 2325 1.2.2.2 mjf * We either started with a unitary reg domain or we've found the 2326 1.2.2.2 mjf * unitary reg domain of the pair 2327 1.2.2.2 mjf */ 2328 1.2.2.2 mjf if (isValidRegDmn(regDmn, rd)) { 2329 1.2.2.2 mjf if (regPair != AH_NULL) 2330 1.2.2.2 mjf rd->pscan &= regPair->pscanMask; 2331 1.2.2.2 mjf if ((country->regDmnEnum & MULTI_DOMAIN_MASK) == 0 && 2332 1.2.2.2 mjf flags != NO_REQ) 2333 1.2.2.2 mjf rd->flags = flags; 2334 1.2.2.2 mjf return AH_TRUE; 2335 1.2.2.2 mjf } else { 2336 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2337 1.2.2.2 mjf "%s: Failed to find unitary reg domain %u\n", __func__, 2338 1.2.2.2 mjf country->regDmnEnum); 2339 1.2.2.2 mjf return AH_FALSE; 2340 1.2.2.2 mjf } 2341 1.2.2.2 mjf } 2342 1.2.2.2 mjf 2343 1.2.2.2 mjf static HAL_BOOL 2344 1.2.2.2 mjf IS_BIT_SET(int bit, const uint64_t bitmask[]) 2345 1.2.2.2 mjf { 2346 1.2.2.2 mjf int byteOffset, bitnum; 2347 1.2.2.2 mjf uint64_t val; 2348 1.2.2.2 mjf 2349 1.2.2.2 mjf byteOffset = bit/64; 2350 1.2.2.2 mjf bitnum = bit - byteOffset*64; 2351 1.2.2.2 mjf val = ((uint64_t) 1) << bitnum; 2352 1.2.2.2 mjf return (bitmask[byteOffset] & val) != 0; 2353 1.2.2.2 mjf } 2354 1.2.2.2 mjf 2355 1.2.2.2 mjf /* Add given regclassid into regclassids array upto max of maxregids */ 2356 1.2.2.2 mjf static void 2357 1.2.2.2 mjf ath_add_regclassid(uint8_t *regclassids, u_int maxregids, 2358 1.2.2.2 mjf u_int *nregids, uint8_t regclassid) 2359 1.2.2.2 mjf { 2360 1.2.2.2 mjf int i; 2361 1.2.2.2 mjf 2362 1.2.2.2 mjf /* Is regclassid valid? */ 2363 1.2.2.2 mjf if (regclassid == 0) 2364 1.2.2.2 mjf return; 2365 1.2.2.2 mjf 2366 1.2.2.2 mjf for (i = 0; i < maxregids; i++) { 2367 1.2.2.2 mjf if (regclassids[i] == regclassid) /* already present */ 2368 1.2.2.2 mjf return; 2369 1.2.2.2 mjf if (regclassids[i] == 0) { /* free slot */ 2370 1.2.2.2 mjf regclassids[i] = regclassid; 2371 1.2.2.2 mjf (*nregids)++; 2372 1.2.2.2 mjf return; 2373 1.2.2.2 mjf } 2374 1.2.2.2 mjf } 2375 1.2.2.2 mjf } 2376 1.2.2.2 mjf 2377 1.2.2.2 mjf /* 2378 1.2.2.2 mjf * Setup the channel list based on the information in the EEPROM and 2379 1.2.2.2 mjf * any supplied country code. Note that we also do a bunch of EEPROM 2380 1.2.2.2 mjf * verification here and setup certain regulatory-related access 2381 1.2.2.2 mjf * control data used later on. 2382 1.2.2.2 mjf */ 2383 1.2.2.2 mjf 2384 1.2.2.2 mjf HAL_BOOL 2385 1.2.2.2 mjf ath_hal_init_channels(struct ath_hal *ah, 2386 1.2.2.2 mjf HAL_CHANNEL *chans, u_int maxchans, u_int *nchans, 2387 1.2.2.2 mjf uint8_t *regclassids, u_int maxregids, u_int *nregids, 2388 1.2.2.2 mjf HAL_CTRY_CODE cc, u_int modeSelect, 2389 1.2.2.2 mjf HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels) 2390 1.2.2.2 mjf { 2391 1.2.2.2 mjf #define CHANNEL_HALF_BW 10 2392 1.2.2.2 mjf #define CHANNEL_QUARTER_BW 5 2393 1.2.2.2 mjf u_int modesAvail; 2394 1.2.2.2 mjf uint16_t maxChan; 2395 1.2.2.2 mjf COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL; 2396 1.2.2.2 mjf REG_DOMAIN rd5GHz, rd2GHz; 2397 1.2.2.2 mjf const struct cmode *cm; 2398 1.2.2.2 mjf HAL_CHANNEL_INTERNAL *ichans = &AH_PRIVATE(ah)->ah_channels[0]; 2399 1.2.2.2 mjf int next, b; 2400 1.2.2.2 mjf uint8_t ctl; 2401 1.2.2.2 mjf 2402 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u mode 0x%x%s%s\n", 2403 1.2.2.2 mjf __func__, cc, modeSelect, enableOutdoor? " Enable outdoor" : " ", 2404 1.2.2.2 mjf enableExtendedChannels ? " Enable ecm" : ""); 2405 1.2.2.2 mjf 2406 1.2.2.2 mjf /* 2407 1.2.2.2 mjf * Validate the EEPROM setting and setup defaults 2408 1.2.2.2 mjf */ 2409 1.2.2.2 mjf if (!isEepromValid(ah)) { 2410 1.2.2.2 mjf /* 2411 1.2.2.2 mjf * Don't return any channels if the EEPROM has an 2412 1.2.2.2 mjf * invalid regulatory domain/country code setting. 2413 1.2.2.2 mjf */ 2414 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2415 1.2.2.2 mjf "%s: invalid EEPROM contents\n",__func__); 2416 1.2.2.2 mjf return AH_FALSE; 2417 1.2.2.2 mjf } 2418 1.2.2.2 mjf 2419 1.2.2.2 mjf AH_PRIVATE(ah)->ah_countryCode = getDefaultCountry(ah); 2420 1.2.2.2 mjf 2421 1.2.2.2 mjf #ifndef AH_SUPPORT_11D 2422 1.2.2.2 mjf if (AH_PRIVATE(ah)->ah_countryCode == CTRY_DEFAULT) { 2423 1.2.2.2 mjf #endif 2424 1.2.2.2 mjf /* 2425 1.2.2.2 mjf * We now have enough state to validate any country code 2426 1.2.2.2 mjf * passed in by the caller. 2427 1.2.2.2 mjf */ 2428 1.2.2.2 mjf if (!isCountryCodeValid(ah, cc)) { 2429 1.2.2.2 mjf /* NB: Atheros silently ignores invalid country codes */ 2430 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2431 1.2.2.2 mjf "%s: invalid country code %d\n", __func__, cc); 2432 1.2.2.2 mjf return AH_FALSE; 2433 1.2.2.2 mjf } 2434 1.2.2.2 mjf AH_PRIVATE(ah)->ah_countryCode = cc & COUNTRY_CODE_MASK; 2435 1.2.2.2 mjf #ifndef AH_SUPPORT_11D 2436 1.2.2.2 mjf } 2437 1.2.2.2 mjf #endif 2438 1.2.2.2 mjf 2439 1.2.2.2 mjf /* Get pointers to the country element and the reg domain elements */ 2440 1.2.2.2 mjf country = findCountry(AH_PRIVATE(ah)->ah_countryCode); 2441 1.2.2.2 mjf 2442 1.2.2.2 mjf if (country == AH_NULL) { 2443 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "NULL Country!, cc= %d\n", 2444 1.2.2.2 mjf AH_PRIVATE(ah)->ah_countryCode); 2445 1.2.2.2 mjf return AH_FALSE; 2446 1.2.2.2 mjf } 2447 1.2.2.2 mjf 2448 1.2.2.2 mjf if (!getWmRD(ah, country, ~CHANNEL_2GHZ, &rd5GHz)) { 2449 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2450 1.2.2.2 mjf "%s: no unitary 5GHz regdomain for country %u\n", 2451 1.2.2.2 mjf __func__, AH_PRIVATE(ah)->ah_countryCode); 2452 1.2.2.2 mjf return AH_FALSE; 2453 1.2.2.2 mjf } 2454 1.2.2.2 mjf if (!getWmRD(ah, country, CHANNEL_2GHZ, &rd2GHz)) { 2455 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2456 1.2.2.2 mjf "%s: no unitary 2GHz regdomain for country %u\n", 2457 1.2.2.2 mjf __func__, AH_PRIVATE(ah)->ah_countryCode); 2458 1.2.2.2 mjf return AH_FALSE; 2459 1.2.2.2 mjf } 2460 1.2.2.2 mjf 2461 1.2.2.2 mjf modesAvail = ath_hal_getwmodesnreg(ah, country, &rd5GHz); 2462 1.2.2.2 mjf maxChan = !enableOutdoor ? country->outdoorChanStart : 7000; 2463 1.2.2.2 mjf 2464 1.2.2.2 mjf if (maxchans > N(AH_PRIVATE(ah)->ah_channels)) 2465 1.2.2.2 mjf maxchans = N(AH_PRIVATE(ah)->ah_channels); 2466 1.2.2.2 mjf next = 0; 2467 1.2.2.2 mjf for (cm = modes; cm < &modes[N(modes)]; cm++) { 2468 1.2.2.2 mjf uint16_t c, c_hi, c_lo; 2469 1.2.2.2 mjf uint64_t *channelBM = AH_NULL; 2470 1.2.2.2 mjf REG_DOMAIN *rd = AH_NULL; 2471 1.2.2.2 mjf REG_DMN_FREQ_BAND *fband = AH_NULL,*freqs; 2472 1.2.2.2 mjf int low_adj, hi_adj, channelSep, lastc; 2473 1.2.2.2 mjf 2474 1.2.2.2 mjf if ((cm->mode & modeSelect) == 0) { 2475 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2476 1.2.2.2 mjf "%s: skip mode 0x%x flags 0x%x\n", 2477 1.2.2.2 mjf __func__, cm->mode, cm->flags); 2478 1.2.2.2 mjf continue; 2479 1.2.2.2 mjf } 2480 1.2.2.2 mjf if ((cm->mode & modesAvail) == 0) { 2481 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2482 1.2.2.2 mjf "%s: !avail mode 0x%x (0x%x) flags 0x%x\n", 2483 1.2.2.2 mjf __func__, modesAvail, cm->mode, cm->flags); 2484 1.2.2.2 mjf continue; 2485 1.2.2.2 mjf } 2486 1.2.2.2 mjf if (!ath_hal_getChannelEdges(ah, cm->flags, &c_lo, &c_hi)) { 2487 1.2.2.2 mjf /* channel not supported by hardware, skip it */ 2488 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2489 1.2.2.2 mjf "%s: channels 0x%x not supported by hardware\n", 2490 1.2.2.2 mjf __func__,cm->flags); 2491 1.2.2.2 mjf continue; 2492 1.2.2.2 mjf } 2493 1.2.2.2 mjf switch (cm->mode) { 2494 1.2.2.2 mjf case HAL_MODE_TURBO: 2495 1.2.2.2 mjf rd = &rd5GHz; 2496 1.2.2.2 mjf channelBM = rd->chan11a_turbo; 2497 1.2.2.2 mjf freqs = ®Dmn5GhzTurboFreq[0]; 2498 1.2.2.2 mjf ctl = rd->conformanceTestLimit | CTL_TURBO; 2499 1.2.2.2 mjf break; 2500 1.2.2.2 mjf case HAL_MODE_11A: 2501 1.2.2.2 mjf case HAL_MODE_11A_HALF_RATE: 2502 1.2.2.2 mjf case HAL_MODE_11A_QUARTER_RATE: 2503 1.2.2.2 mjf case HAL_MODE_11NA_HT20: 2504 1.2.2.2 mjf case HAL_MODE_11NA_HT40PLUS: 2505 1.2.2.2 mjf case HAL_MODE_11NA_HT40MINUS: 2506 1.2.2.2 mjf rd = &rd5GHz; 2507 1.2.2.2 mjf if (cm->mode == HAL_MODE_11A_HALF_RATE) 2508 1.2.2.2 mjf channelBM = rd->chan11a_half; 2509 1.2.2.2 mjf else if (cm->mode == HAL_MODE_11A_QUARTER_RATE) 2510 1.2.2.2 mjf channelBM = rd->chan11a_quarter; 2511 1.2.2.2 mjf else 2512 1.2.2.2 mjf channelBM = rd->chan11a; 2513 1.2.2.2 mjf freqs = ®Dmn5GhzFreq[0]; 2514 1.2.2.2 mjf ctl = rd->conformanceTestLimit; 2515 1.2.2.2 mjf break; 2516 1.2.2.2 mjf case HAL_MODE_11B: 2517 1.2.2.2 mjf rd = &rd2GHz; 2518 1.2.2.2 mjf channelBM = rd->chan11b; 2519 1.2.2.2 mjf freqs = ®Dmn2GhzFreq[0]; 2520 1.2.2.2 mjf ctl = rd->conformanceTestLimit | CTL_11B; 2521 1.2.2.2 mjf break; 2522 1.2.2.2 mjf case HAL_MODE_11G: 2523 1.2.2.2 mjf case HAL_MODE_11G_HALF_RATE: 2524 1.2.2.2 mjf case HAL_MODE_11G_QUARTER_RATE: 2525 1.2.2.2 mjf case HAL_MODE_11NG_HT20: 2526 1.2.2.2 mjf case HAL_MODE_11NG_HT40PLUS: 2527 1.2.2.2 mjf case HAL_MODE_11NG_HT40MINUS: 2528 1.2.2.2 mjf rd = &rd2GHz; 2529 1.2.2.2 mjf if (cm->mode == HAL_MODE_11G_HALF_RATE) 2530 1.2.2.2 mjf channelBM = rd->chan11g_half; 2531 1.2.2.2 mjf else if (cm->mode == HAL_MODE_11G_QUARTER_RATE) 2532 1.2.2.2 mjf channelBM = rd->chan11g_quarter; 2533 1.2.2.2 mjf else 2534 1.2.2.2 mjf channelBM = rd->chan11g; 2535 1.2.2.2 mjf freqs = ®Dmn2Ghz11gFreq[0]; 2536 1.2.2.2 mjf ctl = rd->conformanceTestLimit | CTL_11G; 2537 1.2.2.2 mjf break; 2538 1.2.2.2 mjf case HAL_MODE_11G_TURBO: 2539 1.2.2.2 mjf rd = &rd2GHz; 2540 1.2.2.2 mjf channelBM = rd->chan11g_turbo; 2541 1.2.2.2 mjf freqs = ®Dmn2Ghz11gTurboFreq[0]; 2542 1.2.2.2 mjf ctl = rd->conformanceTestLimit | CTL_108G; 2543 1.2.2.2 mjf break; 2544 1.2.2.2 mjf case HAL_MODE_11A_TURBO: 2545 1.2.2.2 mjf rd = &rd5GHz; 2546 1.2.2.2 mjf channelBM = rd->chan11a_dyn_turbo; 2547 1.2.2.2 mjf freqs = ®Dmn5GhzTurboFreq[0]; 2548 1.2.2.2 mjf ctl = rd->conformanceTestLimit | CTL_108G; 2549 1.2.2.2 mjf break; 2550 1.2.2.2 mjf default: 2551 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2552 1.2.2.2 mjf "%s: Unkonwn HAL mode 0x%x\n", __func__, cm->mode); 2553 1.2.2.2 mjf continue; 2554 1.2.2.2 mjf } 2555 1.2.2.2 mjf if (isChanBitMaskZero(channelBM)) 2556 1.2.2.2 mjf continue; 2557 1.2.2.2 mjf /* 2558 1.2.2.2 mjf * Setup special handling for HT40 channels; e.g. 2559 1.2.2.2 mjf * 5G HT40 channels require 40Mhz channel separation. 2560 1.2.2.2 mjf */ 2561 1.2.2.2 mjf hi_adj = (cm->mode == HAL_MODE_11NA_HT40PLUS || 2562 1.2.2.2 mjf cm->mode == HAL_MODE_11NG_HT40PLUS) ? -20 : 0; 2563 1.2.2.2 mjf low_adj = (cm->mode == HAL_MODE_11NA_HT40MINUS || 2564 1.2.2.2 mjf cm->mode == HAL_MODE_11NG_HT40MINUS) ? 20 : 0; 2565 1.2.2.2 mjf channelSep = (cm->mode == HAL_MODE_11NA_HT40PLUS || 2566 1.2.2.2 mjf cm->mode == HAL_MODE_11NA_HT40MINUS) ? 40 : 0; 2567 1.2.2.2 mjf 2568 1.2.2.2 mjf for (b = 0; b < 64*BMLEN; b++) { 2569 1.2.2.2 mjf if (!IS_BIT_SET(b, channelBM)) 2570 1.2.2.2 mjf continue; 2571 1.2.2.2 mjf fband = &freqs[b]; 2572 1.2.2.2 mjf lastc = 0; 2573 1.2.2.2 mjf 2574 1.2.2.2 mjf ath_add_regclassid(regclassids, maxregids, 2575 1.2.2.2 mjf nregids, fband->regClassId); 2576 1.2.2.2 mjf 2577 1.2.2.2 mjf for (c = fband->lowChannel + low_adj; 2578 1.2.2.2 mjf c <= fband->highChannel + hi_adj; 2579 1.2.2.2 mjf c += fband->channelSep) { 2580 1.2.2.2 mjf HAL_CHANNEL_INTERNAL icv; 2581 1.2.2.2 mjf 2582 1.2.2.2 mjf if (!(c_lo <= c && c <= c_hi)) { 2583 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2584 1.2.2.2 mjf "%s: c %u out of range [%u..%u]\n", 2585 1.2.2.2 mjf __func__, c, c_lo, c_hi); 2586 1.2.2.2 mjf continue; 2587 1.2.2.2 mjf } 2588 1.2.2.2 mjf if (((c+fband->channelSep)/2) > (maxChan+HALF_MAXCHANBW)) { 2589 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2590 1.2.2.2 mjf "%s: c %u > maxChan %u\n", 2591 1.2.2.2 mjf __func__, c, maxChan); 2592 1.2.2.2 mjf continue; 2593 1.2.2.2 mjf } 2594 1.2.2.2 mjf if (next >= maxchans){ 2595 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2596 1.2.2.2 mjf "%s: too many channels for channel table\n", 2597 1.2.2.2 mjf __func__); 2598 1.2.2.2 mjf goto done; 2599 1.2.2.2 mjf } 2600 1.2.2.2 mjf if ((fband->usePassScan & IS_ECM_CHAN) && 2601 1.2.2.2 mjf !enableExtendedChannels) { 2602 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2603 1.2.2.2 mjf "Skipping ecm channel\n"); 2604 1.2.2.2 mjf continue; 2605 1.2.2.2 mjf } 2606 1.2.2.2 mjf /* XXX needs to be in ath_hal_checkchannel */ 2607 1.2.2.2 mjf if ((rd->flags & NO_HOSTAP) && 2608 1.2.2.2 mjf (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP)) { 2609 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2610 1.2.2.2 mjf "Skipping HOSTAP channel\n"); 2611 1.2.2.2 mjf continue; 2612 1.2.2.2 mjf } 2613 1.2.2.2 mjf /* 2614 1.2.2.2 mjf * Make sure that channel separation 2615 1.2.2.2 mjf * meets the requirement. 2616 1.2.2.2 mjf */ 2617 1.2.2.2 mjf if (lastc && channelSep && 2618 1.2.2.2 mjf (c-lastc) < channelSep) 2619 1.2.2.2 mjf continue; 2620 1.2.2.2 mjf 2621 1.2.2.2 mjf OS_MEMZERO(&icv, sizeof(icv)); 2622 1.2.2.2 mjf icv.channel = c; 2623 1.2.2.2 mjf icv.channelFlags = cm->flags; 2624 1.2.2.2 mjf icv.maxRegTxPower = fband->powerDfs; 2625 1.2.2.2 mjf icv.antennaMax = fband->antennaMax; 2626 1.2.2.2 mjf icv.regDmnFlags = rd->flags; 2627 1.2.2.2 mjf icv.conformanceTestLimit = ctl; 2628 1.2.2.2 mjf if (fband->usePassScan & rd->pscan) 2629 1.2.2.2 mjf icv.channelFlags |= CHANNEL_PASSIVE; 2630 1.2.2.2 mjf else 2631 1.2.2.2 mjf icv.channelFlags &= ~CHANNEL_PASSIVE; 2632 1.2.2.2 mjf lastc = c; 2633 1.2.2.2 mjf if (fband->useDfs & rd->dfsMask) { 2634 1.2.2.2 mjf /* DFS and HT40 don't mix */ 2635 1.2.2.2 mjf if (cm->mode == HAL_MODE_11NA_HT40PLUS || 2636 1.2.2.2 mjf cm->mode == HAL_MODE_11NA_HT40MINUS) 2637 1.2.2.2 mjf continue; 2638 1.2.2.2 mjf icv.privFlags = CHANNEL_DFS; 2639 1.2.2.2 mjf } else 2640 1.2.2.2 mjf icv.privFlags = 0; 2641 1.2.2.2 mjf if (rd->flags & LIMIT_FRAME_4MS) 2642 1.2.2.2 mjf icv.privFlags |= CHANNEL_4MS_LIMIT; 2643 1.2.2.2 mjf 2644 1.2.2.2 mjf ichans[next++] = icv; 2645 1.2.2.2 mjf } 2646 1.2.2.2 mjf } 2647 1.2.2.2 mjf } 2648 1.2.2.2 mjf done: 2649 1.2.2.2 mjf if (next != 0) { 2650 1.2.2.2 mjf int i; 2651 1.2.2.2 mjf 2652 1.2.2.2 mjf /* XXX maxchans set above so this cannot happen? */ 2653 1.2.2.2 mjf if (next > N(AH_PRIVATE(ah)->ah_channels)) { 2654 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2655 1.2.2.2 mjf "%s: too many channels %u; truncating to %u\n", 2656 1.2.2.2 mjf __func__, next, 2657 1.2.2.2 mjf (int) N(AH_PRIVATE(ah)->ah_channels)); 2658 1.2.2.2 mjf next = N(AH_PRIVATE(ah)->ah_channels); 2659 1.2.2.2 mjf } 2660 1.2.2.2 mjf 2661 1.2.2.2 mjf /* 2662 1.2.2.2 mjf * Keep a private copy of the channel list so we can 2663 1.2.2.2 mjf * constrain future requests to only these channels 2664 1.2.2.2 mjf */ 2665 1.2.2.2 mjf ath_hal_sort(ichans, next, sizeof(HAL_CHANNEL_INTERNAL), 2666 1.2.2.2 mjf chansort); 2667 1.2.2.2 mjf AH_PRIVATE(ah)->ah_nchan = next; 2668 1.2.2.2 mjf 2669 1.2.2.2 mjf /* 2670 1.2.2.2 mjf * Copy the channel list to the public channel list 2671 1.2.2.2 mjf */ 2672 1.2.2.2 mjf for (i = 0; i < next; i++) { 2673 1.2.2.2 mjf chans[i].channel = ichans[i].channel; 2674 1.2.2.2 mjf chans[i].channelFlags = ichans[i].channelFlags; 2675 1.2.2.2 mjf chans[i].privFlags = ichans[i].privFlags; 2676 1.2.2.2 mjf chans[i].maxRegTxPower = ichans[i].maxRegTxPower; 2677 1.2.2.2 mjf } 2678 1.2.2.2 mjf /* 2679 1.2.2.2 mjf * Retrieve power limits. 2680 1.2.2.2 mjf */ 2681 1.2.2.2 mjf ath_hal_getpowerlimits(ah, chans, next); 2682 1.2.2.2 mjf for (i = 0; i < next; i++) { 2683 1.2.2.2 mjf ichans[i].maxTxPower = chans[i].maxTxPower; 2684 1.2.2.2 mjf ichans[i].minTxPower = chans[i].minTxPower; 2685 1.2.2.2 mjf } 2686 1.2.2.2 mjf } 2687 1.2.2.2 mjf *nchans = next; 2688 1.2.2.2 mjf /* XXX copy private setting to public area */ 2689 1.2.2.2 mjf ah->ah_countryCode = AH_PRIVATE(ah)->ah_countryCode; 2690 1.2.2.2 mjf return (next != 0); 2691 1.2.2.2 mjf #undef CHANNEL_HALF_BW 2692 1.2.2.2 mjf #undef CHANNEL_QUARTER_BW 2693 1.2.2.2 mjf } 2694 1.2.2.2 mjf 2695 1.2.2.2 mjf /* 2696 1.2.2.2 mjf * Return whether or not the specified channel is ok to use 2697 1.2.2.2 mjf * based on the current regulatory domain constraints and 2698 1.2.2.2 mjf * DFS interference. 2699 1.2.2.2 mjf */ 2700 1.2.2.2 mjf HAL_CHANNEL_INTERNAL * 2701 1.2.2.2 mjf ath_hal_checkchannel(struct ath_hal *ah, const HAL_CHANNEL *c) 2702 1.2.2.2 mjf { 2703 1.2.2.2 mjf #define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) 2704 1.2.2.2 mjf HAL_CHANNEL_INTERNAL *base, *cc; 2705 1.2.2.2 mjf /* NB: be wary of user-specified channel flags */ 2706 1.2.2.2 mjf int flags = c->channelFlags & CHAN_FLAGS; 2707 1.2.2.2 mjf int n, lim, d; 2708 1.2.2.2 mjf 2709 1.2.2.2 mjf /* 2710 1.2.2.2 mjf * Check current channel to avoid the lookup. 2711 1.2.2.2 mjf */ 2712 1.2.2.2 mjf cc = AH_PRIVATE(ah)->ah_curchan; 2713 1.2.2.2 mjf if (cc != AH_NULL && cc->channel == c->channel && 2714 1.2.2.2 mjf (cc->channelFlags & CHAN_FLAGS) == flags) { 2715 1.2.2.2 mjf if ((cc->privFlags & CHANNEL_INTERFERENCE) && 2716 1.2.2.2 mjf (cc->channelFlags & CHANNEL_DFS)) 2717 1.2.2.2 mjf return AH_NULL; 2718 1.2.2.2 mjf else 2719 1.2.2.2 mjf return cc; 2720 1.2.2.2 mjf } 2721 1.2.2.2 mjf 2722 1.2.2.2 mjf /* binary search based on known sorting order */ 2723 1.2.2.2 mjf base = AH_PRIVATE(ah)->ah_channels; 2724 1.2.2.2 mjf n = AH_PRIVATE(ah)->ah_nchan; 2725 1.2.2.2 mjf /* binary search based on known sorting order */ 2726 1.2.2.2 mjf for (lim = n; lim != 0; lim >>= 1) { 2727 1.2.2.2 mjf cc = &base[lim>>1]; 2728 1.2.2.2 mjf d = c->channel - cc->channel; 2729 1.2.2.2 mjf if (d == 0) { 2730 1.2.2.2 mjf if ((cc->channelFlags & CHAN_FLAGS) == flags) { 2731 1.2.2.2 mjf if ((cc->privFlags & CHANNEL_INTERFERENCE) && 2732 1.2.2.2 mjf (cc->channelFlags & CHANNEL_DFS)) 2733 1.2.2.2 mjf return AH_NULL; 2734 1.2.2.2 mjf else 2735 1.2.2.2 mjf return cc; 2736 1.2.2.2 mjf } 2737 1.2.2.2 mjf d = flags - (cc->channelFlags & CHAN_FLAGS); 2738 1.2.2.2 mjf } 2739 1.2.2.2 mjf if (d > 0) { 2740 1.2.2.2 mjf base = cc + 1; 2741 1.2.2.2 mjf lim--; 2742 1.2.2.2 mjf } 2743 1.2.2.2 mjf } 2744 1.2.2.2 mjf HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: no match for %u/0x%x\n", 2745 1.2.2.2 mjf __func__, c->channel, c->channelFlags); 2746 1.2.2.2 mjf return AH_NULL; 2747 1.2.2.2 mjf #undef CHAN_FLAGS 2748 1.2.2.2 mjf } 2749 1.2.2.2 mjf 2750 1.2.2.2 mjf /* 2751 1.2.2.2 mjf * Return the max allowed antenna gain and apply any regulatory 2752 1.2.2.2 mjf * domain specific changes. 2753 1.2.2.2 mjf * 2754 1.2.2.2 mjf * NOTE: a negative reduction is possible in RD's that only 2755 1.2.2.2 mjf * measure radiated power (e.g., ETSI) which would increase 2756 1.2.2.2 mjf * that actual conducted output power (though never beyond 2757 1.2.2.2 mjf * the calibrated target power). 2758 1.2.2.2 mjf */ 2759 1.2.2.2 mjf u_int 2760 1.2.2.2 mjf ath_hal_getantennareduction(struct ath_hal *ah, HAL_CHANNEL *chan, u_int twiceGain) 2761 1.2.2.2 mjf { 2762 1.2.2.2 mjf HAL_CHANNEL_INTERNAL *ichan=AH_NULL; 2763 1.2.2.2 mjf int8_t antennaMax; 2764 1.2.2.2 mjf 2765 1.2.2.2 mjf if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) { 2766 1.2.2.2 mjf antennaMax = twiceGain - ichan->antennaMax*2; 2767 1.2.2.2 mjf return (antennaMax < 0) ? 0 : antennaMax; 2768 1.2.2.2 mjf } else { 2769 1.2.2.2 mjf /* Failed to find the correct index - may be a debug channel */ 2770 1.2.2.2 mjf return 0; 2771 1.2.2.2 mjf } 2772 1.2.2.2 mjf } 2773 1.2.2.2 mjf 2774 1.2.2.2 mjf 2775 1.2.2.2 mjf /* XXX - maybe move ctl decision into channel set area or 2776 1.2.2.2 mjf into the tables so no decision is needed in the code */ 2777 1.2.2.2 mjf 2778 1.2.2.2 mjf #define isWwrSKU(_ah) \ 2779 1.2.2.2 mjf ((getEepromRD((_ah)) & WORLD_SKU_MASK) == WORLD_SKU_PREFIX || \ 2780 1.2.2.2 mjf getEepromRD(_ah) == WORLD) 2781 1.2.2.2 mjf 2782 1.2.2.2 mjf 2783 1.2.2.2 mjf /* 2784 1.2.2.2 mjf * Return the test group from the specified channel from 2785 1.2.2.2 mjf * the regulatory table. 2786 1.2.2.2 mjf * 2787 1.2.2.2 mjf * TODO: CTL for 11B CommonMode when regulatory domain is unknown 2788 1.2.2.2 mjf */ 2789 1.2.2.2 mjf u_int 2790 1.2.2.2 mjf ath_hal_getctl(struct ath_hal *ah, HAL_CHANNEL *chan) 2791 1.2.2.2 mjf { 2792 1.2.2.2 mjf u_int ctl = NO_CTL; 2793 1.2.2.2 mjf HAL_CHANNEL_INTERNAL *ichan; 2794 1.2.2.2 mjf 2795 1.2.2.2 mjf /* Special CTL to signify WWR SKU without a known country */ 2796 1.2.2.2 mjf if (AH_PRIVATE(ah)->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) { 2797 1.2.2.2 mjf if (IS_CHAN_B(chan)) { 2798 1.2.2.2 mjf ctl = SD_NO_CTL | CTL_11B; 2799 1.2.2.2 mjf } else if (IS_CHAN_G(chan)) { 2800 1.2.2.2 mjf ctl = SD_NO_CTL | CTL_11G; 2801 1.2.2.2 mjf } else if (IS_CHAN_108G(chan)) { 2802 1.2.2.2 mjf ctl = SD_NO_CTL | CTL_108G; 2803 1.2.2.2 mjf } else if (IS_CHAN_T(chan)) { 2804 1.2.2.2 mjf ctl = SD_NO_CTL | CTL_TURBO; 2805 1.2.2.2 mjf } else { 2806 1.2.2.2 mjf ctl = SD_NO_CTL | CTL_11A; 2807 1.2.2.2 mjf } 2808 1.2.2.2 mjf } else { 2809 1.2.2.2 mjf if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) { 2810 1.2.2.2 mjf ctl = ichan->conformanceTestLimit; 2811 1.2.2.2 mjf /* limit 11G OFDM power */ 2812 1.2.2.2 mjf if (IS_CHAN_PUREG(chan) && 2813 1.2.2.2 mjf (ctl & CTL_MODE_M) == CTL_11B) 2814 1.2.2.2 mjf ctl = (ctl &~ CTL_MODE_M) | CTL_11G; 2815 1.2.2.2 mjf } 2816 1.2.2.2 mjf } 2817 1.2.2.2 mjf return ctl; 2818 1.2.2.2 mjf } 2819 1.2.2.2 mjf 2820 1.2.2.2 mjf /* 2821 1.2.2.2 mjf * Return whether or not a noise floor check is required in 2822 1.2.2.2 mjf * the current regulatory domain for the specified channel. 2823 1.2.2.2 mjf */ 2824 1.2.2.2 mjf HAL_BOOL 2825 1.2.2.2 mjf ath_hal_getnfcheckrequired(struct ath_hal *ah, HAL_CHANNEL *chan) 2826 1.2.2.2 mjf { 2827 1.2.2.2 mjf HAL_CHANNEL_INTERNAL *ichan; 2828 1.2.2.2 mjf 2829 1.2.2.2 mjf if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) 2830 1.2.2.2 mjf return ((ichan->regDmnFlags & NEED_NFC) ? AH_TRUE : AH_FALSE); 2831 1.2.2.2 mjf return AH_FALSE; 2832 1.2.2.2 mjf } 2833 1.2.2.2 mjf 2834 1.2.2.2 mjf /* 2835 1.2.2.2 mjf * Insertion sort. 2836 1.2.2.2 mjf */ 2837 1.2.2.2 mjf #define swap(_a, _b, _size) { \ 2838 1.2.2.2 mjf uint8_t *s = _b; \ 2839 1.2.2.2 mjf int i = _size; \ 2840 1.2.2.2 mjf do { \ 2841 1.2.2.2 mjf uint8_t tmp = *_a; \ 2842 1.2.2.2 mjf *_a++ = *s; \ 2843 1.2.2.2 mjf *s++ = tmp; \ 2844 1.2.2.2 mjf } while (--i); \ 2845 1.2.2.2 mjf _a -= _size; \ 2846 1.2.2.2 mjf } 2847 1.2.2.2 mjf 2848 1.2.2.2 mjf static void 2849 1.2.2.2 mjf ath_hal_sort(void *a, size_t n, size_t size, ath_hal_cmp_t *cmp) 2850 1.2.2.2 mjf { 2851 1.2.2.2 mjf uint8_t *aa = a; 2852 1.2.2.2 mjf uint8_t *ai, *t; 2853 1.2.2.2 mjf 2854 1.2.2.2 mjf for (ai = aa+size; --n >= 1; ai += size) 2855 1.2.2.2 mjf for (t = ai; t > aa; t -= size) { 2856 1.2.2.2 mjf uint8_t *u = t - size; 2857 1.2.2.2 mjf if (cmp(u, t) <= 0) 2858 1.2.2.2 mjf break; 2859 1.2.2.2 mjf swap(u, t, size); 2860 1.2.2.2 mjf } 2861 1.2.2.2 mjf } 2862
Indexes created Sun Nov 02 07:10:05 GMT 2025