1b8e80941Smrg/*
2b8e80941Smrg * Copyright © 2014-2018 Broadcom
3b8e80941Smrg *
4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5b8e80941Smrg * copy of this software and associated documentation files (the "Software"),
6b8e80941Smrg * to deal in the Software without restriction, including without limitation
7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the
9b8e80941Smrg * Software is furnished to do so, subject to the following conditions:
10b8e80941Smrg *
11b8e80941Smrg * The above copyright notice and this permission notice (including the next
12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the
13b8e80941Smrg * Software.
14b8e80941Smrg *
15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21b8e80941Smrg * IN THE SOFTWARE.
22b8e80941Smrg */
23b8e80941Smrg
24b8e80941Smrg#ifndef _V3D_DRM_H_
25b8e80941Smrg#define _V3D_DRM_H_
26b8e80941Smrg
27b8e80941Smrg#include "drm.h"
28b8e80941Smrg
29b8e80941Smrg#if defined(__cplusplus)
30b8e80941Smrgextern "C" {
31b8e80941Smrg#endif
32b8e80941Smrg
33b8e80941Smrg#define DRM_V3D_SUBMIT_CL                         0x00
34b8e80941Smrg#define DRM_V3D_WAIT_BO                           0x01
35b8e80941Smrg#define DRM_V3D_CREATE_BO                         0x02
36b8e80941Smrg#define DRM_V3D_MMAP_BO                           0x03
37b8e80941Smrg#define DRM_V3D_GET_PARAM                         0x04
38b8e80941Smrg#define DRM_V3D_GET_BO_OFFSET                     0x05
39b8e80941Smrg#define DRM_V3D_SUBMIT_TFU                        0x06
40b8e80941Smrg
41b8e80941Smrg#define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
42b8e80941Smrg#define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
43b8e80941Smrg#define DRM_IOCTL_V3D_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
44b8e80941Smrg#define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
45b8e80941Smrg#define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
46b8e80941Smrg#define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
47b8e80941Smrg#define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
48b8e80941Smrg
49b8e80941Smrg/**
50b8e80941Smrg * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
51b8e80941Smrg * engine.
52b8e80941Smrg *
53b8e80941Smrg * This asks the kernel to have the GPU execute an optional binner
54b8e80941Smrg * command list, and a render command list.
55b8e80941Smrg *
56b8e80941Smrg * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
57b8e80941Smrg * each CL executes.  The VCD cache should be flushed (if necessary)
58b8e80941Smrg * by the submitted CLs.  The TLB writes are guaranteed to have been
59b8e80941Smrg * flushed by the time the render done IRQ happens, which is the
60b8e80941Smrg * trigger for out_sync.  Any dirtying of cachelines by the job (only
61b8e80941Smrg * possible using TMU writes) must be flushed by the caller using the
62b8e80941Smrg * CL's cache flush commands.
63b8e80941Smrg */
64b8e80941Smrgstruct drm_v3d_submit_cl {
65b8e80941Smrg	/* Pointer to the binner command list.
66b8e80941Smrg	 *
67b8e80941Smrg	 * This is the first set of commands executed, which runs the
68b8e80941Smrg	 * coordinate shader to determine where primitives land on the screen,
69b8e80941Smrg	 * then writes out the state updates and draw calls necessary per tile
70b8e80941Smrg	 * to the tile allocation BO.
71b8e80941Smrg	 *
72b8e80941Smrg	 * This BCL will block on any previous BCL submitted on the
73b8e80941Smrg	 * same FD, but not on any RCL or BCLs submitted by other
74b8e80941Smrg	 * clients -- that is left up to the submitter to control
75b8e80941Smrg	 * using in_sync_bcl if necessary.
76b8e80941Smrg	 */
77b8e80941Smrg	__u32 bcl_start;
78b8e80941Smrg
79b8e80941Smrg	/** End address of the BCL (first byte after the BCL) */
80b8e80941Smrg	__u32 bcl_end;
81b8e80941Smrg
82b8e80941Smrg	/* Offset of the render command list.
83b8e80941Smrg	 *
84b8e80941Smrg	 * This is the second set of commands executed, which will either
85b8e80941Smrg	 * execute the tiles that have been set up by the BCL, or a fixed set
86b8e80941Smrg	 * of tiles (in the case of RCL-only blits).
87b8e80941Smrg	 *
88b8e80941Smrg	 * This RCL will block on this submit's BCL, and any previous
89b8e80941Smrg	 * RCL submitted on the same FD, but not on any RCL or BCLs
90b8e80941Smrg	 * submitted by other clients -- that is left up to the
91b8e80941Smrg	 * submitter to control using in_sync_rcl if necessary.
92b8e80941Smrg	 */
93b8e80941Smrg	__u32 rcl_start;
94b8e80941Smrg
95b8e80941Smrg	/** End address of the RCL (first byte after the RCL) */
96b8e80941Smrg	__u32 rcl_end;
97b8e80941Smrg
98b8e80941Smrg	/** An optional sync object to wait on before starting the BCL. */
99b8e80941Smrg	__u32 in_sync_bcl;
100b8e80941Smrg	/** An optional sync object to wait on before starting the RCL. */
101b8e80941Smrg	__u32 in_sync_rcl;
102b8e80941Smrg	/** An optional sync object to place the completion fence in. */
103b8e80941Smrg	__u32 out_sync;
104b8e80941Smrg
105b8e80941Smrg	/* Offset of the tile alloc memory
106b8e80941Smrg	 *
107b8e80941Smrg	 * This is optional on V3D 3.3 (where the CL can set the value) but
108b8e80941Smrg	 * required on V3D 4.1.
109b8e80941Smrg	 */
110b8e80941Smrg	__u32 qma;
111b8e80941Smrg
112b8e80941Smrg	/** Size of the tile alloc memory. */
113b8e80941Smrg	__u32 qms;
114b8e80941Smrg
115b8e80941Smrg	/** Offset of the tile state data array. */
116b8e80941Smrg	__u32 qts;
117b8e80941Smrg
118b8e80941Smrg	/* Pointer to a u32 array of the BOs that are referenced by the job.
119b8e80941Smrg	 */
120b8e80941Smrg	__u64 bo_handles;
121b8e80941Smrg
122b8e80941Smrg	/* Number of BO handles passed in (size is that times 4). */
123b8e80941Smrg	__u32 bo_handle_count;
124b8e80941Smrg
125b8e80941Smrg	/* Pad, must be zero-filled. */
126b8e80941Smrg	__u32 pad;
127b8e80941Smrg};
128b8e80941Smrg
129b8e80941Smrg/**
130b8e80941Smrg * struct drm_v3d_wait_bo - ioctl argument for waiting for
131b8e80941Smrg * completion of the last DRM_V3D_SUBMIT_CL on a BO.
132b8e80941Smrg *
133b8e80941Smrg * This is useful for cases where multiple processes might be
134b8e80941Smrg * rendering to a BO and you want to wait for all rendering to be
135b8e80941Smrg * completed.
136b8e80941Smrg */
137b8e80941Smrgstruct drm_v3d_wait_bo {
138b8e80941Smrg	__u32 handle;
139b8e80941Smrg	__u32 pad;
140b8e80941Smrg	__u64 timeout_ns;
141b8e80941Smrg};
142b8e80941Smrg
143b8e80941Smrg/**
144b8e80941Smrg * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
145b8e80941Smrg *
146b8e80941Smrg * There are currently no values for the flags argument, but it may be
147b8e80941Smrg * used in a future extension.
148b8e80941Smrg */
149b8e80941Smrgstruct drm_v3d_create_bo {
150b8e80941Smrg	__u32 size;
151b8e80941Smrg	__u32 flags;
152b8e80941Smrg	/** Returned GEM handle for the BO. */
153b8e80941Smrg	__u32 handle;
154b8e80941Smrg	/**
155b8e80941Smrg	 * Returned offset for the BO in the V3D address space.  This offset
156b8e80941Smrg	 * is private to the DRM fd and is valid for the lifetime of the GEM
157b8e80941Smrg	 * handle.
158b8e80941Smrg	 *
159b8e80941Smrg	 * This offset value will always be nonzero, since various HW
160b8e80941Smrg	 * units treat 0 specially.
161b8e80941Smrg	 */
162b8e80941Smrg	__u32 offset;
163b8e80941Smrg};
164b8e80941Smrg
165b8e80941Smrg/**
166b8e80941Smrg * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
167b8e80941Smrg *
168b8e80941Smrg * This doesn't actually perform an mmap.  Instead, it returns the
169b8e80941Smrg * offset you need to use in an mmap on the DRM device node.  This
170b8e80941Smrg * means that tools like valgrind end up knowing about the mapped
171b8e80941Smrg * memory.
172b8e80941Smrg *
173b8e80941Smrg * There are currently no values for the flags argument, but it may be
174b8e80941Smrg * used in a future extension.
175b8e80941Smrg */
176b8e80941Smrgstruct drm_v3d_mmap_bo {
177b8e80941Smrg	/** Handle for the object being mapped. */
178b8e80941Smrg	__u32 handle;
179b8e80941Smrg	__u32 flags;
180b8e80941Smrg	/** offset into the drm node to use for subsequent mmap call. */
181b8e80941Smrg	__u64 offset;
182b8e80941Smrg};
183b8e80941Smrg
184b8e80941Smrgenum drm_v3d_param {
185b8e80941Smrg	DRM_V3D_PARAM_V3D_UIFCFG,
186b8e80941Smrg	DRM_V3D_PARAM_V3D_HUB_IDENT1,
187b8e80941Smrg	DRM_V3D_PARAM_V3D_HUB_IDENT2,
188b8e80941Smrg	DRM_V3D_PARAM_V3D_HUB_IDENT3,
189b8e80941Smrg	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
190b8e80941Smrg	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
191b8e80941Smrg	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
192b8e80941Smrg	DRM_V3D_PARAM_SUPPORTS_TFU,
193b8e80941Smrg};
194b8e80941Smrg
195b8e80941Smrgstruct drm_v3d_get_param {
196b8e80941Smrg	__u32 param;
197b8e80941Smrg	__u32 pad;
198b8e80941Smrg	__u64 value;
199b8e80941Smrg};
200b8e80941Smrg
201b8e80941Smrg/**
202b8e80941Smrg * Returns the offset for the BO in the V3D address space for this DRM fd.
203b8e80941Smrg * This is the same value returned by drm_v3d_create_bo, if that was called
204b8e80941Smrg * from this DRM fd.
205b8e80941Smrg */
206b8e80941Smrgstruct drm_v3d_get_bo_offset {
207b8e80941Smrg	__u32 handle;
208b8e80941Smrg	__u32 offset;
209b8e80941Smrg};
210b8e80941Smrg
211b8e80941Smrgstruct drm_v3d_submit_tfu {
212b8e80941Smrg	__u32 icfg;
213b8e80941Smrg	__u32 iia;
214b8e80941Smrg	__u32 iis;
215b8e80941Smrg	__u32 ica;
216b8e80941Smrg	__u32 iua;
217b8e80941Smrg	__u32 ioa;
218b8e80941Smrg	__u32 ios;
219b8e80941Smrg	__u32 coef[4];
220b8e80941Smrg	/* First handle is the output BO, following are other inputs.
221b8e80941Smrg	 * 0 for unused.
222b8e80941Smrg	 */
223b8e80941Smrg	__u32 bo_handles[4];
224b8e80941Smrg	/* sync object to block on before running the TFU job.  Each TFU
225b8e80941Smrg	 * job will execute in the order submitted to its FD.  Synchronization
226b8e80941Smrg	 * against rendering jobs requires using sync objects.
227b8e80941Smrg	 */
228b8e80941Smrg	__u32 in_sync;
229b8e80941Smrg	/* Sync object to signal when the TFU job is done. */
230b8e80941Smrg	__u32 out_sync;
231b8e80941Smrg};
232b8e80941Smrg
233b8e80941Smrg#if defined(__cplusplus)
234b8e80941Smrg}
235b8e80941Smrg#endif
236b8e80941Smrg
237b8e80941Smrg#endif /* _V3D_DRM_H_ */
238