1b8e80941Smrg/*
2b8e80941Smrg * Copyright © 2007-2018 Advanced Micro Devices, Inc.
3b8e80941Smrg * All Rights Reserved.
4b8e80941Smrg *
5b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining
6b8e80941Smrg * a copy of this software and associated documentation files (the
7b8e80941Smrg * "Software"), to deal in the Software without restriction, including
8b8e80941Smrg * without limitation the rights to use, copy, modify, merge, publish,
9b8e80941Smrg * distribute, sub license, and/or sell copies of the Software, and to
10b8e80941Smrg * permit persons to whom the Software is furnished to do so, subject to
11b8e80941Smrg * the following conditions:
12b8e80941Smrg *
13b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14b8e80941Smrg * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15b8e80941Smrg * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16b8e80941Smrg * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17b8e80941Smrg * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19b8e80941Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20b8e80941Smrg * USE OR OTHER DEALINGS IN THE SOFTWARE.
21b8e80941Smrg *
22b8e80941Smrg * The above copyright notice and this permission notice (including the
23b8e80941Smrg * next paragraph) shall be included in all copies or substantial portions
24b8e80941Smrg * of the Software.
25b8e80941Smrg */
26b8e80941Smrg
27b8e80941Smrg/**
28b8e80941Smrg****************************************************************************************************
29b8e80941Smrg* @file  addrinterface.h
30b8e80941Smrg* @brief Contains the addrlib interfaces declaration and parameter defines
31b8e80941Smrg****************************************************************************************************
32b8e80941Smrg*/
33b8e80941Smrg#ifndef __ADDR_INTERFACE_H__
34b8e80941Smrg#define __ADDR_INTERFACE_H__
35b8e80941Smrg
36b8e80941Smrg#include "addrtypes.h"
37b8e80941Smrg
38b8e80941Smrg#if defined(__cplusplus)
39b8e80941Smrgextern "C"
40b8e80941Smrg{
41b8e80941Smrg#endif
42b8e80941Smrg
43b8e80941Smrg#define ADDRLIB_VERSION_MAJOR 6
44b8e80941Smrg#define ADDRLIB_VERSION_MINOR 2
45b8e80941Smrg#define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR)
46b8e80941Smrg
47b8e80941Smrg/// Virtually all interface functions need ADDR_HANDLE as first parameter
48d4248a18Schristos#ifndef ADDR_HANDLE_TYPEDEF
49d4248a18Schristos#define ADDR_HANDLE_TYPEDEF
50b8e80941Smrgtypedef VOID*   ADDR_HANDLE;
51d4248a18Schristos#endif
52b8e80941Smrg
53b8e80941Smrg/// Client handle used in callbacks
54b8e80941Smrgtypedef VOID*   ADDR_CLIENT_HANDLE;
55b8e80941Smrg
56b8e80941Smrg/**
57b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
58b8e80941Smrg* //                                  Callback functions
59b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
60b8e80941Smrg*    typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
61b8e80941Smrg*         const ADDR_ALLOCSYSMEM_INPUT* pInput);
62b8e80941Smrg*    typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
63b8e80941Smrg*         VOID* pVirtAddr);
64b8e80941Smrg*    typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
65b8e80941Smrg*         const ADDR_DEBUGPRINT_INPUT* pInput);
66b8e80941Smrg*
67b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
68b8e80941Smrg* //                               Create/Destroy/Config functions
69b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
70b8e80941Smrg*     AddrCreate()
71b8e80941Smrg*     AddrDestroy()
72b8e80941Smrg*
73b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
74b8e80941Smrg* //                                  Surface functions
75b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
76b8e80941Smrg*     AddrComputeSurfaceInfo()
77b8e80941Smrg*     AddrComputeSurfaceAddrFromCoord()
78b8e80941Smrg*     AddrComputeSurfaceCoordFromAddr()
79b8e80941Smrg*
80b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
81b8e80941Smrg* //                                   HTile functions
82b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
83b8e80941Smrg*     AddrComputeHtileInfo()
84b8e80941Smrg*     AddrComputeHtileAddrFromCoord()
85b8e80941Smrg*     AddrComputeHtileCoordFromAddr()
86b8e80941Smrg*
87b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
88b8e80941Smrg* //                                   C-mask functions
89b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
90b8e80941Smrg*     AddrComputeCmaskInfo()
91b8e80941Smrg*     AddrComputeCmaskAddrFromCoord()
92b8e80941Smrg*     AddrComputeCmaskCoordFromAddr()
93b8e80941Smrg*
94b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
95b8e80941Smrg* //                                   F-mask functions
96b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
97b8e80941Smrg*     AddrComputeFmaskInfo()
98b8e80941Smrg*     AddrComputeFmaskAddrFromCoord()
99b8e80941Smrg*     AddrComputeFmaskCoordFromAddr()
100b8e80941Smrg*
101b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
102b8e80941Smrg* //                               Element/Utility functions
103b8e80941Smrg* /////////////////////////////////////////////////////////////////////////////////////////////////
104b8e80941Smrg*     ElemFlt32ToDepthPixel()
105b8e80941Smrg*     ElemFlt32ToColorPixel()
106b8e80941Smrg*     AddrExtractBankPipeSwizzle()
107b8e80941Smrg*     AddrCombineBankPipeSwizzle()
108b8e80941Smrg*     AddrComputeSliceSwizzle()
109b8e80941Smrg*     AddrConvertTileInfoToHW()
110b8e80941Smrg*     AddrConvertTileIndex()
111b8e80941Smrg*     AddrConvertTileIndex1()
112b8e80941Smrg*     AddrGetTileIndex()
113b8e80941Smrg*     AddrComputeBaseSwizzle()
114b8e80941Smrg*     AddrUseTileIndex()
115b8e80941Smrg*     AddrUseCombinedSwizzle()
116b8e80941Smrg*
117b8e80941Smrg**/
118b8e80941Smrg
119b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
120b8e80941Smrg//                                      Callback functions
121b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
122b8e80941Smrg
123b8e80941Smrg/**
124b8e80941Smrg****************************************************************************************************
125b8e80941Smrg* @brief channel setting structure
126b8e80941Smrg****************************************************************************************************
127b8e80941Smrg*/
128b8e80941Smrgtypedef union _ADDR_CHANNEL_SETTING
129b8e80941Smrg{
130b8e80941Smrg    struct
131b8e80941Smrg    {
132b8e80941Smrg        UINT_8 valid   : 1;    ///< Indicate whehter this channel setting is valid
133b8e80941Smrg        UINT_8 channel : 2;    ///< 0 for x channel, 1 for y channel, 2 for z channel
134b8e80941Smrg        UINT_8 index   : 5;    ///< Channel index
135b8e80941Smrg    };
136b8e80941Smrg    UINT_8 value;              ///< Value
137b8e80941Smrg} ADDR_CHANNEL_SETTING;
138b8e80941Smrg
139b8e80941Smrg/**
140b8e80941Smrg****************************************************************************************************
141b8e80941Smrg* @brief address equation key structure
142b8e80941Smrg****************************************************************************************************
143b8e80941Smrg*/
144b8e80941Smrgtypedef union _ADDR_EQUATION_KEY
145b8e80941Smrg{
146b8e80941Smrg    struct
147b8e80941Smrg    {
148b8e80941Smrg        UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel
149b8e80941Smrg        UINT_32 tileMode         : 5; ///< Tile mode
150b8e80941Smrg        UINT_32 microTileType    : 3; ///< Micro tile type
151b8e80941Smrg        UINT_32 pipeConfig       : 5; ///< pipe config
152b8e80941Smrg        UINT_32 numBanksLog2     : 3; ///< Number of banks log2
153b8e80941Smrg        UINT_32 bankWidth        : 4; ///< Bank width
154b8e80941Smrg        UINT_32 bankHeight       : 4; ///< Bank height
155b8e80941Smrg        UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio
156b8e80941Smrg        UINT_32 prt              : 1; ///< SI only, indicate whether this equation is for prt
157b8e80941Smrg        UINT_32 reserved         : 1; ///< Reserved bit
158b8e80941Smrg    } fields;
159b8e80941Smrg    UINT_32 value;
160b8e80941Smrg} ADDR_EQUATION_KEY;
161b8e80941Smrg
162b8e80941Smrg/**
163b8e80941Smrg****************************************************************************************************
164b8e80941Smrg* @brief address equation structure
165b8e80941Smrg****************************************************************************************************
166b8e80941Smrg*/
167b8e80941Smrg#define ADDR_MAX_EQUATION_BIT 20u
168b8e80941Smrg
169b8e80941Smrg// Invalid equation index
170b8e80941Smrg#define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF
171b8e80941Smrg
172b8e80941Smrgtypedef struct _ADDR_EQUATION
173b8e80941Smrg{
174b8e80941Smrg    ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT];  ///< addr setting
175b8e80941Smrg                                                       ///< each bit is result of addr ^ xor ^ xor2
176b8e80941Smrg    ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT];  ///< xor setting
177b8e80941Smrg    ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT];  ///< xor2 setting
178b8e80941Smrg    UINT_32              numBits;                      ///< The number of bits in equation
179b8e80941Smrg    BOOL_32              stackedDepthSlices;           ///< TRUE if depth slices are treated as being
180b8e80941Smrg                                                       ///< stacked vertically prior to swizzling
181b8e80941Smrg} ADDR_EQUATION;
182b8e80941Smrg
183b8e80941Smrg/**
184b8e80941Smrg****************************************************************************************************
185b8e80941Smrg* @brief Alloc system memory flags.
186b8e80941Smrg* @note These flags are reserved for future use and if flags are added will minimize the impact
187b8e80941Smrg*       of the client.
188b8e80941Smrg****************************************************************************************************
189b8e80941Smrg*/
190b8e80941Smrgtypedef union _ADDR_ALLOCSYSMEM_FLAGS
191b8e80941Smrg{
192b8e80941Smrg    struct
193b8e80941Smrg    {
194b8e80941Smrg        UINT_32 reserved    : 32;  ///< Reserved for future use.
195b8e80941Smrg    } fields;
196b8e80941Smrg    UINT_32 value;
197b8e80941Smrg
198b8e80941Smrg} ADDR_ALLOCSYSMEM_FLAGS;
199b8e80941Smrg
200b8e80941Smrg/**
201b8e80941Smrg****************************************************************************************************
202b8e80941Smrg* @brief Alloc system memory input structure
203b8e80941Smrg****************************************************************************************************
204b8e80941Smrg*/
205b8e80941Smrgtypedef struct _ADDR_ALLOCSYSMEM_INPUT
206b8e80941Smrg{
207b8e80941Smrg    UINT_32                 size;           ///< Size of this structure in bytes
208b8e80941Smrg
209b8e80941Smrg    ADDR_ALLOCSYSMEM_FLAGS  flags;          ///< System memory flags.
210b8e80941Smrg    UINT_32                 sizeInBytes;    ///< System memory allocation size in bytes.
211b8e80941Smrg    ADDR_CLIENT_HANDLE      hClient;        ///< Client handle
212b8e80941Smrg} ADDR_ALLOCSYSMEM_INPUT;
213b8e80941Smrg
214b8e80941Smrg/**
215b8e80941Smrg****************************************************************************************************
216b8e80941Smrg* ADDR_ALLOCSYSMEM
217b8e80941Smrg*   @brief
218b8e80941Smrg*       Allocate system memory callback function. Returns valid pointer on success.
219b8e80941Smrg****************************************************************************************************
220b8e80941Smrg*/
221b8e80941Smrgtypedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
222b8e80941Smrg    const ADDR_ALLOCSYSMEM_INPUT* pInput);
223b8e80941Smrg
224b8e80941Smrg/**
225b8e80941Smrg****************************************************************************************************
226b8e80941Smrg* @brief Free system memory input structure
227b8e80941Smrg****************************************************************************************************
228b8e80941Smrg*/
229b8e80941Smrgtypedef struct _ADDR_FREESYSMEM_INPUT
230b8e80941Smrg{
231b8e80941Smrg    UINT_32                 size;           ///< Size of this structure in bytes
232b8e80941Smrg
233b8e80941Smrg    VOID*                   pVirtAddr;      ///< Virtual address
234b8e80941Smrg    ADDR_CLIENT_HANDLE      hClient;        ///< Client handle
235b8e80941Smrg} ADDR_FREESYSMEM_INPUT;
236b8e80941Smrg
237b8e80941Smrg/**
238b8e80941Smrg****************************************************************************************************
239b8e80941Smrg* ADDR_FREESYSMEM
240b8e80941Smrg*   @brief
241b8e80941Smrg*       Free system memory callback function.
242b8e80941Smrg*       Returns ADDR_OK on success.
243b8e80941Smrg****************************************************************************************************
244b8e80941Smrg*/
245b8e80941Smrgtypedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
246b8e80941Smrg    const ADDR_FREESYSMEM_INPUT* pInput);
247b8e80941Smrg
248b8e80941Smrg/**
249b8e80941Smrg****************************************************************************************************
250b8e80941Smrg* @brief Print debug message input structure
251b8e80941Smrg****************************************************************************************************
252b8e80941Smrg*/
253b8e80941Smrgtypedef struct _ADDR_DEBUGPRINT_INPUT
254b8e80941Smrg{
255b8e80941Smrg    UINT_32             size;           ///< Size of this structure in bytes
256b8e80941Smrg
257b8e80941Smrg    CHAR*               pDebugString;   ///< Debug print string
258b8e80941Smrg    va_list             ap;             ///< Variable argument list
259b8e80941Smrg    ADDR_CLIENT_HANDLE  hClient;        ///< Client handle
260b8e80941Smrg} ADDR_DEBUGPRINT_INPUT;
261b8e80941Smrg
262b8e80941Smrg/**
263b8e80941Smrg****************************************************************************************************
264b8e80941Smrg* ADDR_DEBUGPRINT
265b8e80941Smrg*   @brief
266b8e80941Smrg*       Print debug message callback function.
267b8e80941Smrg*       Returns ADDR_OK on success.
268b8e80941Smrg****************************************************************************************************
269b8e80941Smrg*/
270b8e80941Smrgtypedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
271b8e80941Smrg    const ADDR_DEBUGPRINT_INPUT* pInput);
272b8e80941Smrg
273b8e80941Smrg/**
274b8e80941Smrg****************************************************************************************************
275b8e80941Smrg* ADDR_CALLBACKS
276b8e80941Smrg*
277b8e80941Smrg*   @brief
278b8e80941Smrg*       Address Library needs client to provide system memory alloc/free routines.
279b8e80941Smrg****************************************************************************************************
280b8e80941Smrg*/
281b8e80941Smrgtypedef struct _ADDR_CALLBACKS
282b8e80941Smrg{
283b8e80941Smrg    ADDR_ALLOCSYSMEM allocSysMem;   ///< Routine to allocate system memory
284b8e80941Smrg    ADDR_FREESYSMEM  freeSysMem;    ///< Routine to free system memory
285b8e80941Smrg    ADDR_DEBUGPRINT  debugPrint;    ///< Routine to print debug message
286b8e80941Smrg} ADDR_CALLBACKS;
287b8e80941Smrg
288b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
289b8e80941Smrg//                               Create/Destroy functions
290b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
291b8e80941Smrg
292b8e80941Smrg/**
293b8e80941Smrg****************************************************************************************************
294b8e80941Smrg* ADDR_CREATE_FLAGS
295b8e80941Smrg*
296b8e80941Smrg*   @brief
297b8e80941Smrg*       This structure is used to pass some setup in creation of AddrLib
298b8e80941Smrg*   @note
299b8e80941Smrg****************************************************************************************************
300b8e80941Smrg*/
301b8e80941Smrgtypedef union _ADDR_CREATE_FLAGS
302b8e80941Smrg{
303b8e80941Smrg    struct
304b8e80941Smrg    {
305b8e80941Smrg        UINT_32 noCubeMipSlicesPad     : 1;    ///< Turn cubemap faces padding off
306b8e80941Smrg        UINT_32 fillSizeFields         : 1;    ///< If clients fill size fields in all input and
307b8e80941Smrg                                               ///  output structure
308b8e80941Smrg        UINT_32 useTileIndex           : 1;    ///< Make tileIndex field in input valid
309b8e80941Smrg        UINT_32 useCombinedSwizzle     : 1;    ///< Use combined tile swizzle
310b8e80941Smrg        UINT_32 checkLast2DLevel       : 1;    ///< Check the last 2D mip sub level
311b8e80941Smrg        UINT_32 useHtileSliceAlign     : 1;    ///< Do htile single slice alignment
312b8e80941Smrg        UINT_32 allowLargeThickTile    : 1;    ///< Allow 64*thickness*bytesPerPixel > rowSize
313b8e80941Smrg        UINT_32 reserved               : 25;   ///< Reserved bits for future use
314b8e80941Smrg    };
315b8e80941Smrg
316b8e80941Smrg    UINT_32 value;
317b8e80941Smrg} ADDR_CREATE_FLAGS;
318b8e80941Smrg
319b8e80941Smrg/**
320b8e80941Smrg****************************************************************************************************
321b8e80941Smrg*   ADDR_REGISTER_VALUE
322b8e80941Smrg*
323b8e80941Smrg*   @brief
324b8e80941Smrg*       Data from registers to setup AddrLib global data, used in AddrCreate
325b8e80941Smrg****************************************************************************************************
326b8e80941Smrg*/
327b8e80941Smrgtypedef struct _ADDR_REGISTER_VALUE
328b8e80941Smrg{
329b8e80941Smrg    UINT_32  gbAddrConfig;       ///< For R8xx, use GB_ADDR_CONFIG register value.
330b8e80941Smrg                                 ///  For R6xx/R7xx, use GB_TILING_CONFIG.
331b8e80941Smrg                                 ///  But they can be treated as the same.
332b8e80941Smrg                                 ///  if this value is 0, use chip to set default value
333b8e80941Smrg    UINT_32  backendDisables;    ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled.
334b8e80941Smrg                                 ///  Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE
335b8e80941Smrg
336b8e80941Smrg                                 ///  R800 registers-----------------------------------------------
337b8e80941Smrg    UINT_32  noOfBanks;          ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK
338b8e80941Smrg                                 ///  No enums for this value in h/w header files
339b8e80941Smrg                                 ///  0: 4
340b8e80941Smrg                                 ///  1: 8
341b8e80941Smrg                                 ///  2: 16
342b8e80941Smrg    UINT_32  noOfRanks;          ///  MC_ARB_RAMCFG.NOOFRANK
343b8e80941Smrg                                 ///  0: 1
344b8e80941Smrg                                 ///  1: 2
345b8e80941Smrg                                 ///  SI (R1000) registers-----------------------------------------
346b8e80941Smrg    const UINT_32* pTileConfig;  ///< Global tile setting tables
347b8e80941Smrg    UINT_32  noOfEntries;        ///< Number of entries in pTileConfig
348b8e80941Smrg
349b8e80941Smrg                                 ///< CI registers-------------------------------------------------
350b8e80941Smrg    const UINT_32* pMacroTileConfig;    ///< Global macro tile mode table
351b8e80941Smrg    UINT_32  noOfMacroEntries;   ///< Number of entries in pMacroTileConfig
352b8e80941Smrg
353b8e80941Smrg                                 ///< GFX9 HW parameters
354b8e80941Smrg    UINT_32  blockVarSizeLog2;   ///< SW_VAR_* block size
355b8e80941Smrg} ADDR_REGISTER_VALUE;
356b8e80941Smrg
357b8e80941Smrg/**
358b8e80941Smrg****************************************************************************************************
359b8e80941Smrg* ADDR_CREATE_INPUT
360b8e80941Smrg*
361b8e80941Smrg*   @brief
362b8e80941Smrg*       Parameters use to create an AddrLib Object. Caller must provide all fields.
363b8e80941Smrg*
364b8e80941Smrg****************************************************************************************************
365b8e80941Smrg*/
366b8e80941Smrgtypedef struct _ADDR_CREATE_INPUT
367b8e80941Smrg{
368b8e80941Smrg    UINT_32             size;                ///< Size of this structure in bytes
369b8e80941Smrg
370b8e80941Smrg    UINT_32             chipEngine;          ///< Chip Engine
371b8e80941Smrg    UINT_32             chipFamily;          ///< Chip Family
372b8e80941Smrg    UINT_32             chipRevision;        ///< Chip Revision
373b8e80941Smrg    ADDR_CALLBACKS      callbacks;           ///< Callbacks for sysmem alloc/free/print
374b8e80941Smrg    ADDR_CREATE_FLAGS   createFlags;         ///< Flags to setup AddrLib
375b8e80941Smrg    ADDR_REGISTER_VALUE regValue;            ///< Data from registers to setup AddrLib global data
376b8e80941Smrg    ADDR_CLIENT_HANDLE  hClient;             ///< Client handle
377b8e80941Smrg    UINT_32             minPitchAlignPixels; ///< Minimum pitch alignment in pixels
378b8e80941Smrg} ADDR_CREATE_INPUT;
379b8e80941Smrg
380b8e80941Smrg/**
381b8e80941Smrg****************************************************************************************************
382b8e80941Smrg* ADDR_CREATEINFO_OUTPUT
383b8e80941Smrg*
384b8e80941Smrg*   @brief
385b8e80941Smrg*       Return AddrLib handle to client driver
386b8e80941Smrg*
387b8e80941Smrg****************************************************************************************************
388b8e80941Smrg*/
389b8e80941Smrgtypedef struct _ADDR_CREATE_OUTPUT
390b8e80941Smrg{
391b8e80941Smrg    UINT_32              size;            ///< Size of this structure in bytes
392b8e80941Smrg
393b8e80941Smrg    ADDR_HANDLE          hLib;            ///< Address lib handle
394b8e80941Smrg
395b8e80941Smrg    UINT_32              numEquations;    ///< Number of equations in the table
396b8e80941Smrg    const ADDR_EQUATION* pEquationTable;  ///< Pointer to the equation table
397b8e80941Smrg} ADDR_CREATE_OUTPUT;
398b8e80941Smrg
399b8e80941Smrg/**
400b8e80941Smrg****************************************************************************************************
401b8e80941Smrg*   AddrCreate
402b8e80941Smrg*
403b8e80941Smrg*   @brief
404b8e80941Smrg*       Create AddrLib object, must be called before any interface calls
405b8e80941Smrg*
406b8e80941Smrg*   @return
407b8e80941Smrg*       ADDR_OK if successful
408b8e80941Smrg****************************************************************************************************
409b8e80941Smrg*/
410b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrCreate(
411b8e80941Smrg    const ADDR_CREATE_INPUT*    pAddrCreateIn,
412b8e80941Smrg    ADDR_CREATE_OUTPUT*         pAddrCreateOut);
413b8e80941Smrg
414b8e80941Smrg/**
415b8e80941Smrg****************************************************************************************************
416b8e80941Smrg*   AddrDestroy
417b8e80941Smrg*
418b8e80941Smrg*   @brief
419b8e80941Smrg*       Destroy AddrLib object, must be called to free internally allocated resources.
420b8e80941Smrg*
421b8e80941Smrg*   @return
422b8e80941Smrg*      ADDR_OK if successful
423b8e80941Smrg****************************************************************************************************
424b8e80941Smrg*/
425b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrDestroy(
426b8e80941Smrg    ADDR_HANDLE hLib);
427b8e80941Smrg
428b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
429b8e80941Smrg//                                    Surface functions
430b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
431b8e80941Smrg
432b8e80941Smrg/**
433b8e80941Smrg****************************************************************************************************
434b8e80941Smrg* @brief
435b8e80941Smrg*       Bank/tiling parameters. On function input, these can be set as desired or
436b8e80941Smrg*       left 0 for AddrLib to calculate/default. On function output, these are the actual
437b8e80941Smrg*       parameters used.
438b8e80941Smrg* @note
439b8e80941Smrg*       Valid bankWidth/bankHeight value:
440b8e80941Smrg*       1,2,4,8. They are factors instead of pixels or bytes.
441b8e80941Smrg*
442b8e80941Smrg*       The bank number remains constant across each row of the
443b8e80941Smrg*       macro tile as each pipe is selected, so the number of
444b8e80941Smrg*       tiles in the x direction with the same bank number will
445b8e80941Smrg*       be bank_width * num_pipes.
446b8e80941Smrg****************************************************************************************************
447b8e80941Smrg*/
448b8e80941Smrgtypedef struct _ADDR_TILEINFO
449b8e80941Smrg{
450b8e80941Smrg    ///  Any of these parameters can be set to 0 to use the HW default.
451b8e80941Smrg    UINT_32     banks;              ///< Number of banks, numerical value
452b8e80941Smrg    UINT_32     bankWidth;          ///< Number of tiles in the X direction in the same bank
453b8e80941Smrg    UINT_32     bankHeight;         ///< Number of tiles in the Y direction in the same bank
454b8e80941Smrg    UINT_32     macroAspectRatio;   ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1
455b8e80941Smrg    UINT_32     tileSplitBytes;     ///< Tile split size, in bytes
456b8e80941Smrg    AddrPipeCfg pipeConfig;         ///< Pipe Config = HW enum + 1
457b8e80941Smrg} ADDR_TILEINFO;
458b8e80941Smrg
459b8e80941Smrg// Create a define to avoid client change. The removal of R800 is because we plan to implement SI
460b8e80941Smrg// within 800 HWL - An AddrPipeCfg is added in above data structure
461b8e80941Smrgtypedef ADDR_TILEINFO ADDR_R800_TILEINFO;
462b8e80941Smrg
463b8e80941Smrg/**
464b8e80941Smrg****************************************************************************************************
465b8e80941Smrg* @brief
466b8e80941Smrg*       Information needed by quad buffer stereo support
467b8e80941Smrg****************************************************************************************************
468b8e80941Smrg*/
469b8e80941Smrgtypedef struct _ADDR_QBSTEREOINFO
470b8e80941Smrg{
471b8e80941Smrg    UINT_32         eyeHeight;          ///< Height (in pixel rows) to right eye
472b8e80941Smrg    UINT_32         rightOffset;        ///< Offset (in bytes) to right eye
473b8e80941Smrg    UINT_32         rightSwizzle;       ///< TileSwizzle for right eyes
474b8e80941Smrg} ADDR_QBSTEREOINFO;
475b8e80941Smrg
476b8e80941Smrg/**
477b8e80941Smrg****************************************************************************************************
478b8e80941Smrg*   ADDR_SURFACE_FLAGS
479b8e80941Smrg*
480b8e80941Smrg*   @brief
481b8e80941Smrg*       Surface flags
482b8e80941Smrg****************************************************************************************************
483b8e80941Smrg*/
484b8e80941Smrgtypedef union _ADDR_SURFACE_FLAGS
485b8e80941Smrg{
486b8e80941Smrg    struct
487b8e80941Smrg    {
488b8e80941Smrg        UINT_32 color                : 1; ///< Flag indicates this is a color buffer
489b8e80941Smrg        UINT_32 depth                : 1; ///< Flag indicates this is a depth/stencil buffer
490b8e80941Smrg        UINT_32 stencil              : 1; ///< Flag indicates this is a stencil buffer
491b8e80941Smrg        UINT_32 texture              : 1; ///< Flag indicates this is a texture
492b8e80941Smrg        UINT_32 cube                 : 1; ///< Flag indicates this is a cubemap
493b8e80941Smrg        UINT_32 volume               : 1; ///< Flag indicates this is a volume texture
494b8e80941Smrg        UINT_32 fmask                : 1; ///< Flag indicates this is an fmask
495b8e80941Smrg        UINT_32 cubeAsArray          : 1; ///< Flag indicates if treat cubemap as arrays
496b8e80941Smrg        UINT_32 compressZ            : 1; ///< Flag indicates z buffer is compressed
497b8e80941Smrg        UINT_32 overlay              : 1; ///< Flag indicates this is an overlay surface
498b8e80941Smrg        UINT_32 noStencil            : 1; ///< Flag indicates this depth has no separate stencil
499b8e80941Smrg        UINT_32 display              : 1; ///< Flag indicates this should match display controller req.
500b8e80941Smrg        UINT_32 opt4Space            : 1; ///< Flag indicates this surface should be optimized for space
501b8e80941Smrg                                          ///  i.e. save some memory but may lose performance
502b8e80941Smrg        UINT_32 prt                  : 1; ///< Flag for partially resident texture
503b8e80941Smrg        UINT_32 qbStereo             : 1; ///< Quad buffer stereo surface
504b8e80941Smrg        UINT_32 pow2Pad              : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)
505b8e80941Smrg        UINT_32 interleaved          : 1; ///< Special flag for interleaved YUV surface padding
506b8e80941Smrg        UINT_32 tcCompatible         : 1; ///< Flag indicates surface needs to be shader readable
507b8e80941Smrg        UINT_32 dispTileType         : 1; ///< NI: force display Tiling for 128 bit shared resoruce
508b8e80941Smrg        UINT_32 dccCompatible        : 1; ///< VI: whether to make MSAA surface support dcc fast clear
509b8e80941Smrg        UINT_32 dccPipeWorkaround    : 1; ///< VI: whether to workaround the HW limit that
510b8e80941Smrg                                          ///  dcc can't be enabled if pipe config of tile mode
511b8e80941Smrg                                          ///  is different from that of ASIC, this flag
512b8e80941Smrg                                          ///  is address lib internal flag, client should ignore it
513b8e80941Smrg        UINT_32 czDispCompatible     : 1; ///< SI+: CZ family has a HW bug needs special alignment.
514b8e80941Smrg                                          ///  This flag indicates we need to follow the
515b8e80941Smrg                                          ///  alignment with CZ families or other ASICs under
516b8e80941Smrg                                          ///  PX configuration + CZ.
517b8e80941Smrg        UINT_32 nonSplit             : 1; ///< CI: depth texture should not be split
518b8e80941Smrg        UINT_32 disableLinearOpt     : 1; ///< Disable tile mode optimization to linear
519b8e80941Smrg        UINT_32 needEquation         : 1; ///< Make the surface tile setting equation compatible.
520b8e80941Smrg                                          ///  This flag indicates we need to override tile
521b8e80941Smrg                                          ///  mode to PRT_* tile mode to disable slice rotation,
522b8e80941Smrg                                          ///  which is needed by swizzle pattern equation.
523b8e80941Smrg        UINT_32 skipIndicesOutput    : 1; ///< Skipping indices in output.
524b8e80941Smrg        UINT_32 rotateDisplay        : 1; ///< Rotate micro tile type
525b8e80941Smrg        UINT_32 minimizeAlignment    : 1; ///< Minimize alignment
526b8e80941Smrg        UINT_32 preferEquation       : 1; ///< Return equation index without adjusting tile mode
527b8e80941Smrg        UINT_32 matchStencilTileCfg  : 1; ///< Select tile index of stencil as well as depth surface
528b8e80941Smrg                                          ///  to make sure they share same tile config parameters
529b8e80941Smrg        UINT_32 disallowLargeThickDegrade   : 1;    ///< Disallow large thick tile degrade
530b8e80941Smrg        UINT_32 reserved             : 1; ///< Reserved bits
531b8e80941Smrg    };
532b8e80941Smrg
533b8e80941Smrg    UINT_32 value;
534b8e80941Smrg} ADDR_SURFACE_FLAGS;
535b8e80941Smrg
536b8e80941Smrg/**
537b8e80941Smrg****************************************************************************************************
538b8e80941Smrg*   ADDR_COMPUTE_SURFACE_INFO_INPUT
539b8e80941Smrg*
540b8e80941Smrg*   @brief
541b8e80941Smrg*       Input structure for AddrComputeSurfaceInfo
542b8e80941Smrg****************************************************************************************************
543b8e80941Smrg*/
544b8e80941Smrgtypedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT
545b8e80941Smrg{
546b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
547b8e80941Smrg
548b8e80941Smrg    AddrTileMode        tileMode;           ///< Tile mode
549b8e80941Smrg    AddrFormat          format;             ///< If format is set to valid one, bpp/width/height
550b8e80941Smrg                                            ///  might be overwritten
551b8e80941Smrg    UINT_32             bpp;                ///< Bits per pixel
552b8e80941Smrg    UINT_32             numSamples;         ///< Number of samples
553b8e80941Smrg    UINT_32             width;              ///< Width, in pixels
554b8e80941Smrg    UINT_32             height;             ///< Height, in pixels
555b8e80941Smrg    UINT_32             numSlices;          ///< Number of surface slices or depth
556b8e80941Smrg    UINT_32             slice;              ///< Slice index
557b8e80941Smrg    UINT_32             mipLevel;           ///< Current mipmap level
558b8e80941Smrg    UINT_32             numMipLevels;       ///< Number of mips in mip chain
559b8e80941Smrg    ADDR_SURFACE_FLAGS  flags;              ///< Surface type flags
560b8e80941Smrg    UINT_32             numFrags;           ///< Number of fragments, leave it zero or the same as
561b8e80941Smrg                                            ///  number of samples for normal AA; Set it to the
562b8e80941Smrg                                            ///  number of fragments for EQAA
563b8e80941Smrg    /// r800 and later HWL parameters
564b8e80941Smrg    // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's
565b8e80941Smrg    ADDR_TILEINFO*      pTileInfo;          ///< 2D tile parameters. Set to 0 to default/calculate
566b8e80941Smrg    AddrTileType        tileType;           ///< Micro tiling type, not needed when tileIndex != -1
567b8e80941Smrg    INT_32              tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
568b8e80941Smrg                                            ///  while the global useTileIndex is set to 1
569b8e80941Smrg    UINT_32             basePitch;          ///< Base level pitch in pixels, 0 means ignored, is a
570b8e80941Smrg                                            ///  must for mip levels from SI+.
571b8e80941Smrg                                            ///  Don't use pitch in blocks for compressed formats!
572b8e80941Smrg    UINT_32             maxBaseAlign;       ///< Max base alignment request from client
573b8e80941Smrg    UINT_32             pitchAlign;         ///< Pitch alignment request from client
574b8e80941Smrg    UINT_32             heightAlign;        ///< Height alignment request from client
575b8e80941Smrg} ADDR_COMPUTE_SURFACE_INFO_INPUT;
576b8e80941Smrg
577b8e80941Smrg/**
578b8e80941Smrg****************************************************************************************************
579b8e80941Smrg*   ADDR_COMPUTE_SURFACE_INFO_OUTPUT
580b8e80941Smrg*
581b8e80941Smrg*   @brief
582b8e80941Smrg*       Output structure for AddrComputeSurfInfo
583b8e80941Smrg*   @note
584b8e80941Smrg        Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
585b8e80941Smrg        Pixel: Original pixel
586b8e80941Smrg****************************************************************************************************
587b8e80941Smrg*/
588b8e80941Smrgtypedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
589b8e80941Smrg{
590b8e80941Smrg    UINT_32         size;           ///< Size of this structure in bytes
591b8e80941Smrg
592b8e80941Smrg    UINT_32         pitch;          ///< Pitch in elements (in blocks for compressed formats)
593b8e80941Smrg    UINT_32         height;         ///< Height in elements (in blocks for compressed formats)
594b8e80941Smrg    UINT_32         depth;          ///< Number of slice/depth
595b8e80941Smrg    UINT_64         surfSize;       ///< Surface size in bytes
596b8e80941Smrg    AddrTileMode    tileMode;       ///< Actual tile mode. May differ from that in input
597b8e80941Smrg    UINT_32         baseAlign;      ///< Base address alignment
598b8e80941Smrg    UINT_32         pitchAlign;     ///< Pitch alignment, in elements
599b8e80941Smrg    UINT_32         heightAlign;    ///< Height alignment, in elements
600b8e80941Smrg    UINT_32         depthAlign;     ///< Depth alignment, aligned to thickness, for 3d texture
601b8e80941Smrg    UINT_32         bpp;            ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit)
602b8e80941Smrg    UINT_32         pixelPitch;     ///< Pitch in original pixels
603b8e80941Smrg    UINT_32         pixelHeight;    ///< Height in original pixels
604b8e80941Smrg    UINT_32         pixelBits;      ///< Original bits per pixel, passed from input
605b8e80941Smrg    UINT_64         sliceSize;      ///< Size of slice specified by input's slice
606b8e80941Smrg                                    ///  The result is controlled by surface flags & createFlags
607b8e80941Smrg                                    ///  By default this value equals to surfSize for volume
608b8e80941Smrg    UINT_32         pitchTileMax;   ///< PITCH_TILE_MAX value for h/w register
609b8e80941Smrg    UINT_32         heightTileMax;  ///< HEIGHT_TILE_MAX value for h/w register
610b8e80941Smrg    UINT_32         sliceTileMax;   ///< SLICE_TILE_MAX value for h/w register
611b8e80941Smrg
612b8e80941Smrg    UINT_32         numSamples;     ///< Pass the effective numSamples processed in this call
613b8e80941Smrg
614b8e80941Smrg    /// r800 and later HWL parameters
615b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;      ///< Tile parameters used. Filled in if 0 on input
616b8e80941Smrg    AddrTileType    tileType;       ///< Micro tiling type, only valid when tileIndex != -1
617b8e80941Smrg    INT_32          tileIndex;      ///< Tile index, MAY be "downgraded"
618b8e80941Smrg
619b8e80941Smrg    INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
620b8e80941Smrg    /// Output flags
621b8e80941Smrg    struct
622b8e80941Smrg    {
623b8e80941Smrg        /// Special information to work around SI mipmap swizzle bug UBTS #317508
624b8e80941Smrg        UINT_32     last2DLevel  : 1;  ///< TRUE if this is the last 2D(3D) tiled
625b8e80941Smrg                                       ///< Only meaningful when create flag checkLast2DLevel is set
626b8e80941Smrg        UINT_32     tcCompatible : 1;  ///< If the surface can be shader compatible
627b8e80941Smrg        UINT_32     dccUnsupport : 1;  ///< If the surface can support DCC compressed rendering
628b8e80941Smrg        UINT_32     prtTileIndex : 1;  ///< SI only, indicate the returned tile index is for PRT
629b8e80941Smrg                                       ///< If address lib return true for mip 0, client should set prt flag
630b8e80941Smrg                                       ///< for child mips in subsequent compute surface info calls
631b8e80941Smrg        UINT_32     reserved     :28;  ///< Reserved bits
632b8e80941Smrg    };
633b8e80941Smrg
634b8e80941Smrg    UINT_32         equationIndex;     ///< Equation index in the equation table;
635b8e80941Smrg
636b8e80941Smrg    UINT_32         blockWidth;        ///< Width in element inside one block(1D->Micro, 2D->Macro)
637b8e80941Smrg    UINT_32         blockHeight;       ///< Height in element inside one block(1D->Micro, 2D->Macro)
638b8e80941Smrg    UINT_32         blockSlices;       ///< Slice number inside one block(1D->Micro, 2D->Macro)
639b8e80941Smrg
640b8e80941Smrg    /// Stereo info
641b8e80941Smrg    ADDR_QBSTEREOINFO*  pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
642b8e80941Smrg
643b8e80941Smrg    INT_32          stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set
644b8e80941Smrg} ADDR_COMPUTE_SURFACE_INFO_OUTPUT;
645b8e80941Smrg
646b8e80941Smrg/**
647b8e80941Smrg****************************************************************************************************
648b8e80941Smrg*   AddrComputeSurfaceInfo
649b8e80941Smrg*
650b8e80941Smrg*   @brief
651b8e80941Smrg*       Compute surface width/height/depth/alignments and suitable tiling mode
652b8e80941Smrg****************************************************************************************************
653b8e80941Smrg*/
654b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
655b8e80941Smrg    ADDR_HANDLE                             hLib,
656b8e80941Smrg    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,
657b8e80941Smrg    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut);
658b8e80941Smrg
659b8e80941Smrg/**
660b8e80941Smrg****************************************************************************************************
661b8e80941Smrg*   ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
662b8e80941Smrg*
663b8e80941Smrg*   @brief
664b8e80941Smrg*       Input structure for AddrComputeSurfaceAddrFromCoord
665b8e80941Smrg****************************************************************************************************
666b8e80941Smrg*/
667b8e80941Smrgtypedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
668b8e80941Smrg{
669b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
670b8e80941Smrg
671b8e80941Smrg    UINT_32         x;                  ///< X coordinate
672b8e80941Smrg    UINT_32         y;                  ///< Y coordinate
673b8e80941Smrg    UINT_32         slice;              ///< Slice index
674b8e80941Smrg    UINT_32         sample;             ///< Sample index, use fragment index for EQAA
675b8e80941Smrg
676b8e80941Smrg    UINT_32         bpp;                ///< Bits per pixel
677b8e80941Smrg    UINT_32         pitch;              ///< Surface pitch, in pixels
678b8e80941Smrg    UINT_32         height;             ///< Surface height, in pixels
679b8e80941Smrg    UINT_32         numSlices;          ///< Surface depth
680b8e80941Smrg    UINT_32         numSamples;         ///< Number of samples
681b8e80941Smrg
682b8e80941Smrg    AddrTileMode    tileMode;           ///< Tile mode
683b8e80941Smrg    BOOL_32         isDepth;            ///< TRUE if the surface uses depth sample ordering within
684b8e80941Smrg                                        ///  micro tile. Textures can also choose depth sample order
685b8e80941Smrg    UINT_32         tileBase;           ///< Base offset (in bits) inside micro tile which handles
686b8e80941Smrg                                        ///  the case that components are stored separately
687b8e80941Smrg    UINT_32         compBits;           ///< The component bits actually needed(for planar surface)
688b8e80941Smrg
689b8e80941Smrg    UINT_32         numFrags;           ///< Number of fragments, leave it zero or the same as
690b8e80941Smrg                                        ///  number of samples for normal AA; Set it to the
691b8e80941Smrg                                        ///  number of fragments for EQAA
692b8e80941Smrg    /// r800 and later HWL parameters
693b8e80941Smrg    // Used for 1D tiling above
694b8e80941Smrg    AddrTileType    tileType;           ///< See defintion of AddrTileType
695b8e80941Smrg    struct
696b8e80941Smrg    {
697b8e80941Smrg        UINT_32     ignoreSE : 1;       ///< TRUE if shader engines are ignored. This is texture
698b8e80941Smrg                                        ///  only flag. Only non-RT texture can set this to TRUE
699b8e80941Smrg        UINT_32     reserved :31;       ///< Reserved for future use.
700b8e80941Smrg    };
701b8e80941Smrg    // 2D tiling needs following structure
702b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;          ///< 2D tile parameters. Client must provide all data
703b8e80941Smrg    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
704b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
705b8e80941Smrg    union
706b8e80941Smrg    {
707b8e80941Smrg        struct
708b8e80941Smrg        {
709b8e80941Smrg            UINT_32  bankSwizzle;       ///< Bank swizzle
710b8e80941Smrg            UINT_32  pipeSwizzle;       ///< Pipe swizzle
711b8e80941Smrg        };
712b8e80941Smrg        UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
713b8e80941Smrg    };
714b8e80941Smrg} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
715b8e80941Smrg
716b8e80941Smrg/**
717b8e80941Smrg****************************************************************************************************
718b8e80941Smrg*   ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
719b8e80941Smrg*
720b8e80941Smrg*   @brief
721b8e80941Smrg*       Output structure for AddrComputeSurfaceAddrFromCoord
722b8e80941Smrg****************************************************************************************************
723b8e80941Smrg*/
724b8e80941Smrgtypedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
725b8e80941Smrg{
726b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
727b8e80941Smrg
728b8e80941Smrg    UINT_64 addr;           ///< Byte address
729b8e80941Smrg    UINT_32 bitPosition;    ///< Bit position within surfaceAddr, 0-7.
730b8e80941Smrg                            ///  For surface bpp < 8, e.g. FMT_1.
731b8e80941Smrg    UINT_32 prtBlockIndex;  ///< Index of a PRT tile (64K block)
732b8e80941Smrg} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
733b8e80941Smrg
734b8e80941Smrg/**
735b8e80941Smrg****************************************************************************************************
736b8e80941Smrg*   AddrComputeSurfaceAddrFromCoord
737b8e80941Smrg*
738b8e80941Smrg*   @brief
739b8e80941Smrg*       Compute surface address from a given coordinate.
740b8e80941Smrg****************************************************************************************************
741b8e80941Smrg*/
742b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
743b8e80941Smrg    ADDR_HANDLE                                     hLib,
744b8e80941Smrg    const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
745b8e80941Smrg    ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut);
746b8e80941Smrg
747b8e80941Smrg/**
748b8e80941Smrg****************************************************************************************************
749b8e80941Smrg*   ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
750b8e80941Smrg*
751b8e80941Smrg*   @brief
752b8e80941Smrg*       Input structure for AddrComputeSurfaceCoordFromAddr
753b8e80941Smrg****************************************************************************************************
754b8e80941Smrg*/
755b8e80941Smrgtypedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
756b8e80941Smrg{
757b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
758b8e80941Smrg
759b8e80941Smrg    UINT_64         addr;               ///< Address in bytes
760b8e80941Smrg    UINT_32         bitPosition;        ///< Bit position in addr. 0-7. for surface bpp < 8,
761b8e80941Smrg                                        ///  e.g. FMT_1;
762b8e80941Smrg    UINT_32         bpp;                ///< Bits per pixel
763b8e80941Smrg    UINT_32         pitch;              ///< Pitch, in pixels
764b8e80941Smrg    UINT_32         height;             ///< Height in pixels
765b8e80941Smrg    UINT_32         numSlices;          ///< Surface depth
766b8e80941Smrg    UINT_32         numSamples;         ///< Number of samples
767b8e80941Smrg
768b8e80941Smrg    AddrTileMode    tileMode;           ///< Tile mode
769b8e80941Smrg    BOOL_32         isDepth;            ///< Surface uses depth sample ordering within micro tile.
770b8e80941Smrg                                        ///  Note: Textures can choose depth sample order as well.
771b8e80941Smrg    UINT_32         tileBase;           ///< Base offset (in bits) inside micro tile which handles
772b8e80941Smrg                                        ///  the case that components are stored separately
773b8e80941Smrg    UINT_32         compBits;           ///< The component bits actually needed(for planar surface)
774b8e80941Smrg
775b8e80941Smrg    UINT_32         numFrags;           ///< Number of fragments, leave it zero or the same as
776b8e80941Smrg                                        ///  number of samples for normal AA; Set it to the
777b8e80941Smrg                                        ///  number of fragments for EQAA
778b8e80941Smrg    /// r800 and later HWL parameters
779b8e80941Smrg    // Used for 1D tiling above
780b8e80941Smrg    AddrTileType    tileType;           ///< See defintion of AddrTileType
781b8e80941Smrg    struct
782b8e80941Smrg    {
783b8e80941Smrg        UINT_32     ignoreSE : 1;       ///< TRUE if shader engines are ignored. This is texture
784b8e80941Smrg                                        ///  only flag. Only non-RT texture can set this to TRUE
785b8e80941Smrg        UINT_32     reserved :31;       ///< Reserved for future use.
786b8e80941Smrg    };
787b8e80941Smrg    // 2D tiling needs following structure
788b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;          ///< 2D tile parameters. Client must provide all data
789b8e80941Smrg    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
790b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
791b8e80941Smrg    union
792b8e80941Smrg    {
793b8e80941Smrg        struct
794b8e80941Smrg        {
795b8e80941Smrg            UINT_32  bankSwizzle;       ///< Bank swizzle
796b8e80941Smrg            UINT_32  pipeSwizzle;       ///< Pipe swizzle
797b8e80941Smrg        };
798b8e80941Smrg        UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
799b8e80941Smrg    };
800b8e80941Smrg} ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
801b8e80941Smrg
802b8e80941Smrg/**
803b8e80941Smrg****************************************************************************************************
804b8e80941Smrg*   ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
805b8e80941Smrg*
806b8e80941Smrg*   @brief
807b8e80941Smrg*       Output structure for AddrComputeSurfaceCoordFromAddr
808b8e80941Smrg****************************************************************************************************
809b8e80941Smrg*/
810b8e80941Smrgtypedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
811b8e80941Smrg{
812b8e80941Smrg    UINT_32 size;   ///< Size of this structure in bytes
813b8e80941Smrg
814b8e80941Smrg    UINT_32 x;      ///< X coordinate
815b8e80941Smrg    UINT_32 y;      ///< Y coordinate
816b8e80941Smrg    UINT_32 slice;  ///< Index of slices
817b8e80941Smrg    UINT_32 sample; ///< Index of samples, means fragment index for EQAA
818b8e80941Smrg} ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
819b8e80941Smrg
820b8e80941Smrg/**
821b8e80941Smrg****************************************************************************************************
822b8e80941Smrg*   AddrComputeSurfaceCoordFromAddr
823b8e80941Smrg*
824b8e80941Smrg*   @brief
825b8e80941Smrg*       Compute coordinate from a given surface address
826b8e80941Smrg****************************************************************************************************
827b8e80941Smrg*/
828b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
829b8e80941Smrg    ADDR_HANDLE                                     hLib,
830b8e80941Smrg    const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
831b8e80941Smrg    ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut);
832b8e80941Smrg
833b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
834b8e80941Smrg//                                   HTile functions
835b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
836b8e80941Smrg
837b8e80941Smrg/**
838b8e80941Smrg****************************************************************************************************
839b8e80941Smrg*   ADDR_HTILE_FLAGS
840b8e80941Smrg*
841b8e80941Smrg*   @brief
842b8e80941Smrg*       HTILE flags
843b8e80941Smrg****************************************************************************************************
844b8e80941Smrg*/
845b8e80941Smrgtypedef union _ADDR_HTILE_FLAGS
846b8e80941Smrg{
847b8e80941Smrg    struct
848b8e80941Smrg    {
849b8e80941Smrg        UINT_32 tcCompatible          : 1;  ///< Flag indicates surface needs to be shader readable
850b8e80941Smrg        UINT_32 skipTcCompatSizeAlign : 1;  ///< Flag indicates that addrLib will not align htile
851b8e80941Smrg                                            ///  size to 256xBankxPipe when computing tc-compatible
852b8e80941Smrg                                            ///  htile info.
853b8e80941Smrg        UINT_32 reserved              : 30; ///< Reserved bits
854b8e80941Smrg    };
855b8e80941Smrg
856b8e80941Smrg    UINT_32 value;
857b8e80941Smrg} ADDR_HTILE_FLAGS;
858b8e80941Smrg
859b8e80941Smrg/**
860b8e80941Smrg****************************************************************************************************
861b8e80941Smrg*   ADDR_COMPUTE_HTILE_INFO_INPUT
862b8e80941Smrg*
863b8e80941Smrg*   @brief
864b8e80941Smrg*       Input structure of AddrComputeHtileInfo
865b8e80941Smrg****************************************************************************************************
866b8e80941Smrg*/
867b8e80941Smrgtypedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT
868b8e80941Smrg{
869b8e80941Smrg    UINT_32            size;            ///< Size of this structure in bytes
870b8e80941Smrg
871b8e80941Smrg    ADDR_HTILE_FLAGS   flags;           ///< HTILE flags
872b8e80941Smrg    UINT_32            pitch;           ///< Surface pitch, in pixels
873b8e80941Smrg    UINT_32            height;          ///< Surface height, in pixels
874b8e80941Smrg    UINT_32            numSlices;       ///< Number of slices
875b8e80941Smrg    BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
876b8e80941Smrg    AddrHtileBlockSize blockWidth;      ///< 4 or 8. EG above only support 8
877b8e80941Smrg    AddrHtileBlockSize blockHeight;     ///< 4 or 8. EG above only support 8
878b8e80941Smrg    ADDR_TILEINFO*     pTileInfo;       ///< Tile info
879b8e80941Smrg
880b8e80941Smrg    INT_32             tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
881b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
882b8e80941Smrg    INT_32             macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
883b8e80941Smrg                                        ///< README: When tileIndex is not -1, this must be valid
884b8e80941Smrg} ADDR_COMPUTE_HTILE_INFO_INPUT;
885b8e80941Smrg
886b8e80941Smrg/**
887b8e80941Smrg****************************************************************************************************
888b8e80941Smrg*   ADDR_COMPUTE_HTILE_INFO_OUTPUT
889b8e80941Smrg*
890b8e80941Smrg*   @brief
891b8e80941Smrg*       Output structure of AddrComputeHtileInfo
892b8e80941Smrg****************************************************************************************************
893b8e80941Smrg*/
894b8e80941Smrgtypedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
895b8e80941Smrg{
896b8e80941Smrg    UINT_32 size;               ///< Size of this structure in bytes
897b8e80941Smrg
898b8e80941Smrg    UINT_32 pitch;              ///< Pitch in pixels of depth buffer represented in this
899b8e80941Smrg                                ///  HTile buffer. This might be larger than original depth
900b8e80941Smrg                                ///  buffer pitch when called with an unaligned pitch.
901b8e80941Smrg    UINT_32 height;             ///< Height in pixels, as above
902b8e80941Smrg    UINT_64 htileBytes;         ///< Size of HTILE buffer, in bytes
903b8e80941Smrg    UINT_32 baseAlign;          ///< Base alignment
904b8e80941Smrg    UINT_32 bpp;                ///< Bits per pixel for HTILE is how many bits for an 8x8 block!
905b8e80941Smrg    UINT_32 macroWidth;         ///< Macro width in pixels, actually squared cache shape
906b8e80941Smrg    UINT_32 macroHeight;        ///< Macro height in pixels
907b8e80941Smrg    UINT_64 sliceSize;          ///< Slice size, in bytes.
908b8e80941Smrg    BOOL_32 sliceInterleaved;   ///< Flag to indicate if different slice's htile is interleaved
909b8e80941Smrg                                ///  Compute engine clear can't be used if htile is interleaved
910b8e80941Smrg    BOOL_32 nextMipLevelCompressible;   ///< Flag to indicate whether HTILE can be enabled in
911b8e80941Smrg                                        ///  next mip level, it also indicates if memory set based
912b8e80941Smrg                                        ///  fast clear can be used for current mip level.
913b8e80941Smrg} ADDR_COMPUTE_HTILE_INFO_OUTPUT;
914b8e80941Smrg
915b8e80941Smrg/**
916b8e80941Smrg****************************************************************************************************
917b8e80941Smrg*   AddrComputeHtileInfo
918b8e80941Smrg*
919b8e80941Smrg*   @brief
920b8e80941Smrg*       Compute Htile pitch, height, base alignment and size in bytes
921b8e80941Smrg****************************************************************************************************
922b8e80941Smrg*/
923b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
924b8e80941Smrg    ADDR_HANDLE                             hLib,
925b8e80941Smrg    const ADDR_COMPUTE_HTILE_INFO_INPUT*    pIn,
926b8e80941Smrg    ADDR_COMPUTE_HTILE_INFO_OUTPUT*         pOut);
927b8e80941Smrg
928b8e80941Smrg/**
929b8e80941Smrg****************************************************************************************************
930b8e80941Smrg*   ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
931b8e80941Smrg*
932b8e80941Smrg*   @brief
933b8e80941Smrg*       Input structure for AddrComputeHtileAddrFromCoord
934b8e80941Smrg****************************************************************************************************
935b8e80941Smrg*/
936b8e80941Smrgtypedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
937b8e80941Smrg{
938b8e80941Smrg    UINT_32            size;            ///< Size of this structure in bytes
939b8e80941Smrg
940b8e80941Smrg    UINT_32            pitch;           ///< Pitch, in pixels
941b8e80941Smrg    UINT_32            height;          ///< Height in pixels
942b8e80941Smrg    UINT_32            x;               ///< X coordinate
943b8e80941Smrg    UINT_32            y;               ///< Y coordinate
944b8e80941Smrg    UINT_32            slice;           ///< Index of slice
945b8e80941Smrg    UINT_32            numSlices;       ///< Number of slices
946b8e80941Smrg    BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
947b8e80941Smrg    ADDR_HTILE_FLAGS   flags;           ///< htile flags
948b8e80941Smrg    AddrHtileBlockSize blockWidth;      ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
949b8e80941Smrg    AddrHtileBlockSize blockHeight;     ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
950b8e80941Smrg    ADDR_TILEINFO*     pTileInfo;       ///< Tile info
951b8e80941Smrg
952b8e80941Smrg    INT_32             tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
953b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
954b8e80941Smrg    INT_32             macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
955b8e80941Smrg                                        ///< README: When tileIndex is not -1, this must be valid
956b8e80941Smrg    UINT_32            bpp;             ///< depth/stencil buffer bit per pixel size
957b8e80941Smrg    UINT_32            zStencilAddr;    ///< tcCompatible Z/Stencil surface address
958b8e80941Smrg} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
959b8e80941Smrg
960b8e80941Smrg/**
961b8e80941Smrg****************************************************************************************************
962b8e80941Smrg*   ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
963b8e80941Smrg*
964b8e80941Smrg*   @brief
965b8e80941Smrg*       Output structure for AddrComputeHtileAddrFromCoord
966b8e80941Smrg****************************************************************************************************
967b8e80941Smrg*/
968b8e80941Smrgtypedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
969b8e80941Smrg{
970b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
971b8e80941Smrg
972b8e80941Smrg    UINT_64 addr;           ///< Address in bytes
973b8e80941Smrg    UINT_32 bitPosition;    ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method.
974b8e80941Smrg                            ///  So we keep bitPosition for HTILE as well
975b8e80941Smrg} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
976b8e80941Smrg
977b8e80941Smrg/**
978b8e80941Smrg****************************************************************************************************
979b8e80941Smrg*   AddrComputeHtileAddrFromCoord
980b8e80941Smrg*
981b8e80941Smrg*   @brief
982b8e80941Smrg*       Compute Htile address according to coordinates (of depth buffer)
983b8e80941Smrg****************************************************************************************************
984b8e80941Smrg*/
985b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
986b8e80941Smrg    ADDR_HANDLE                                     hLib,
987b8e80941Smrg    const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*   pIn,
988b8e80941Smrg    ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*        pOut);
989b8e80941Smrg
990b8e80941Smrg/**
991b8e80941Smrg****************************************************************************************************
992b8e80941Smrg*   ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
993b8e80941Smrg*
994b8e80941Smrg*   @brief
995b8e80941Smrg*       Input structure for AddrComputeHtileCoordFromAddr
996b8e80941Smrg****************************************************************************************************
997b8e80941Smrg*/
998b8e80941Smrgtypedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
999b8e80941Smrg{
1000b8e80941Smrg    UINT_32            size;            ///< Size of this structure in bytes
1001b8e80941Smrg
1002b8e80941Smrg    UINT_64            addr;            ///< Address
1003b8e80941Smrg    UINT_32            bitPosition;     ///< Bit position 0 or 4. CMASK and HTILE share some methods
1004b8e80941Smrg                                        ///  so we keep bitPosition for HTILE as well
1005b8e80941Smrg    UINT_32            pitch;           ///< Pitch, in pixels
1006b8e80941Smrg    UINT_32            height;          ///< Height, in pixels
1007b8e80941Smrg    UINT_32            numSlices;       ///< Number of slices
1008b8e80941Smrg    BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
1009b8e80941Smrg    AddrHtileBlockSize blockWidth;      ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1010b8e80941Smrg    AddrHtileBlockSize blockHeight;     ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1011b8e80941Smrg    ADDR_TILEINFO*     pTileInfo;       ///< Tile info
1012b8e80941Smrg
1013b8e80941Smrg    INT_32             tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
1014b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
1015b8e80941Smrg    INT_32             macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
1016b8e80941Smrg                                        ///< README: When tileIndex is not -1, this must be valid
1017b8e80941Smrg} ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT;
1018b8e80941Smrg
1019b8e80941Smrg/**
1020b8e80941Smrg****************************************************************************************************
1021b8e80941Smrg*   ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1022b8e80941Smrg*
1023b8e80941Smrg*   @brief
1024b8e80941Smrg*       Output structure for AddrComputeHtileCoordFromAddr
1025b8e80941Smrg****************************************************************************************************
1026b8e80941Smrg*/
1027b8e80941Smrgtypedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1028b8e80941Smrg{
1029b8e80941Smrg    UINT_32 size;   ///< Size of this structure in bytes
1030b8e80941Smrg
1031b8e80941Smrg    UINT_32 x;      ///< X coordinate
1032b8e80941Smrg    UINT_32 y;      ///< Y coordinate
1033b8e80941Smrg    UINT_32 slice;  ///< Slice index
1034b8e80941Smrg} ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
1035b8e80941Smrg
1036b8e80941Smrg/**
1037b8e80941Smrg****************************************************************************************************
1038b8e80941Smrg*   AddrComputeHtileCoordFromAddr
1039b8e80941Smrg*
1040b8e80941Smrg*   @brief
1041b8e80941Smrg*       Compute coordinates within depth buffer (1st pixel of a micro tile) according to
1042b8e80941Smrg*       Htile address
1043b8e80941Smrg****************************************************************************************************
1044b8e80941Smrg*/
1045b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
1046b8e80941Smrg    ADDR_HANDLE                                     hLib,
1047b8e80941Smrg    const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT*   pIn,
1048b8e80941Smrg    ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*        pOut);
1049b8e80941Smrg
1050b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
1051b8e80941Smrg//                                     C-mask functions
1052b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
1053b8e80941Smrg
1054b8e80941Smrg/**
1055b8e80941Smrg****************************************************************************************************
1056b8e80941Smrg*   ADDR_CMASK_FLAGS
1057b8e80941Smrg*
1058b8e80941Smrg*   @brief
1059b8e80941Smrg*       CMASK flags
1060b8e80941Smrg****************************************************************************************************
1061b8e80941Smrg*/
1062b8e80941Smrgtypedef union _ADDR_CMASK_FLAGS
1063b8e80941Smrg{
1064b8e80941Smrg    struct
1065b8e80941Smrg    {
1066b8e80941Smrg        UINT_32 tcCompatible  : 1; ///< Flag indicates surface needs to be shader readable
1067b8e80941Smrg        UINT_32 reserved      :31; ///< Reserved bits
1068b8e80941Smrg    };
1069b8e80941Smrg
1070b8e80941Smrg    UINT_32 value;
1071b8e80941Smrg} ADDR_CMASK_FLAGS;
1072b8e80941Smrg
1073b8e80941Smrg/**
1074b8e80941Smrg****************************************************************************************************
1075b8e80941Smrg*   ADDR_COMPUTE_CMASK_INFO_INPUT
1076b8e80941Smrg*
1077b8e80941Smrg*   @brief
1078b8e80941Smrg*       Input structure of AddrComputeCmaskInfo
1079b8e80941Smrg****************************************************************************************************
1080b8e80941Smrg*/
1081b8e80941Smrgtypedef struct _ADDR_COMPUTE_CMASKINFO_INPUT
1082b8e80941Smrg{
1083b8e80941Smrg    UINT_32             size;            ///< Size of this structure in bytes
1084b8e80941Smrg
1085b8e80941Smrg    ADDR_CMASK_FLAGS    flags;           ///< CMASK flags
1086b8e80941Smrg    UINT_32             pitch;           ///< Pitch, in pixels, of color buffer
1087b8e80941Smrg    UINT_32             height;          ///< Height, in pixels, of color buffer
1088b8e80941Smrg    UINT_32             numSlices;       ///< Number of slices, of color buffer
1089b8e80941Smrg    BOOL_32             isLinear;        ///< Linear or tiled layout, Only SI can be linear
1090b8e80941Smrg    ADDR_TILEINFO*      pTileInfo;       ///< Tile info
1091b8e80941Smrg
1092b8e80941Smrg    INT_32              tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
1093b8e80941Smrg                                         ///  while the global useTileIndex is set to 1
1094b8e80941Smrg    INT_32              macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
1095b8e80941Smrg                                         ///< README: When tileIndex is not -1, this must be valid
1096b8e80941Smrg} ADDR_COMPUTE_CMASK_INFO_INPUT;
1097b8e80941Smrg
1098b8e80941Smrg/**
1099b8e80941Smrg****************************************************************************************************
1100b8e80941Smrg*   ADDR_COMPUTE_CMASK_INFO_OUTPUT
1101b8e80941Smrg*
1102b8e80941Smrg*   @brief
1103b8e80941Smrg*       Output structure of AddrComputeCmaskInfo
1104b8e80941Smrg****************************************************************************************************
1105b8e80941Smrg*/
1106b8e80941Smrgtypedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT
1107b8e80941Smrg{
1108b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
1109b8e80941Smrg
1110b8e80941Smrg    UINT_32 pitch;          ///< Pitch in pixels of color buffer which
1111b8e80941Smrg                            ///  this Cmask matches. The size might be larger than
1112b8e80941Smrg                            ///  original color buffer pitch when called with
1113b8e80941Smrg                            ///  an unaligned pitch.
1114b8e80941Smrg    UINT_32 height;         ///< Height in pixels, as above
1115b8e80941Smrg    UINT_64 cmaskBytes;     ///< Size in bytes of CMask buffer
1116b8e80941Smrg    UINT_32 baseAlign;      ///< Base alignment
1117b8e80941Smrg    UINT_32 blockMax;       ///< Cmask block size. Need this to set CB_COLORn_MASK register
1118b8e80941Smrg    UINT_32 macroWidth;     ///< Macro width in pixels, actually squared cache shape
1119b8e80941Smrg    UINT_32 macroHeight;    ///< Macro height in pixels
1120b8e80941Smrg    UINT_64 sliceSize;      ///< Slice size, in bytes.
1121b8e80941Smrg} ADDR_COMPUTE_CMASK_INFO_OUTPUT;
1122b8e80941Smrg
1123b8e80941Smrg/**
1124b8e80941Smrg****************************************************************************************************
1125b8e80941Smrg*   AddrComputeCmaskInfo
1126b8e80941Smrg*
1127b8e80941Smrg*   @brief
1128b8e80941Smrg*       Compute Cmask pitch, height, base alignment and size in bytes from color buffer
1129b8e80941Smrg*       info
1130b8e80941Smrg****************************************************************************************************
1131b8e80941Smrg*/
1132b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
1133b8e80941Smrg    ADDR_HANDLE                             hLib,
1134b8e80941Smrg    const ADDR_COMPUTE_CMASK_INFO_INPUT*    pIn,
1135b8e80941Smrg    ADDR_COMPUTE_CMASK_INFO_OUTPUT*         pOut);
1136b8e80941Smrg
1137b8e80941Smrg/**
1138b8e80941Smrg****************************************************************************************************
1139b8e80941Smrg*   ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1140b8e80941Smrg*
1141b8e80941Smrg*   @brief
1142b8e80941Smrg*       Input structure for AddrComputeCmaskAddrFromCoord
1143b8e80941Smrg*
1144b8e80941Smrg****************************************************************************************************
1145b8e80941Smrg*/
1146b8e80941Smrgtypedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1147b8e80941Smrg{
1148b8e80941Smrg    UINT_32          size;           ///< Size of this structure in bytes
1149b8e80941Smrg    UINT_32          x;              ///< X coordinate
1150b8e80941Smrg    UINT_32          y;              ///< Y coordinate
1151b8e80941Smrg    UINT_64          fmaskAddr;      ///< Fmask addr for tc compatible Cmask
1152b8e80941Smrg    UINT_32          slice;          ///< Slice index
1153b8e80941Smrg    UINT_32          pitch;          ///< Pitch in pixels, of color buffer
1154b8e80941Smrg    UINT_32          height;         ///< Height in pixels, of color buffer
1155b8e80941Smrg    UINT_32          numSlices;      ///< Number of slices
1156b8e80941Smrg    UINT_32          bpp;
1157b8e80941Smrg    BOOL_32          isLinear;       ///< Linear or tiled layout, Only SI can be linear
1158b8e80941Smrg    ADDR_CMASK_FLAGS flags;          ///< CMASK flags
1159b8e80941Smrg    ADDR_TILEINFO*   pTileInfo;      ///< Tile info
1160b8e80941Smrg
1161b8e80941Smrg    INT_32           tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
1162b8e80941Smrg                                     ///< while the global useTileIndex is set to 1
1163b8e80941Smrg    INT_32           macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1164b8e80941Smrg                                     ///< README: When tileIndex is not -1, this must be valid
1165b8e80941Smrg} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
1166b8e80941Smrg
1167b8e80941Smrg/**
1168b8e80941Smrg****************************************************************************************************
1169b8e80941Smrg*   ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1170b8e80941Smrg*
1171b8e80941Smrg*   @brief
1172b8e80941Smrg*       Output structure for AddrComputeCmaskAddrFromCoord
1173b8e80941Smrg****************************************************************************************************
1174b8e80941Smrg*/
1175b8e80941Smrgtypedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1176b8e80941Smrg{
1177b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
1178b8e80941Smrg
1179b8e80941Smrg    UINT_64 addr;           ///< CMASK address in bytes
1180b8e80941Smrg    UINT_32 bitPosition;    ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1181b8e80941Smrg                            ///  so the address may be located in bit 0 (0) or 4 (4)
1182b8e80941Smrg} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
1183b8e80941Smrg
1184b8e80941Smrg/**
1185b8e80941Smrg****************************************************************************************************
1186b8e80941Smrg*   AddrComputeCmaskAddrFromCoord
1187b8e80941Smrg*
1188b8e80941Smrg*   @brief
1189b8e80941Smrg*       Compute Cmask address according to coordinates (of MSAA color buffer)
1190b8e80941Smrg****************************************************************************************************
1191b8e80941Smrg*/
1192b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
1193b8e80941Smrg    ADDR_HANDLE                                     hLib,
1194b8e80941Smrg    const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*   pIn,
1195b8e80941Smrg    ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut);
1196b8e80941Smrg
1197b8e80941Smrg/**
1198b8e80941Smrg****************************************************************************************************
1199b8e80941Smrg*   ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1200b8e80941Smrg*
1201b8e80941Smrg*   @brief
1202b8e80941Smrg*       Input structure for AddrComputeCmaskCoordFromAddr
1203b8e80941Smrg****************************************************************************************************
1204b8e80941Smrg*/
1205b8e80941Smrgtypedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1206b8e80941Smrg{
1207b8e80941Smrg    UINT_32        size;            ///< Size of this structure in bytes
1208b8e80941Smrg
1209b8e80941Smrg    UINT_64        addr;            ///< CMASK address in bytes
1210b8e80941Smrg    UINT_32        bitPosition;     ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1211b8e80941Smrg                                    ///  so the address may be located in bit 0 (0) or 4 (4)
1212b8e80941Smrg    UINT_32        pitch;           ///< Pitch, in pixels
1213b8e80941Smrg    UINT_32        height;          ///< Height in pixels
1214b8e80941Smrg    UINT_32        numSlices;       ///< Number of slices
1215b8e80941Smrg    BOOL_32        isLinear;        ///< Linear or tiled layout, Only SI can be linear
1216b8e80941Smrg    ADDR_TILEINFO* pTileInfo;       ///< Tile info
1217b8e80941Smrg
1218b8e80941Smrg    INT_32         tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
1219b8e80941Smrg                                    ///  while the global useTileIndex is set to 1
1220b8e80941Smrg    INT_32         macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
1221b8e80941Smrg                                    ///< README: When tileIndex is not -1, this must be valid
1222b8e80941Smrg} ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT;
1223b8e80941Smrg
1224b8e80941Smrg/**
1225b8e80941Smrg****************************************************************************************************
1226b8e80941Smrg*   ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1227b8e80941Smrg*
1228b8e80941Smrg*   @brief
1229b8e80941Smrg*       Output structure for AddrComputeCmaskCoordFromAddr
1230b8e80941Smrg****************************************************************************************************
1231b8e80941Smrg*/
1232b8e80941Smrgtypedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1233b8e80941Smrg{
1234b8e80941Smrg    UINT_32 size;   ///< Size of this structure in bytes
1235b8e80941Smrg
1236b8e80941Smrg    UINT_32 x;      ///< X coordinate
1237b8e80941Smrg    UINT_32 y;      ///< Y coordinate
1238b8e80941Smrg    UINT_32 slice;  ///< Slice index
1239b8e80941Smrg} ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
1240b8e80941Smrg
1241b8e80941Smrg/**
1242b8e80941Smrg****************************************************************************************************
1243b8e80941Smrg*   AddrComputeCmaskCoordFromAddr
1244b8e80941Smrg*
1245b8e80941Smrg*   @brief
1246b8e80941Smrg*       Compute coordinates within color buffer (1st pixel of a micro tile) according to
1247b8e80941Smrg*       Cmask address
1248b8e80941Smrg****************************************************************************************************
1249b8e80941Smrg*/
1250b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
1251b8e80941Smrg    ADDR_HANDLE                                     hLib,
1252b8e80941Smrg    const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT*   pIn,
1253b8e80941Smrg    ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*        pOut);
1254b8e80941Smrg
1255b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
1256b8e80941Smrg//                                     F-mask functions
1257b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
1258b8e80941Smrg
1259b8e80941Smrg/**
1260b8e80941Smrg****************************************************************************************************
1261b8e80941Smrg*   ADDR_COMPUTE_FMASK_INFO_INPUT
1262b8e80941Smrg*
1263b8e80941Smrg*   @brief
1264b8e80941Smrg*       Input structure for AddrComputeFmaskInfo
1265b8e80941Smrg****************************************************************************************************
1266b8e80941Smrg*/
1267b8e80941Smrgtypedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT
1268b8e80941Smrg{
1269b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
1270b8e80941Smrg
1271b8e80941Smrg    AddrTileMode    tileMode;           ///< Tile mode
1272b8e80941Smrg    UINT_32         pitch;              ///< Surface pitch, in pixels
1273b8e80941Smrg    UINT_32         height;             ///< Surface height, in pixels
1274b8e80941Smrg    UINT_32         numSlices;          ///< Number of slice/depth
1275b8e80941Smrg    UINT_32         numSamples;         ///< Number of samples
1276b8e80941Smrg    UINT_32         numFrags;           ///< Number of fragments, leave it zero or the same as
1277b8e80941Smrg                                        ///  number of samples for normal AA; Set it to the
1278b8e80941Smrg                                        ///  number of fragments for EQAA
1279b8e80941Smrg    /// r800 and later HWL parameters
1280b8e80941Smrg    struct
1281b8e80941Smrg    {
1282b8e80941Smrg        UINT_32 resolved:   1;          ///< TRUE if the surface is for resolved fmask, only used
1283b8e80941Smrg                                        ///  by H/W clients. S/W should always set it to FALSE.
1284b8e80941Smrg        UINT_32 reserved:  31;          ///< Reserved for future use.
1285b8e80941Smrg    };
1286b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;          ///< 2D tiling parameters. Clients must give valid data
1287b8e80941Smrg    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
1288b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
1289b8e80941Smrg} ADDR_COMPUTE_FMASK_INFO_INPUT;
1290b8e80941Smrg
1291b8e80941Smrg/**
1292b8e80941Smrg****************************************************************************************************
1293b8e80941Smrg*   ADDR_COMPUTE_FMASK_INFO_OUTPUT
1294b8e80941Smrg*
1295b8e80941Smrg*   @brief
1296b8e80941Smrg*       Output structure for AddrComputeFmaskInfo
1297b8e80941Smrg****************************************************************************************************
1298b8e80941Smrg*/
1299b8e80941Smrgtypedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT
1300b8e80941Smrg{
1301b8e80941Smrg    UINT_32         size;           ///< Size of this structure in bytes
1302b8e80941Smrg
1303b8e80941Smrg    UINT_32         pitch;          ///< Pitch of fmask in pixels
1304b8e80941Smrg    UINT_32         height;         ///< Height of fmask in pixels
1305b8e80941Smrg    UINT_32         numSlices;      ///< Slices of fmask
1306b8e80941Smrg    UINT_64         fmaskBytes;     ///< Size of fmask in bytes
1307b8e80941Smrg    UINT_32         baseAlign;      ///< Base address alignment
1308b8e80941Smrg    UINT_32         pitchAlign;     ///< Pitch alignment
1309b8e80941Smrg    UINT_32         heightAlign;    ///< Height alignment
1310b8e80941Smrg    UINT_32         bpp;            ///< Bits per pixel of FMASK is: number of bit planes
1311b8e80941Smrg    UINT_32         numSamples;     ///< Number of samples, used for dump, export this since input
1312b8e80941Smrg                                    ///  may be changed in 9xx and above
1313b8e80941Smrg    /// r800 and later HWL parameters
1314b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;      ///< Tile parameters used. Fmask can have different
1315b8e80941Smrg                                    ///  bank_height from color buffer
1316b8e80941Smrg    INT_32          tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
1317b8e80941Smrg                                    ///  while the global useTileIndex is set to 1
1318b8e80941Smrg    INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1319b8e80941Smrg    UINT_64         sliceSize;      ///< Size of slice in bytes
1320b8e80941Smrg} ADDR_COMPUTE_FMASK_INFO_OUTPUT;
1321b8e80941Smrg
1322b8e80941Smrg/**
1323b8e80941Smrg****************************************************************************************************
1324b8e80941Smrg*   AddrComputeFmaskInfo
1325b8e80941Smrg*
1326b8e80941Smrg*   @brief
1327b8e80941Smrg*       Compute Fmask pitch/height/depth/alignments and size in bytes
1328b8e80941Smrg****************************************************************************************************
1329b8e80941Smrg*/
1330b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
1331b8e80941Smrg    ADDR_HANDLE                             hLib,
1332b8e80941Smrg    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pIn,
1333b8e80941Smrg    ADDR_COMPUTE_FMASK_INFO_OUTPUT*         pOut);
1334b8e80941Smrg
1335b8e80941Smrg/**
1336b8e80941Smrg****************************************************************************************************
1337b8e80941Smrg*   ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1338b8e80941Smrg*
1339b8e80941Smrg*   @brief
1340b8e80941Smrg*       Input structure for AddrComputeFmaskAddrFromCoord
1341b8e80941Smrg****************************************************************************************************
1342b8e80941Smrg*/
1343b8e80941Smrgtypedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1344b8e80941Smrg{
1345b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
1346b8e80941Smrg
1347b8e80941Smrg    UINT_32         x;                  ///< X coordinate
1348b8e80941Smrg    UINT_32         y;                  ///< Y coordinate
1349b8e80941Smrg    UINT_32         slice;              ///< Slice index
1350b8e80941Smrg    UINT_32         plane;              ///< Plane number
1351b8e80941Smrg    UINT_32         sample;             ///< Sample index (fragment index for EQAA)
1352b8e80941Smrg
1353b8e80941Smrg    UINT_32         pitch;              ///< Surface pitch, in pixels
1354b8e80941Smrg    UINT_32         height;             ///< Surface height, in pixels
1355b8e80941Smrg    UINT_32         numSamples;         ///< Number of samples
1356b8e80941Smrg    UINT_32         numFrags;           ///< Number of fragments, leave it zero or the same as
1357b8e80941Smrg                                        ///  number of samples for normal AA; Set it to the
1358b8e80941Smrg                                        ///  number of fragments for EQAA
1359b8e80941Smrg
1360b8e80941Smrg    AddrTileMode    tileMode;           ///< Tile mode
1361b8e80941Smrg    union
1362b8e80941Smrg    {
1363b8e80941Smrg        struct
1364b8e80941Smrg        {
1365b8e80941Smrg            UINT_32  bankSwizzle;       ///< Bank swizzle
1366b8e80941Smrg            UINT_32  pipeSwizzle;       ///< Pipe swizzle
1367b8e80941Smrg        };
1368b8e80941Smrg        UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
1369b8e80941Smrg    };
1370b8e80941Smrg
1371b8e80941Smrg    /// r800 and later HWL parameters
1372b8e80941Smrg    struct
1373b8e80941Smrg    {
1374b8e80941Smrg        UINT_32 resolved:   1;          ///< TRUE if this is a resolved fmask, used by H/W clients
1375b8e80941Smrg        UINT_32 ignoreSE:   1;          ///< TRUE if shader engines are ignored.
1376b8e80941Smrg        UINT_32 reserved:  30;          ///< Reserved for future use.
1377b8e80941Smrg    };
1378b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;          ///< 2D tiling parameters. Client must provide all data
1379b8e80941Smrg
1380b8e80941Smrg} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
1381b8e80941Smrg
1382b8e80941Smrg/**
1383b8e80941Smrg****************************************************************************************************
1384b8e80941Smrg*   ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1385b8e80941Smrg*
1386b8e80941Smrg*   @brief
1387b8e80941Smrg*       Output structure for AddrComputeFmaskAddrFromCoord
1388b8e80941Smrg****************************************************************************************************
1389b8e80941Smrg*/
1390b8e80941Smrgtypedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1391b8e80941Smrg{
1392b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
1393b8e80941Smrg
1394b8e80941Smrg    UINT_64 addr;           ///< Fmask address
1395b8e80941Smrg    UINT_32 bitPosition;    ///< Bit position within fmaskAddr, 0-7.
1396b8e80941Smrg} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
1397b8e80941Smrg
1398b8e80941Smrg/**
1399b8e80941Smrg****************************************************************************************************
1400b8e80941Smrg*   AddrComputeFmaskAddrFromCoord
1401b8e80941Smrg*
1402b8e80941Smrg*   @brief
1403b8e80941Smrg*       Compute Fmask address according to coordinates (x,y,slice,sample,plane)
1404b8e80941Smrg****************************************************************************************************
1405b8e80941Smrg*/
1406b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
1407b8e80941Smrg    ADDR_HANDLE                                     hLib,
1408b8e80941Smrg    const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*   pIn,
1409b8e80941Smrg    ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*        pOut);
1410b8e80941Smrg
1411b8e80941Smrg/**
1412b8e80941Smrg****************************************************************************************************
1413b8e80941Smrg*   ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1414b8e80941Smrg*
1415b8e80941Smrg*   @brief
1416b8e80941Smrg*       Input structure for AddrComputeFmaskCoordFromAddr
1417b8e80941Smrg****************************************************************************************************
1418b8e80941Smrg*/
1419b8e80941Smrgtypedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1420b8e80941Smrg{
1421b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
1422b8e80941Smrg
1423b8e80941Smrg    UINT_64         addr;               ///< Address
1424b8e80941Smrg    UINT_32         bitPosition;        ///< Bit position within addr, 0-7.
1425b8e80941Smrg
1426b8e80941Smrg    UINT_32         pitch;              ///< Pitch, in pixels
1427b8e80941Smrg    UINT_32         height;             ///< Height in pixels
1428b8e80941Smrg    UINT_32         numSamples;         ///< Number of samples
1429b8e80941Smrg    UINT_32         numFrags;           ///< Number of fragments
1430b8e80941Smrg    AddrTileMode    tileMode;           ///< Tile mode
1431b8e80941Smrg    union
1432b8e80941Smrg    {
1433b8e80941Smrg        struct
1434b8e80941Smrg        {
1435b8e80941Smrg            UINT_32  bankSwizzle;       ///< Bank swizzle
1436b8e80941Smrg            UINT_32  pipeSwizzle;       ///< Pipe swizzle
1437b8e80941Smrg        };
1438b8e80941Smrg        UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
1439b8e80941Smrg    };
1440b8e80941Smrg
1441b8e80941Smrg    /// r800 and later HWL parameters
1442b8e80941Smrg    struct
1443b8e80941Smrg    {
1444b8e80941Smrg        UINT_32 resolved:   1;          ///< TRUE if this is a resolved fmask, used by HW components
1445b8e80941Smrg        UINT_32 ignoreSE:   1;          ///< TRUE if shader engines are ignored.
1446b8e80941Smrg        UINT_32 reserved:  30;          ///< Reserved for future use.
1447b8e80941Smrg    };
1448b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;          ///< 2D tile parameters. Client must provide all data
1449b8e80941Smrg
1450b8e80941Smrg} ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT;
1451b8e80941Smrg
1452b8e80941Smrg/**
1453b8e80941Smrg****************************************************************************************************
1454b8e80941Smrg*   ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1455b8e80941Smrg*
1456b8e80941Smrg*   @brief
1457b8e80941Smrg*       Output structure for AddrComputeFmaskCoordFromAddr
1458b8e80941Smrg****************************************************************************************************
1459b8e80941Smrg*/
1460b8e80941Smrgtypedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1461b8e80941Smrg{
1462b8e80941Smrg    UINT_32 size;       ///< Size of this structure in bytes
1463b8e80941Smrg
1464b8e80941Smrg    UINT_32 x;          ///< X coordinate
1465b8e80941Smrg    UINT_32 y;          ///< Y coordinate
1466b8e80941Smrg    UINT_32 slice;      ///< Slice index
1467b8e80941Smrg    UINT_32 plane;      ///< Plane number
1468b8e80941Smrg    UINT_32 sample;     ///< Sample index (fragment index for EQAA)
1469b8e80941Smrg} ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
1470b8e80941Smrg
1471b8e80941Smrg/**
1472b8e80941Smrg****************************************************************************************************
1473b8e80941Smrg*   AddrComputeFmaskCoordFromAddr
1474b8e80941Smrg*
1475b8e80941Smrg*   @brief
1476b8e80941Smrg*       Compute FMASK coordinate from an given address
1477b8e80941Smrg****************************************************************************************************
1478b8e80941Smrg*/
1479b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
1480b8e80941Smrg    ADDR_HANDLE                                     hLib,
1481b8e80941Smrg    const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*   pIn,
1482b8e80941Smrg    ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*        pOut);
1483b8e80941Smrg
1484b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
1485b8e80941Smrg//                          Element/utility functions
1486b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
1487b8e80941Smrg
1488b8e80941Smrg/**
1489b8e80941Smrg****************************************************************************************************
1490b8e80941Smrg*   AddrGetVersion
1491b8e80941Smrg*
1492b8e80941Smrg*   @brief
1493b8e80941Smrg*       Get AddrLib version number
1494b8e80941Smrg****************************************************************************************************
1495b8e80941Smrg*/
1496b8e80941SmrgUINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib);
1497b8e80941Smrg
1498b8e80941Smrg/**
1499b8e80941Smrg****************************************************************************************************
1500b8e80941Smrg*   AddrUseTileIndex
1501b8e80941Smrg*
1502b8e80941Smrg*   @brief
1503b8e80941Smrg*       Return TRUE if tileIndex is enabled in this address library
1504b8e80941Smrg****************************************************************************************************
1505b8e80941Smrg*/
1506b8e80941SmrgBOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);
1507b8e80941Smrg
1508b8e80941Smrg/**
1509b8e80941Smrg****************************************************************************************************
1510b8e80941Smrg*   AddrUseCombinedSwizzle
1511b8e80941Smrg*
1512b8e80941Smrg*   @brief
1513b8e80941Smrg*       Return TRUE if combined swizzle is enabled in this address library
1514b8e80941Smrg****************************************************************************************************
1515b8e80941Smrg*/
1516b8e80941SmrgBOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);
1517b8e80941Smrg
1518b8e80941Smrg/**
1519b8e80941Smrg****************************************************************************************************
1520b8e80941Smrg*   ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1521b8e80941Smrg*
1522b8e80941Smrg*   @brief
1523b8e80941Smrg*       Input structure of AddrExtractBankPipeSwizzle
1524b8e80941Smrg****************************************************************************************************
1525b8e80941Smrg*/
1526b8e80941Smrgtypedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1527b8e80941Smrg{
1528b8e80941Smrg    UINT_32         size;           ///< Size of this structure in bytes
1529b8e80941Smrg
1530b8e80941Smrg    UINT_32         base256b;       ///< Base256b value
1531b8e80941Smrg
1532b8e80941Smrg    /// r800 and later HWL parameters
1533b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;      ///< 2D tile parameters. Client must provide all data
1534b8e80941Smrg
1535b8e80941Smrg    INT_32          tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
1536b8e80941Smrg                                    ///  while the global useTileIndex is set to 1
1537b8e80941Smrg    INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1538b8e80941Smrg                                    ///< README: When tileIndex is not -1, this must be valid
1539b8e80941Smrg} ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT;
1540b8e80941Smrg
1541b8e80941Smrg/**
1542b8e80941Smrg****************************************************************************************************
1543b8e80941Smrg*   ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1544b8e80941Smrg*
1545b8e80941Smrg*   @brief
1546b8e80941Smrg*       Output structure of AddrExtractBankPipeSwizzle
1547b8e80941Smrg****************************************************************************************************
1548b8e80941Smrg*/
1549b8e80941Smrgtypedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1550b8e80941Smrg{
1551b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
1552b8e80941Smrg
1553b8e80941Smrg    UINT_32 bankSwizzle;    ///< Bank swizzle
1554b8e80941Smrg    UINT_32 pipeSwizzle;    ///< Pipe swizzle
1555b8e80941Smrg} ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT;
1556b8e80941Smrg
1557b8e80941Smrg/**
1558b8e80941Smrg****************************************************************************************************
1559b8e80941Smrg*   AddrExtractBankPipeSwizzle
1560b8e80941Smrg*
1561b8e80941Smrg*   @brief
1562b8e80941Smrg*       Extract Bank and Pipe swizzle from base256b
1563b8e80941Smrg*   @return
1564b8e80941Smrg*       ADDR_OK if no error
1565b8e80941Smrg****************************************************************************************************
1566b8e80941Smrg*/
1567b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
1568b8e80941Smrg    ADDR_HANDLE                                 hLib,
1569b8e80941Smrg    const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT*  pIn,
1570b8e80941Smrg    ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT*       pOut);
1571b8e80941Smrg
1572b8e80941Smrg/**
1573b8e80941Smrg****************************************************************************************************
1574b8e80941Smrg*   ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1575b8e80941Smrg*
1576b8e80941Smrg*   @brief
1577b8e80941Smrg*       Input structure of AddrCombineBankPipeSwizzle
1578b8e80941Smrg****************************************************************************************************
1579b8e80941Smrg*/
1580b8e80941Smrgtypedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1581b8e80941Smrg{
1582b8e80941Smrg    UINT_32         size;           ///< Size of this structure in bytes
1583b8e80941Smrg
1584b8e80941Smrg    UINT_32         bankSwizzle;    ///< Bank swizzle
1585b8e80941Smrg    UINT_32         pipeSwizzle;    ///< Pipe swizzle
1586b8e80941Smrg    UINT_64         baseAddr;       ///< Base address (leave it zero for driver clients)
1587b8e80941Smrg
1588b8e80941Smrg    /// r800 and later HWL parameters
1589b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;      ///< 2D tile parameters. Client must provide all data
1590b8e80941Smrg
1591b8e80941Smrg    INT_32          tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
1592b8e80941Smrg                                    ///  while the global useTileIndex is set to 1
1593b8e80941Smrg    INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1594b8e80941Smrg                                    ///< README: When tileIndex is not -1, this must be valid
1595b8e80941Smrg} ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT;
1596b8e80941Smrg
1597b8e80941Smrg/**
1598b8e80941Smrg****************************************************************************************************
1599b8e80941Smrg*   ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1600b8e80941Smrg*
1601b8e80941Smrg*   @brief
1602b8e80941Smrg*       Output structure of AddrCombineBankPipeSwizzle
1603b8e80941Smrg****************************************************************************************************
1604b8e80941Smrg*/
1605b8e80941Smrgtypedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1606b8e80941Smrg{
1607b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
1608b8e80941Smrg
1609b8e80941Smrg    UINT_32 tileSwizzle;    ///< Combined swizzle
1610b8e80941Smrg} ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT;
1611b8e80941Smrg
1612b8e80941Smrg/**
1613b8e80941Smrg****************************************************************************************************
1614b8e80941Smrg*   AddrCombineBankPipeSwizzle
1615b8e80941Smrg*
1616b8e80941Smrg*   @brief
1617b8e80941Smrg*       Combine Bank and Pipe swizzle
1618b8e80941Smrg*   @return
1619b8e80941Smrg*       ADDR_OK if no error
1620b8e80941Smrg*   @note
1621b8e80941Smrg*       baseAddr here is full MCAddress instead of base256b
1622b8e80941Smrg****************************************************************************************************
1623b8e80941Smrg*/
1624b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
1625b8e80941Smrg    ADDR_HANDLE                                 hLib,
1626b8e80941Smrg    const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT*  pIn,
1627b8e80941Smrg    ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT*       pOut);
1628b8e80941Smrg
1629b8e80941Smrg/**
1630b8e80941Smrg****************************************************************************************************
1631b8e80941Smrg*   ADDR_COMPUTE_SLICESWIZZLE_INPUT
1632b8e80941Smrg*
1633b8e80941Smrg*   @brief
1634b8e80941Smrg*       Input structure of AddrComputeSliceSwizzle
1635b8e80941Smrg****************************************************************************************************
1636b8e80941Smrg*/
1637b8e80941Smrgtypedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
1638b8e80941Smrg{
1639b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
1640b8e80941Smrg
1641b8e80941Smrg    AddrTileMode    tileMode;           ///< Tile Mode
1642b8e80941Smrg    UINT_32         baseSwizzle;        ///< Base tile swizzle
1643b8e80941Smrg    UINT_32         slice;              ///< Slice index
1644b8e80941Smrg    UINT_64         baseAddr;           ///< Base address, driver should leave it 0 in most cases
1645b8e80941Smrg
1646b8e80941Smrg    /// r800 and later HWL parameters
1647b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;          ///< 2D tile parameters. Actually banks needed here!
1648b8e80941Smrg
1649b8e80941Smrg    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
1650b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
1651b8e80941Smrg    INT_32          macroModeIndex;     ///< Index in macro tile mode table if there is one (CI)
1652b8e80941Smrg                                        ///< README: When tileIndex is not -1, this must be valid
1653b8e80941Smrg} ADDR_COMPUTE_SLICESWIZZLE_INPUT;
1654b8e80941Smrg
1655b8e80941Smrg/**
1656b8e80941Smrg****************************************************************************************************
1657b8e80941Smrg*   ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1658b8e80941Smrg*
1659b8e80941Smrg*   @brief
1660b8e80941Smrg*       Output structure of AddrComputeSliceSwizzle
1661b8e80941Smrg****************************************************************************************************
1662b8e80941Smrg*/
1663b8e80941Smrgtypedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1664b8e80941Smrg{
1665b8e80941Smrg    UINT_32  size;           ///< Size of this structure in bytes
1666b8e80941Smrg
1667b8e80941Smrg    UINT_32  tileSwizzle;    ///< Recalculated tileSwizzle value
1668b8e80941Smrg} ADDR_COMPUTE_SLICESWIZZLE_OUTPUT;
1669b8e80941Smrg
1670b8e80941Smrg/**
1671b8e80941Smrg****************************************************************************************************
1672b8e80941Smrg*   AddrComputeSliceSwizzle
1673b8e80941Smrg*
1674b8e80941Smrg*   @brief
1675b8e80941Smrg*       Extract Bank and Pipe swizzle from base256b
1676b8e80941Smrg*   @return
1677b8e80941Smrg*       ADDR_OK if no error
1678b8e80941Smrg****************************************************************************************************
1679b8e80941Smrg*/
1680b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
1681b8e80941Smrg    ADDR_HANDLE                             hLib,
1682b8e80941Smrg    const ADDR_COMPUTE_SLICESWIZZLE_INPUT*  pIn,
1683b8e80941Smrg    ADDR_COMPUTE_SLICESWIZZLE_OUTPUT*       pOut);
1684b8e80941Smrg
1685b8e80941Smrg/**
1686b8e80941Smrg****************************************************************************************************
1687b8e80941Smrg*   AddrSwizzleGenOption
1688b8e80941Smrg*
1689b8e80941Smrg*   @brief
1690b8e80941Smrg*       Which swizzle generating options: legacy or linear
1691b8e80941Smrg****************************************************************************************************
1692b8e80941Smrg*/
1693b8e80941Smrgtypedef enum _AddrSwizzleGenOption
1694b8e80941Smrg{
1695b8e80941Smrg    ADDR_SWIZZLE_GEN_DEFAULT    = 0,    ///< As is in client driver implemention for swizzle
1696b8e80941Smrg    ADDR_SWIZZLE_GEN_LINEAR     = 1,    ///< Using a linear increment of swizzle
1697b8e80941Smrg} AddrSwizzleGenOption;
1698b8e80941Smrg
1699b8e80941Smrg/**
1700b8e80941Smrg****************************************************************************************************
1701b8e80941Smrg*   AddrSwizzleOption
1702b8e80941Smrg*
1703b8e80941Smrg*   @brief
1704b8e80941Smrg*       Controls how swizzle is generated
1705b8e80941Smrg****************************************************************************************************
1706b8e80941Smrg*/
1707b8e80941Smrgtypedef union _ADDR_SWIZZLE_OPTION
1708b8e80941Smrg{
1709b8e80941Smrg    struct
1710b8e80941Smrg    {
1711b8e80941Smrg        UINT_32 genOption       : 1;    ///< The way swizzle is generated, see AddrSwizzleGenOption
1712b8e80941Smrg        UINT_32 reduceBankBit   : 1;    ///< TRUE if we need reduce swizzle bits
1713b8e80941Smrg        UINT_32 reserved        :30;    ///< Reserved bits
1714b8e80941Smrg    };
1715b8e80941Smrg
1716b8e80941Smrg    UINT_32 value;
1717b8e80941Smrg
1718b8e80941Smrg} ADDR_SWIZZLE_OPTION;
1719b8e80941Smrg
1720b8e80941Smrg/**
1721b8e80941Smrg****************************************************************************************************
1722b8e80941Smrg*   ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1723b8e80941Smrg*
1724b8e80941Smrg*   @brief
1725b8e80941Smrg*       Input structure of AddrComputeBaseSwizzle
1726b8e80941Smrg****************************************************************************************************
1727b8e80941Smrg*/
1728b8e80941Smrgtypedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1729b8e80941Smrg{
1730b8e80941Smrg    UINT_32             size;           ///< Size of this structure in bytes
1731b8e80941Smrg
1732b8e80941Smrg    ADDR_SWIZZLE_OPTION option;         ///< Swizzle option
1733b8e80941Smrg    UINT_32             surfIndex;      ///< Index of this surface type
1734b8e80941Smrg    AddrTileMode        tileMode;       ///< Tile Mode
1735b8e80941Smrg
1736b8e80941Smrg    /// r800 and later HWL parameters
1737b8e80941Smrg    ADDR_TILEINFO*      pTileInfo;      ///< 2D tile parameters. Actually banks needed here!
1738b8e80941Smrg
1739b8e80941Smrg    INT_32              tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
1740b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
1741b8e80941Smrg    INT_32              macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1742b8e80941Smrg                                        ///< README: When tileIndex is not -1, this must be valid
1743b8e80941Smrg} ADDR_COMPUTE_BASE_SWIZZLE_INPUT;
1744b8e80941Smrg
1745b8e80941Smrg/**
1746b8e80941Smrg****************************************************************************************************
1747b8e80941Smrg*   ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1748b8e80941Smrg*
1749b8e80941Smrg*   @brief
1750b8e80941Smrg*       Output structure of AddrComputeBaseSwizzle
1751b8e80941Smrg****************************************************************************************************
1752b8e80941Smrg*/
1753b8e80941Smrgtypedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1754b8e80941Smrg{
1755b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
1756b8e80941Smrg
1757b8e80941Smrg    UINT_32 tileSwizzle;    ///< Combined swizzle
1758b8e80941Smrg} ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT;
1759b8e80941Smrg
1760b8e80941Smrg/**
1761b8e80941Smrg****************************************************************************************************
1762b8e80941Smrg*   AddrComputeBaseSwizzle
1763b8e80941Smrg*
1764b8e80941Smrg*   @brief
1765b8e80941Smrg*       Return a Combined Bank and Pipe swizzle base on surface based on surface type/index
1766b8e80941Smrg*   @return
1767b8e80941Smrg*       ADDR_OK if no error
1768b8e80941Smrg****************************************************************************************************
1769b8e80941Smrg*/
1770b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
1771b8e80941Smrg    ADDR_HANDLE                             hLib,
1772b8e80941Smrg    const ADDR_COMPUTE_BASE_SWIZZLE_INPUT*  pIn,
1773b8e80941Smrg    ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT*       pOut);
1774b8e80941Smrg
1775b8e80941Smrg/**
1776b8e80941Smrg****************************************************************************************************
1777b8e80941Smrg*   ELEM_GETEXPORTNORM_INPUT
1778b8e80941Smrg*
1779b8e80941Smrg*   @brief
1780b8e80941Smrg*       Input structure for ElemGetExportNorm
1781b8e80941Smrg*
1782b8e80941Smrg****************************************************************************************************
1783b8e80941Smrg*/
1784b8e80941Smrgtypedef struct _ELEM_GETEXPORTNORM_INPUT
1785b8e80941Smrg{
1786b8e80941Smrg    UINT_32             size;       ///< Size of this structure in bytes
1787b8e80941Smrg
1788b8e80941Smrg    AddrColorFormat     format;     ///< Color buffer format; Client should use ColorFormat
1789b8e80941Smrg    AddrSurfaceNumber   num;        ///< Surface number type; Client should use NumberType
1790b8e80941Smrg    AddrSurfaceSwap     swap;       ///< Surface swap byte swap; Client should use SurfaceSwap
1791b8e80941Smrg    UINT_32             numSamples; ///< Number of samples
1792b8e80941Smrg} ELEM_GETEXPORTNORM_INPUT;
1793b8e80941Smrg
1794b8e80941Smrg/**
1795b8e80941Smrg****************************************************************************************************
1796b8e80941Smrg*  ElemGetExportNorm
1797b8e80941Smrg*
1798b8e80941Smrg*   @brief
1799b8e80941Smrg*       Helper function to check one format can be EXPORT_NUM, which is a register
1800b8e80941Smrg*       CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600
1801b8e80941Smrg*       family
1802b8e80941Smrg*   @note
1803b8e80941Smrg*       The implementation is only for r600.
1804b8e80941Smrg*       00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two
1805b8e80941Smrg*       clocks per export)
1806b8e80941Smrg*       01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one
1807b8e80941Smrg*       clock per export)
1808b8e80941Smrg*
1809b8e80941Smrg****************************************************************************************************
1810b8e80941Smrg*/
1811b8e80941SmrgBOOL_32 ADDR_API ElemGetExportNorm(
1812b8e80941Smrg    ADDR_HANDLE                     hLib,
1813b8e80941Smrg    const ELEM_GETEXPORTNORM_INPUT* pIn);
1814b8e80941Smrg
1815b8e80941Smrg/**
1816b8e80941Smrg****************************************************************************************************
1817b8e80941Smrg*   ELEM_FLT32TODEPTHPIXEL_INPUT
1818b8e80941Smrg*
1819b8e80941Smrg*   @brief
1820b8e80941Smrg*       Input structure for addrFlt32ToDepthPixel
1821b8e80941Smrg*
1822b8e80941Smrg****************************************************************************************************
1823b8e80941Smrg*/
1824b8e80941Smrgtypedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT
1825b8e80941Smrg{
1826b8e80941Smrg    UINT_32         size;           ///< Size of this structure in bytes
1827b8e80941Smrg
1828b8e80941Smrg    AddrDepthFormat format;         ///< Depth buffer format
1829b8e80941Smrg    ADDR_FLT_32     comps[2];       ///< Component values (Z/stencil)
1830b8e80941Smrg} ELEM_FLT32TODEPTHPIXEL_INPUT;
1831b8e80941Smrg
1832b8e80941Smrg/**
1833b8e80941Smrg****************************************************************************************************
1834b8e80941Smrg*   ELEM_FLT32TODEPTHPIXEL_INPUT
1835b8e80941Smrg*
1836b8e80941Smrg*   @brief
1837b8e80941Smrg*       Output structure for ElemFlt32ToDepthPixel
1838b8e80941Smrg*
1839b8e80941Smrg****************************************************************************************************
1840b8e80941Smrg*/
1841b8e80941Smrgtypedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT
1842b8e80941Smrg{
1843b8e80941Smrg    UINT_32 size;           ///< Size of this structure in bytes
1844b8e80941Smrg
1845b8e80941Smrg    UINT_8* pPixel;         ///< Real depth value. Same data type as depth buffer.
1846b8e80941Smrg                            ///  Client must provide enough storage for this type.
1847b8e80941Smrg    UINT_32 depthBase;      ///< Tile base in bits for depth bits
1848b8e80941Smrg    UINT_32 stencilBase;    ///< Tile base in bits for stencil bits
1849b8e80941Smrg    UINT_32 depthBits;      ///< Bits for depth
1850b8e80941Smrg    UINT_32 stencilBits;    ///< Bits for stencil
1851b8e80941Smrg} ELEM_FLT32TODEPTHPIXEL_OUTPUT;
1852b8e80941Smrg
1853b8e80941Smrg/**
1854b8e80941Smrg****************************************************************************************************
1855b8e80941Smrg*   ElemFlt32ToDepthPixel
1856b8e80941Smrg*
1857b8e80941Smrg*   @brief
1858b8e80941Smrg*       Convert a FLT_32 value to a depth/stencil pixel value
1859b8e80941Smrg*
1860b8e80941Smrg*   @return
1861b8e80941Smrg*       Return code
1862b8e80941Smrg*
1863b8e80941Smrg****************************************************************************************************
1864b8e80941Smrg*/
1865b8e80941SmrgADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
1866b8e80941Smrg    ADDR_HANDLE                         hLib,
1867b8e80941Smrg    const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
1868b8e80941Smrg    ELEM_FLT32TODEPTHPIXEL_OUTPUT*      pOut);
1869b8e80941Smrg
1870b8e80941Smrg/**
1871b8e80941Smrg****************************************************************************************************
1872b8e80941Smrg*   ELEM_FLT32TOCOLORPIXEL_INPUT
1873b8e80941Smrg*
1874b8e80941Smrg*   @brief
1875b8e80941Smrg*       Input structure for addrFlt32ToColorPixel
1876b8e80941Smrg*
1877b8e80941Smrg****************************************************************************************************
1878b8e80941Smrg*/
1879b8e80941Smrgtypedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT
1880b8e80941Smrg{
1881b8e80941Smrg    UINT_32            size;           ///< Size of this structure in bytes
1882b8e80941Smrg
1883b8e80941Smrg    AddrColorFormat    format;         ///< Color buffer format
1884b8e80941Smrg    AddrSurfaceNumber  surfNum;        ///< Surface number
1885b8e80941Smrg    AddrSurfaceSwap    surfSwap;       ///< Surface swap
1886b8e80941Smrg    ADDR_FLT_32        comps[4];       ///< Component values (r/g/b/a)
1887b8e80941Smrg} ELEM_FLT32TOCOLORPIXEL_INPUT;
1888b8e80941Smrg
1889b8e80941Smrg/**
1890b8e80941Smrg****************************************************************************************************
1891b8e80941Smrg*   ELEM_FLT32TOCOLORPIXEL_INPUT
1892b8e80941Smrg*
1893b8e80941Smrg*   @brief
1894b8e80941Smrg*       Output structure for ElemFlt32ToColorPixel
1895b8e80941Smrg*
1896b8e80941Smrg****************************************************************************************************
1897b8e80941Smrg*/
1898b8e80941Smrgtypedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT
1899b8e80941Smrg{
1900b8e80941Smrg    UINT_32 size;       ///< Size of this structure in bytes
1901b8e80941Smrg
1902b8e80941Smrg    UINT_8* pPixel;     ///< Real color value. Same data type as color buffer.
1903b8e80941Smrg                        ///  Client must provide enough storage for this type.
1904b8e80941Smrg} ELEM_FLT32TOCOLORPIXEL_OUTPUT;
1905b8e80941Smrg
1906b8e80941Smrg/**
1907b8e80941Smrg****************************************************************************************************
1908b8e80941Smrg*   ElemFlt32ToColorPixel
1909b8e80941Smrg*
1910b8e80941Smrg*   @brief
1911b8e80941Smrg*       Convert a FLT_32 value to a red/green/blue/alpha pixel value
1912b8e80941Smrg*
1913b8e80941Smrg*   @return
1914b8e80941Smrg*       Return code
1915b8e80941Smrg*
1916b8e80941Smrg****************************************************************************************************
1917b8e80941Smrg*/
1918b8e80941SmrgADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
1919b8e80941Smrg    ADDR_HANDLE                         hLib,
1920b8e80941Smrg    const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
1921b8e80941Smrg    ELEM_FLT32TOCOLORPIXEL_OUTPUT*      pOut);
1922b8e80941Smrg
1923b8e80941Smrg/**
1924b8e80941Smrg****************************************************************************************************
1925b8e80941Smrg*   ElemSize
1926b8e80941Smrg*
1927b8e80941Smrg*   @brief
1928b8e80941Smrg*       Get bits-per-element for specified format
1929b8e80941Smrg*
1930b8e80941Smrg*   @return
1931b8e80941Smrg*       Bits-per-element of specified format
1932b8e80941Smrg*
1933b8e80941Smrg****************************************************************************************************
1934b8e80941Smrg*/
1935b8e80941SmrgUINT_32 ADDR_API ElemSize(
1936b8e80941Smrg    ADDR_HANDLE hLib,
1937b8e80941Smrg    AddrFormat  format);
1938b8e80941Smrg
1939b8e80941Smrg/**
1940b8e80941Smrg****************************************************************************************************
1941b8e80941Smrg*   ADDR_CONVERT_TILEINFOTOHW_INPUT
1942b8e80941Smrg*
1943b8e80941Smrg*   @brief
1944b8e80941Smrg*       Input structure for AddrConvertTileInfoToHW
1945b8e80941Smrg*   @note
1946b8e80941Smrg*       When reverse is TRUE, indices are igonred
1947b8e80941Smrg****************************************************************************************************
1948b8e80941Smrg*/
1949b8e80941Smrgtypedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT
1950b8e80941Smrg{
1951b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
1952b8e80941Smrg    BOOL_32         reverse;            ///< Convert control flag.
1953b8e80941Smrg                                        ///  FALSE: convert from real value to HW value;
1954b8e80941Smrg                                        ///  TRUE: convert from HW value to real value.
1955b8e80941Smrg
1956b8e80941Smrg    /// r800 and later HWL parameters
1957b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;          ///< Tile parameters with real value
1958b8e80941Smrg
1959b8e80941Smrg    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
1960b8e80941Smrg                                        ///  while the global useTileIndex is set to 1
1961b8e80941Smrg    INT_32          macroModeIndex;     ///< Index in macro tile mode table if there is one (CI)
1962b8e80941Smrg                                        ///< README: When tileIndex is not -1, this must be valid
1963b8e80941Smrg    UINT_32         bpp;                ///< Bits per pixel
1964b8e80941Smrg} ADDR_CONVERT_TILEINFOTOHW_INPUT;
1965b8e80941Smrg
1966b8e80941Smrg/**
1967b8e80941Smrg****************************************************************************************************
1968b8e80941Smrg*   ADDR_CONVERT_TILEINFOTOHW_OUTPUT
1969b8e80941Smrg*
1970b8e80941Smrg*   @brief
1971b8e80941Smrg*       Output structure for AddrConvertTileInfoToHW
1972b8e80941Smrg****************************************************************************************************
1973b8e80941Smrg*/
1974b8e80941Smrgtypedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT
1975b8e80941Smrg{
1976b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
1977b8e80941Smrg
1978b8e80941Smrg    /// r800 and later HWL parameters
1979b8e80941Smrg    ADDR_TILEINFO*      pTileInfo;          ///< Tile parameters with hardware register value
1980b8e80941Smrg
1981b8e80941Smrg} ADDR_CONVERT_TILEINFOTOHW_OUTPUT;
1982b8e80941Smrg
1983b8e80941Smrg/**
1984b8e80941Smrg****************************************************************************************************
1985b8e80941Smrg*   AddrConvertTileInfoToHW
1986b8e80941Smrg*
1987b8e80941Smrg*   @brief
1988b8e80941Smrg*       Convert tile info from real value to hardware register value
1989b8e80941Smrg****************************************************************************************************
1990b8e80941Smrg*/
1991b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
1992b8e80941Smrg    ADDR_HANDLE                             hLib,
1993b8e80941Smrg    const ADDR_CONVERT_TILEINFOTOHW_INPUT*  pIn,
1994b8e80941Smrg    ADDR_CONVERT_TILEINFOTOHW_OUTPUT*       pOut);
1995b8e80941Smrg
1996b8e80941Smrg/**
1997b8e80941Smrg****************************************************************************************************
1998b8e80941Smrg*   ADDR_CONVERT_TILEINDEX_INPUT
1999b8e80941Smrg*
2000b8e80941Smrg*   @brief
2001b8e80941Smrg*       Input structure for AddrConvertTileIndex
2002b8e80941Smrg****************************************************************************************************
2003b8e80941Smrg*/
2004b8e80941Smrgtypedef struct _ADDR_CONVERT_TILEINDEX_INPUT
2005b8e80941Smrg{
2006b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
2007b8e80941Smrg
2008b8e80941Smrg    INT_32          tileIndex;          ///< Tile index
2009b8e80941Smrg    INT_32          macroModeIndex;     ///< Index in macro tile mode table if there is one (CI)
2010b8e80941Smrg    UINT_32         bpp;                ///< Bits per pixel
2011b8e80941Smrg    BOOL_32         tileInfoHw;         ///< Set to TRUE if client wants HW enum, otherwise actual
2012b8e80941Smrg} ADDR_CONVERT_TILEINDEX_INPUT;
2013b8e80941Smrg
2014b8e80941Smrg/**
2015b8e80941Smrg****************************************************************************************************
2016b8e80941Smrg*   ADDR_CONVERT_TILEINDEX_OUTPUT
2017b8e80941Smrg*
2018b8e80941Smrg*   @brief
2019b8e80941Smrg*       Output structure for AddrConvertTileIndex
2020b8e80941Smrg****************************************************************************************************
2021b8e80941Smrg*/
2022b8e80941Smrgtypedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT
2023b8e80941Smrg{
2024b8e80941Smrg    UINT_32             size;           ///< Size of this structure in bytes
2025b8e80941Smrg
2026b8e80941Smrg    AddrTileMode        tileMode;       ///< Tile mode
2027b8e80941Smrg    AddrTileType        tileType;       ///< Tile type
2028b8e80941Smrg    ADDR_TILEINFO*      pTileInfo;      ///< Tile info
2029b8e80941Smrg
2030b8e80941Smrg} ADDR_CONVERT_TILEINDEX_OUTPUT;
2031b8e80941Smrg
2032b8e80941Smrg/**
2033b8e80941Smrg****************************************************************************************************
2034b8e80941Smrg*   AddrConvertTileIndex
2035b8e80941Smrg*
2036b8e80941Smrg*   @brief
2037b8e80941Smrg*       Convert tile index to tile mode/type/info
2038b8e80941Smrg****************************************************************************************************
2039b8e80941Smrg*/
2040b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex(
2041b8e80941Smrg    ADDR_HANDLE                         hLib,
2042b8e80941Smrg    const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
2043b8e80941Smrg    ADDR_CONVERT_TILEINDEX_OUTPUT*      pOut);
2044b8e80941Smrg
2045b8e80941Smrg/**
2046b8e80941Smrg****************************************************************************************************
2047b8e80941Smrg*   ADDR_GET_MACROMODEINDEX_INPUT
2048b8e80941Smrg*
2049b8e80941Smrg*   @brief
2050b8e80941Smrg*       Input structure for AddrGetMacroModeIndex
2051b8e80941Smrg****************************************************************************************************
2052b8e80941Smrg*/
2053b8e80941Smrgtypedef struct _ADDR_GET_MACROMODEINDEX_INPUT
2054b8e80941Smrg{
2055b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
2056b8e80941Smrg    ADDR_SURFACE_FLAGS  flags;              ///< Surface flag
2057b8e80941Smrg    INT_32              tileIndex;          ///< Tile index
2058b8e80941Smrg    UINT_32             bpp;                ///< Bits per pixel
2059b8e80941Smrg    UINT_32             numFrags;           ///< Number of color fragments
2060b8e80941Smrg} ADDR_GET_MACROMODEINDEX_INPUT;
2061b8e80941Smrg
2062b8e80941Smrg/**
2063b8e80941Smrg****************************************************************************************************
2064b8e80941Smrg*   ADDR_GET_MACROMODEINDEX_OUTPUT
2065b8e80941Smrg*
2066b8e80941Smrg*   @brief
2067b8e80941Smrg*       Output structure for AddrGetMacroModeIndex
2068b8e80941Smrg****************************************************************************************************
2069b8e80941Smrg*/
2070b8e80941Smrgtypedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT
2071b8e80941Smrg{
2072b8e80941Smrg    UINT_32             size;            ///< Size of this structure in bytes
2073b8e80941Smrg    INT_32              macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
2074b8e80941Smrg} ADDR_GET_MACROMODEINDEX_OUTPUT;
2075b8e80941Smrg
2076b8e80941Smrg/**
2077b8e80941Smrg****************************************************************************************************
2078b8e80941Smrg*   AddrGetMacroModeIndex
2079b8e80941Smrg*
2080b8e80941Smrg*   @brief
2081b8e80941Smrg*       Get macro mode index based on input parameters
2082b8e80941Smrg****************************************************************************************************
2083b8e80941Smrg*/
2084b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex(
2085b8e80941Smrg    ADDR_HANDLE                          hLib,
2086b8e80941Smrg    const ADDR_GET_MACROMODEINDEX_INPUT* pIn,
2087b8e80941Smrg    ADDR_GET_MACROMODEINDEX_OUTPUT*      pOut);
2088b8e80941Smrg
2089b8e80941Smrg/**
2090b8e80941Smrg****************************************************************************************************
2091b8e80941Smrg*   ADDR_CONVERT_TILEINDEX1_INPUT
2092b8e80941Smrg*
2093b8e80941Smrg*   @brief
2094b8e80941Smrg*       Input structure for AddrConvertTileIndex1 (without macro mode index)
2095b8e80941Smrg****************************************************************************************************
2096b8e80941Smrg*/
2097b8e80941Smrgtypedef struct _ADDR_CONVERT_TILEINDEX1_INPUT
2098b8e80941Smrg{
2099b8e80941Smrg    UINT_32         size;               ///< Size of this structure in bytes
2100b8e80941Smrg
2101b8e80941Smrg    INT_32          tileIndex;          ///< Tile index
2102b8e80941Smrg    UINT_32         bpp;                ///< Bits per pixel
2103b8e80941Smrg    UINT_32         numSamples;         ///< Number of samples
2104b8e80941Smrg    BOOL_32         tileInfoHw;         ///< Set to TRUE if client wants HW enum, otherwise actual
2105b8e80941Smrg} ADDR_CONVERT_TILEINDEX1_INPUT;
2106b8e80941Smrg
2107b8e80941Smrg/**
2108b8e80941Smrg****************************************************************************************************
2109b8e80941Smrg*   AddrConvertTileIndex1
2110b8e80941Smrg*
2111b8e80941Smrg*   @brief
2112b8e80941Smrg*       Convert tile index to tile mode/type/info
2113b8e80941Smrg****************************************************************************************************
2114b8e80941Smrg*/
2115b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
2116b8e80941Smrg    ADDR_HANDLE                             hLib,
2117b8e80941Smrg    const ADDR_CONVERT_TILEINDEX1_INPUT*    pIn,
2118b8e80941Smrg    ADDR_CONVERT_TILEINDEX_OUTPUT*          pOut);
2119b8e80941Smrg
2120b8e80941Smrg/**
2121b8e80941Smrg****************************************************************************************************
2122b8e80941Smrg*   ADDR_GET_TILEINDEX_INPUT
2123b8e80941Smrg*
2124b8e80941Smrg*   @brief
2125b8e80941Smrg*       Input structure for AddrGetTileIndex
2126b8e80941Smrg****************************************************************************************************
2127b8e80941Smrg*/
2128b8e80941Smrgtypedef struct _ADDR_GET_TILEINDEX_INPUT
2129b8e80941Smrg{
2130b8e80941Smrg    UINT_32         size;           ///< Size of this structure in bytes
2131b8e80941Smrg
2132b8e80941Smrg    AddrTileMode    tileMode;       ///< Tile mode
2133b8e80941Smrg    AddrTileType    tileType;       ///< Tile-type: disp/non-disp/...
2134b8e80941Smrg    ADDR_TILEINFO*  pTileInfo;      ///< Pointer to tile-info structure, can be NULL for linear/1D
2135b8e80941Smrg} ADDR_GET_TILEINDEX_INPUT;
2136b8e80941Smrg
2137b8e80941Smrg/**
2138b8e80941Smrg****************************************************************************************************
2139b8e80941Smrg*   ADDR_GET_TILEINDEX_OUTPUT
2140b8e80941Smrg*
2141b8e80941Smrg*   @brief
2142b8e80941Smrg*       Output structure for AddrGetTileIndex
2143b8e80941Smrg****************************************************************************************************
2144b8e80941Smrg*/
2145b8e80941Smrgtypedef struct _ADDR_GET_TILEINDEX_OUTPUT
2146b8e80941Smrg{
2147b8e80941Smrg    UINT_32         size;           ///< Size of this structure in bytes
2148b8e80941Smrg
2149b8e80941Smrg    INT_32          index;          ///< index in table
2150b8e80941Smrg} ADDR_GET_TILEINDEX_OUTPUT;
2151b8e80941Smrg
2152b8e80941Smrg/**
2153b8e80941Smrg****************************************************************************************************
2154b8e80941Smrg*   AddrGetTileIndex
2155b8e80941Smrg*
2156b8e80941Smrg*   @brief
2157b8e80941Smrg*       Get the tiling mode index in table
2158b8e80941Smrg****************************************************************************************************
2159b8e80941Smrg*/
2160b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
2161b8e80941Smrg    ADDR_HANDLE                     hLib,
2162b8e80941Smrg    const ADDR_GET_TILEINDEX_INPUT* pIn,
2163b8e80941Smrg    ADDR_GET_TILEINDEX_OUTPUT*      pOut);
2164b8e80941Smrg
2165b8e80941Smrg/**
2166b8e80941Smrg****************************************************************************************************
2167b8e80941Smrg*   ADDR_PRT_INFO_INPUT
2168b8e80941Smrg*
2169b8e80941Smrg*   @brief
2170b8e80941Smrg*       Input structure for AddrComputePrtInfo
2171b8e80941Smrg****************************************************************************************************
2172b8e80941Smrg*/
2173b8e80941Smrgtypedef struct _ADDR_PRT_INFO_INPUT
2174b8e80941Smrg{
2175b8e80941Smrg    AddrFormat          format;        ///< Surface format
2176b8e80941Smrg    UINT_32             baseMipWidth;  ///< Base mipmap width
2177b8e80941Smrg    UINT_32             baseMipHeight; ///< Base mipmap height
2178b8e80941Smrg    UINT_32             baseMipDepth;  ///< Base mipmap depth
2179b8e80941Smrg    UINT_32             numFrags;      ///< Number of fragments,
2180b8e80941Smrg} ADDR_PRT_INFO_INPUT;
2181b8e80941Smrg
2182b8e80941Smrg/**
2183b8e80941Smrg****************************************************************************************************
2184b8e80941Smrg*   ADDR_PRT_INFO_OUTPUT
2185b8e80941Smrg*
2186b8e80941Smrg*   @brief
2187b8e80941Smrg*       Input structure for AddrComputePrtInfo
2188b8e80941Smrg****************************************************************************************************
2189b8e80941Smrg*/
2190b8e80941Smrgtypedef struct _ADDR_PRT_INFO_OUTPUT
2191b8e80941Smrg{
2192b8e80941Smrg    UINT_32             prtTileWidth;
2193b8e80941Smrg    UINT_32             prtTileHeight;
2194b8e80941Smrg} ADDR_PRT_INFO_OUTPUT;
2195b8e80941Smrg
2196b8e80941Smrg/**
2197b8e80941Smrg****************************************************************************************************
2198b8e80941Smrg*   AddrComputePrtInfo
2199b8e80941Smrg*
2200b8e80941Smrg*   @brief
2201b8e80941Smrg*       Compute prt surface related information
2202b8e80941Smrg****************************************************************************************************
2203b8e80941Smrg*/
2204b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
2205b8e80941Smrg    ADDR_HANDLE                 hLib,
2206b8e80941Smrg    const ADDR_PRT_INFO_INPUT*  pIn,
2207b8e80941Smrg    ADDR_PRT_INFO_OUTPUT*       pOut);
2208b8e80941Smrg
2209b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
2210b8e80941Smrg//                                     DCC key functions
2211b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
2212b8e80941Smrg
2213b8e80941Smrg/**
2214b8e80941Smrg****************************************************************************************************
2215b8e80941Smrg*   _ADDR_COMPUTE_DCCINFO_INPUT
2216b8e80941Smrg*
2217b8e80941Smrg*   @brief
2218b8e80941Smrg*       Input structure of AddrComputeDccInfo
2219b8e80941Smrg****************************************************************************************************
2220b8e80941Smrg*/
2221b8e80941Smrgtypedef struct _ADDR_COMPUTE_DCCINFO_INPUT
2222b8e80941Smrg{
2223b8e80941Smrg    UINT_32             size;            ///< Size of this structure in bytes
2224b8e80941Smrg    UINT_32             bpp;             ///< BitPP of color surface
2225b8e80941Smrg    UINT_32             numSamples;      ///< Sample number of color surface
2226b8e80941Smrg    UINT_64             colorSurfSize;   ///< Size of color surface to which dcc key is bound
2227b8e80941Smrg    AddrTileMode        tileMode;        ///< Tile mode of color surface
2228b8e80941Smrg    ADDR_TILEINFO       tileInfo;        ///< Tile info of color surface
2229b8e80941Smrg    UINT_32             tileSwizzle;     ///< Tile swizzle
2230b8e80941Smrg    INT_32              tileIndex;       ///< Tile index of color surface,
2231b8e80941Smrg                                         ///< MUST be -1 if you don't want to use it
2232b8e80941Smrg                                         ///< while the global useTileIndex is set to 1
2233b8e80941Smrg    INT_32              macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
2234b8e80941Smrg                                         ///< README: When tileIndex is not -1, this must be valid
2235b8e80941Smrg} ADDR_COMPUTE_DCCINFO_INPUT;
2236b8e80941Smrg
2237b8e80941Smrg/**
2238b8e80941Smrg****************************************************************************************************
2239b8e80941Smrg*   ADDR_COMPUTE_DCCINFO_OUTPUT
2240b8e80941Smrg*
2241b8e80941Smrg*   @brief
2242b8e80941Smrg*       Output structure of AddrComputeDccInfo
2243b8e80941Smrg****************************************************************************************************
2244b8e80941Smrg*/
2245b8e80941Smrgtypedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
2246b8e80941Smrg{
2247b8e80941Smrg    UINT_32 size;                 ///< Size of this structure in bytes
2248b8e80941Smrg    UINT_32 dccRamBaseAlign;      ///< Base alignment of dcc key
2249b8e80941Smrg    UINT_64 dccRamSize;           ///< Size of dcc key
2250b8e80941Smrg    UINT_64 dccFastClearSize;     ///< Size of dcc key portion that can be fast cleared
2251b8e80941Smrg    BOOL_32 subLvlCompressible;   ///< Whether sub resource is compressiable
2252b8e80941Smrg    BOOL_32 dccRamSizeAligned;    ///< Whether the dcc key size is aligned
2253b8e80941Smrg} ADDR_COMPUTE_DCCINFO_OUTPUT;
2254b8e80941Smrg
2255b8e80941Smrg/**
2256b8e80941Smrg****************************************************************************************************
2257b8e80941Smrg*   AddrComputeDccInfo
2258b8e80941Smrg*
2259b8e80941Smrg*   @brief
2260b8e80941Smrg*       Compute DCC key size, base alignment
2261b8e80941Smrg*       info
2262b8e80941Smrg****************************************************************************************************
2263b8e80941Smrg*/
2264b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
2265b8e80941Smrg    ADDR_HANDLE                             hLib,
2266b8e80941Smrg    const ADDR_COMPUTE_DCCINFO_INPUT*       pIn,
2267b8e80941Smrg    ADDR_COMPUTE_DCCINFO_OUTPUT*            pOut);
2268b8e80941Smrg
2269b8e80941Smrg/**
2270b8e80941Smrg****************************************************************************************************
2271b8e80941Smrg*   ADDR_GET_MAX_ALINGMENTS_OUTPUT
2272b8e80941Smrg*
2273b8e80941Smrg*   @brief
2274b8e80941Smrg*       Output structure of AddrGetMaxAlignments
2275b8e80941Smrg****************************************************************************************************
2276b8e80941Smrg*/
2277b8e80941Smrgtypedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
2278b8e80941Smrg{
2279b8e80941Smrg    UINT_32 size;                   ///< Size of this structure in bytes
2280b8e80941Smrg    UINT_32 baseAlign;              ///< Maximum base alignment in bytes
2281b8e80941Smrg} ADDR_GET_MAX_ALINGMENTS_OUTPUT;
2282b8e80941Smrg
2283b8e80941Smrg/**
2284b8e80941Smrg****************************************************************************************************
2285b8e80941Smrg*   AddrGetMaxAlignments
2286b8e80941Smrg*
2287b8e80941Smrg*   @brief
2288b8e80941Smrg*       Gets maximnum alignments
2289b8e80941Smrg****************************************************************************************************
2290b8e80941Smrg*/
2291b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
2292b8e80941Smrg    ADDR_HANDLE                     hLib,
2293b8e80941Smrg    ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
2294b8e80941Smrg
2295b8e80941Smrg/**
2296b8e80941Smrg****************************************************************************************************
2297b8e80941Smrg*   AddrGetMaxMetaAlignments
2298b8e80941Smrg*
2299b8e80941Smrg*   @brief
2300b8e80941Smrg*       Gets maximnum alignments for metadata
2301b8e80941Smrg****************************************************************************************************
2302b8e80941Smrg*/
2303b8e80941SmrgADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
2304b8e80941Smrg    ADDR_HANDLE                     hLib,
2305b8e80941Smrg    ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
2306b8e80941Smrg
2307b8e80941Smrg/**
2308b8e80941Smrg****************************************************************************************************
2309b8e80941Smrg*                                Address library interface version 2
2310b8e80941Smrg*                                    available from Gfx9 hardware
2311b8e80941Smrg****************************************************************************************************
2312b8e80941Smrg*     Addr2ComputeSurfaceInfo()
2313b8e80941Smrg*     Addr2ComputeSurfaceAddrFromCoord()
2314b8e80941Smrg*     Addr2ComputeSurfaceCoordFromAddr()
2315b8e80941Smrg
2316b8e80941Smrg*     Addr2ComputeHtileInfo()
2317b8e80941Smrg*     Addr2ComputeHtileAddrFromCoord()
2318b8e80941Smrg*     Addr2ComputeHtileCoordFromAddr()
2319b8e80941Smrg*
2320b8e80941Smrg*     Addr2ComputeCmaskInfo()
2321b8e80941Smrg*     Addr2ComputeCmaskAddrFromCoord()
2322b8e80941Smrg*     Addr2ComputeCmaskCoordFromAddr()
2323b8e80941Smrg*
2324b8e80941Smrg*     Addr2ComputeFmaskInfo()
2325b8e80941Smrg*     Addr2ComputeFmaskAddrFromCoord()
2326b8e80941Smrg*     Addr2ComputeFmaskCoordFromAddr()
2327b8e80941Smrg*
2328b8e80941Smrg*     Addr2ComputeDccInfo()
2329b8e80941Smrg*
2330b8e80941Smrg**/
2331b8e80941Smrg
2332b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
2333b8e80941Smrg//                                    Surface functions for Gfx9
2334b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
2335b8e80941Smrg
2336b8e80941Smrg/**
2337b8e80941Smrg****************************************************************************************************
2338b8e80941Smrg*   ADDR2_SURFACE_FLAGS
2339b8e80941Smrg*
2340b8e80941Smrg*   @brief
2341b8e80941Smrg*       Surface flags
2342b8e80941Smrg****************************************************************************************************
2343b8e80941Smrg*/
2344b8e80941Smrgtypedef union _ADDR2_SURFACE_FLAGS
2345b8e80941Smrg{
2346b8e80941Smrg    struct
2347b8e80941Smrg    {
2348b8e80941Smrg        UINT_32 color             :  1; ///< This resource is a color buffer, can be used with RTV
2349b8e80941Smrg        UINT_32 depth             :  1; ///< Thie resource is a depth buffer, can be used with DSV
2350b8e80941Smrg        UINT_32 stencil           :  1; ///< Thie resource is a stencil buffer, can be used with DSV
2351b8e80941Smrg        UINT_32 fmask             :  1; ///< This is an fmask surface
2352b8e80941Smrg        UINT_32 overlay           :  1; ///< This is an overlay surface
2353b8e80941Smrg        UINT_32 display           :  1; ///< This resource is displable, can be used with DRV
2354b8e80941Smrg        UINT_32 prt               :  1; ///< This is a partially resident texture
2355b8e80941Smrg        UINT_32 qbStereo          :  1; ///< This is a quad buffer stereo surface
2356b8e80941Smrg        UINT_32 interleaved       :  1; ///< Special flag for interleaved YUV surface padding
2357b8e80941Smrg        UINT_32 texture           :  1; ///< This resource can be used with SRV
2358b8e80941Smrg        UINT_32 unordered         :  1; ///< This resource can be used with UAV
2359b8e80941Smrg        UINT_32 rotated           :  1; ///< This resource is rotated and displable
2360b8e80941Smrg        UINT_32 needEquation      :  1; ///< This resource needs equation to be generated if possible
2361b8e80941Smrg        UINT_32 opt4space         :  1; ///< This resource should be optimized for space
2362b8e80941Smrg        UINT_32 minimizeAlign     :  1; ///< This resource should use minimum alignment
2363b8e80941Smrg        UINT_32 noMetadata        :  1; ///< This resource has no metadata
2364b8e80941Smrg        UINT_32 metaRbUnaligned   :  1; ///< This resource has rb unaligned metadata
2365b8e80941Smrg        UINT_32 metaPipeUnaligned :  1; ///< This resource has pipe unaligned metadata
2366b8e80941Smrg        UINT_32 view3dAs2dArray   :  1; ///< This resource is a 3D resource viewed as 2D array
2367b8e80941Smrg        UINT_32 reserved          : 13; ///< Reserved bits
2368b8e80941Smrg    };
2369b8e80941Smrg
2370b8e80941Smrg    UINT_32 value;
2371b8e80941Smrg} ADDR2_SURFACE_FLAGS;
2372b8e80941Smrg
2373b8e80941Smrg/**
2374b8e80941Smrg****************************************************************************************************
2375b8e80941Smrg*   ADDR2_COMPUTE_SURFACE_INFO_INPUT
2376b8e80941Smrg*
2377b8e80941Smrg*   @brief
2378b8e80941Smrg*       Input structure for Addr2ComputeSurfaceInfo
2379b8e80941Smrg****************************************************************************************************
2380b8e80941Smrg*/
2381b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT
2382b8e80941Smrg{
2383b8e80941Smrg    UINT_32               size;              ///< Size of this structure in bytes
2384b8e80941Smrg
2385b8e80941Smrg    ADDR2_SURFACE_FLAGS   flags;             ///< Surface flags
2386b8e80941Smrg    AddrSwizzleMode       swizzleMode;       ///< Swizzle Mode for Gfx9
2387b8e80941Smrg    AddrResourceType      resourceType;      ///< Surface type
2388b8e80941Smrg    AddrFormat            format;            ///< Surface format
2389b8e80941Smrg    UINT_32               bpp;               ///< bits per pixel
2390b8e80941Smrg    UINT_32               width;             ///< Width (of mip0), in pixels
2391b8e80941Smrg    UINT_32               height;            ///< Height (of mip0), in pixels
2392b8e80941Smrg    UINT_32               numSlices;         ///< Number surface slice/depth (of mip0),
2393b8e80941Smrg    UINT_32               numMipLevels;      ///< Total mipmap levels.
2394b8e80941Smrg    UINT_32               numSamples;        ///< Number of samples
2395b8e80941Smrg    UINT_32               numFrags;          ///< Number of fragments, leave it zero or the same as
2396b8e80941Smrg                                             ///  number of samples for normal AA; Set it to the
2397b8e80941Smrg                                             ///  number of fragments for EQAA
2398b8e80941Smrg    UINT_32               pitchInElement;    ///< Pitch in elements (blocks for compressed formats)
2399b8e80941Smrg    UINT_32               sliceAlign;        ///< Required slice size in bytes
2400b8e80941Smrg} ADDR2_COMPUTE_SURFACE_INFO_INPUT;
2401b8e80941Smrg
2402b8e80941Smrg/**
2403b8e80941Smrg****************************************************************************************************
2404b8e80941Smrg*   ADDR2_MIP_INFO
2405b8e80941Smrg*
2406b8e80941Smrg*   @brief
2407b8e80941Smrg*       Structure that contains information for mip level
2408b8e80941Smrg*
2409b8e80941Smrg****************************************************************************************************
2410b8e80941Smrg*/
2411b8e80941Smrgtypedef struct _ADDR2_MIP_INFO
2412b8e80941Smrg{
2413b8e80941Smrg    UINT_32             pitch;              ///< Pitch in elements
2414b8e80941Smrg    UINT_32             height;             ///< Padded height in elements
2415b8e80941Smrg    UINT_32             depth;              ///< Padded depth
2416b8e80941Smrg    UINT_32             pixelPitch;         ///< Pitch in pixels
2417b8e80941Smrg    UINT_32             pixelHeight;        ///< Padded height in pixels
2418b8e80941Smrg    UINT_32             equationIndex;      ///< Equation index in the equation table
2419b8e80941Smrg    UINT_64             offset;             ///< Offset in bytes from mip base, should only be used
2420b8e80941Smrg                                            ///< to setup vam surface descriptor, can't be used
2421b8e80941Smrg                                            ///< to setup swizzle pattern
2422b8e80941Smrg    UINT_64             macroBlockOffset;   ///< macro block offset in bytes from mip base
2423b8e80941Smrg    UINT_32             mipTailOffset;      ///< mip tail offset in bytes
2424b8e80941Smrg    UINT_32             mipTailCoordX;      ///< mip tail coord x
2425b8e80941Smrg    UINT_32             mipTailCoordY;      ///< mip tail coord y
2426b8e80941Smrg    UINT_32             mipTailCoordZ;      ///< mip tail coord z
2427b8e80941Smrg} ADDR2_MIP_INFO;
2428b8e80941Smrg
2429b8e80941Smrg/**
2430b8e80941Smrg****************************************************************************************************
2431b8e80941Smrg*   ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2432b8e80941Smrg*
2433b8e80941Smrg*   @brief
2434b8e80941Smrg*       Output structure for Addr2ComputeSurfInfo
2435b8e80941Smrg*   @note
2436b8e80941Smrg        Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
2437b8e80941Smrg        Pixel: Original pixel
2438b8e80941Smrg****************************************************************************************************
2439b8e80941Smrg*/
2440b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2441b8e80941Smrg{
2442b8e80941Smrg    UINT_32             size;                 ///< Size of this structure in bytes
2443b8e80941Smrg
2444b8e80941Smrg    UINT_32             pitch;                ///< Pitch in elements (blocks for compressed formats)
2445b8e80941Smrg    UINT_32             height;               ///< Padded height (of mip0) in elements
2446b8e80941Smrg    UINT_32             numSlices;            ///< Padded depth for 3d resource
2447b8e80941Smrg                                              ///< or padded number of slices for 2d array resource
2448b8e80941Smrg    UINT_32             mipChainPitch;        ///< Pitch (of total mip chain) in elements
2449b8e80941Smrg    UINT_32             mipChainHeight;       ///< Padded height (of total mip chain) in elements
2450b8e80941Smrg    UINT_32             mipChainSlice;        ///< Padded depth (of total mip chain)
2451b8e80941Smrg    UINT_64             sliceSize;            ///< Slice (total mip chain) size in bytes
2452b8e80941Smrg    UINT_64             surfSize;             ///< Surface (total mip chain) size in bytes
2453b8e80941Smrg    UINT_32             baseAlign;            ///< Base address alignment
2454b8e80941Smrg    UINT_32             bpp;                  ///< Bits per elements
2455b8e80941Smrg                                              ///  (e.g. blocks for BCn, 1/3 for 96bit)
2456b8e80941Smrg    UINT_32             pixelMipChainPitch;   ///< Mip chain pitch in original pixels
2457b8e80941Smrg    UINT_32             pixelMipChainHeight;  ///< Mip chain height in original pixels
2458b8e80941Smrg    UINT_32             pixelPitch;           ///< Pitch in original pixels
2459b8e80941Smrg    UINT_32             pixelHeight;          ///< Height in original pixels
2460b8e80941Smrg    UINT_32             pixelBits;            ///< Original bits per pixel, passed from input
2461b8e80941Smrg
2462b8e80941Smrg    UINT_32             blockWidth;           ///< Width in element inside one block
2463b8e80941Smrg    UINT_32             blockHeight;          ///< Height in element inside one block
2464b8e80941Smrg    UINT_32             blockSlices;          ///< Slice number inside one block
2465b8e80941Smrg                                              ///< Prt tile is one block, its width/height/slice
2466b8e80941Smrg                                              ///< equals to blcok width/height/slice
2467b8e80941Smrg
2468b8e80941Smrg    BOOL_32             epitchIsHeight;       ///< Whether to use height to program epitch register
2469b8e80941Smrg    /// Stereo info
2470b8e80941Smrg    ADDR_QBSTEREOINFO*  pStereoInfo;          ///< Stereo info, needed if qbStereo flag is TRUE
2471b8e80941Smrg    /// Mip info
2472b8e80941Smrg    ADDR2_MIP_INFO*     pMipInfo;             ///< Pointer to mip information array
2473b8e80941Smrg                                              ///  if it is not NULL, the array is assumed to
2474b8e80941Smrg                                              ///  contain numMipLevels entries
2475b8e80941Smrg
2476b8e80941Smrg    UINT_32             equationIndex;        ///< Equation index in the equation table of mip0
2477b8e80941Smrg    BOOL_32             mipChainInTail;       ///< If whole mipchain falls into mip tail block
2478b8e80941Smrg    UINT_32             firstMipIdInTail;     ///< The id of first mip in tail, if there is no mip
2479b8e80941Smrg                                              ///  in tail, it will be set to number of mip levels
2480b8e80941Smrg} ADDR2_COMPUTE_SURFACE_INFO_OUTPUT;
2481b8e80941Smrg
2482b8e80941Smrg/**
2483b8e80941Smrg****************************************************************************************************
2484b8e80941Smrg*   Addr2ComputeSurfaceInfo
2485b8e80941Smrg*
2486b8e80941Smrg*   @brief
2487b8e80941Smrg*       Compute surface width/height/slices/alignments and suitable tiling mode
2488b8e80941Smrg****************************************************************************************************
2489b8e80941Smrg*/
2490b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
2491b8e80941Smrg    ADDR_HANDLE                                hLib,
2492b8e80941Smrg    const ADDR2_COMPUTE_SURFACE_INFO_INPUT*    pIn,
2493b8e80941Smrg    ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*         pOut);
2494b8e80941Smrg
2495b8e80941Smrg/**
2496b8e80941Smrg****************************************************************************************************
2497b8e80941Smrg*   ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2498b8e80941Smrg*
2499b8e80941Smrg*   @brief
2500b8e80941Smrg*       Input structure for Addr2ComputeSurfaceAddrFromCoord
2501b8e80941Smrg****************************************************************************************************
2502b8e80941Smrg*/
2503b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2504b8e80941Smrg{
2505b8e80941Smrg    UINT_32             size;            ///< Size of this structure in bytes
2506b8e80941Smrg
2507b8e80941Smrg    UINT_32             x;               ///< X coordinate
2508b8e80941Smrg    UINT_32             y;               ///< Y coordinate
2509b8e80941Smrg    UINT_32             slice;           ///< Slice index
2510b8e80941Smrg    UINT_32             sample;          ///< Sample index, use fragment index for EQAA
2511b8e80941Smrg    UINT_32             mipId;           ///< the mip ID in mip chain
2512b8e80941Smrg
2513b8e80941Smrg    AddrSwizzleMode     swizzleMode;     ///< Swizzle mode for Gfx9
2514b8e80941Smrg    ADDR2_SURFACE_FLAGS flags;           ///< Surface flags
2515b8e80941Smrg    AddrResourceType    resourceType;    ///< Surface type
2516b8e80941Smrg    UINT_32             bpp;             ///< Bits per pixel
2517b8e80941Smrg    UINT_32             unalignedWidth;  ///< Surface original width (of mip0)
2518b8e80941Smrg    UINT_32             unalignedHeight; ///< Surface original height (of mip0)
2519b8e80941Smrg    UINT_32             numSlices;       ///< Surface original slices (of mip0)
2520b8e80941Smrg    UINT_32             numMipLevels;    ///< Total mipmap levels
2521b8e80941Smrg    UINT_32             numSamples;      ///< Number of samples
2522b8e80941Smrg    UINT_32             numFrags;        ///< Number of fragments, leave it zero or the same as
2523b8e80941Smrg                                         ///  number of samples for normal AA; Set it to the
2524b8e80941Smrg                                         ///  number of fragments for EQAA
2525b8e80941Smrg
2526b8e80941Smrg    UINT_32             pipeBankXor;     ///< Combined swizzle used to do bank/pipe rotation
2527b8e80941Smrg    UINT_32             pitchInElement;  ///< Pitch in elements (blocks for compressed formats)
2528b8e80941Smrg} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
2529b8e80941Smrg
2530b8e80941Smrg/**
2531b8e80941Smrg****************************************************************************************************
2532b8e80941Smrg*   ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2533b8e80941Smrg*
2534b8e80941Smrg*   @brief
2535b8e80941Smrg*       Output structure for Addr2ComputeSurfaceAddrFromCoord
2536b8e80941Smrg****************************************************************************************************
2537b8e80941Smrg*/
2538b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2539b8e80941Smrg{
2540b8e80941Smrg    UINT_32    size;             ///< Size of this structure in bytes
2541b8e80941Smrg
2542b8e80941Smrg    UINT_64    addr;             ///< Byte address
2543b8e80941Smrg    UINT_32    bitPosition;      ///< Bit position within surfaceAddr, 0-7.
2544b8e80941Smrg                                 ///  For surface bpp < 8, e.g. FMT_1.
2545b8e80941Smrg    UINT_32    prtBlockIndex;    ///< Index of a PRT tile (64K block)
2546b8e80941Smrg} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
2547b8e80941Smrg
2548b8e80941Smrg/**
2549b8e80941Smrg****************************************************************************************************
2550b8e80941Smrg*   Addr2ComputeSurfaceAddrFromCoord
2551b8e80941Smrg*
2552b8e80941Smrg*   @brief
2553b8e80941Smrg*       Compute surface address from a given coordinate.
2554b8e80941Smrg****************************************************************************************************
2555b8e80941Smrg*/
2556b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
2557b8e80941Smrg    ADDR_HANDLE                                         hLib,
2558b8e80941Smrg    const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT*    pIn,
2559b8e80941Smrg    ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*         pOut);
2560b8e80941Smrg
2561b8e80941Smrg/**
2562b8e80941Smrg****************************************************************************************************
2563b8e80941Smrg*   ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2564b8e80941Smrg*
2565b8e80941Smrg*   @brief
2566b8e80941Smrg*       Input structure for Addr2ComputeSurfaceCoordFromAddr
2567b8e80941Smrg****************************************************************************************************
2568b8e80941Smrg*/
2569b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2570b8e80941Smrg{
2571b8e80941Smrg    UINT_32             size;            ///< Size of this structure in bytes
2572b8e80941Smrg
2573b8e80941Smrg    UINT_64             addr;            ///< Address in bytes
2574b8e80941Smrg    UINT_32             bitPosition;     ///< Bit position in addr. 0-7. for surface bpp < 8,
2575b8e80941Smrg                                         ///  e.g. FMT_1;
2576b8e80941Smrg
2577b8e80941Smrg    AddrSwizzleMode     swizzleMode;     ///< Swizzle mode for Gfx9
2578b8e80941Smrg    ADDR2_SURFACE_FLAGS flags;           ///< Surface flags
2579b8e80941Smrg    AddrResourceType    resourceType;    ///< Surface type
2580b8e80941Smrg    UINT_32             bpp;             ///< Bits per pixel
2581b8e80941Smrg    UINT_32             unalignedWidth;  ///< Surface original width (of mip0)
2582b8e80941Smrg    UINT_32             unalignedHeight; ///< Surface original height (of mip0)
2583b8e80941Smrg    UINT_32             numSlices;       ///< Surface original slices (of mip0)
2584b8e80941Smrg    UINT_32             numMipLevels;    ///< Total mipmap levels.
2585b8e80941Smrg    UINT_32             numSamples;      ///< Number of samples
2586b8e80941Smrg    UINT_32             numFrags;        ///< Number of fragments, leave it zero or the same as
2587b8e80941Smrg                                         ///  number of samples for normal AA; Set it to the
2588b8e80941Smrg                                         ///  number of fragments for EQAA
2589b8e80941Smrg
2590b8e80941Smrg    UINT_32             pipeBankXor;     ///< Combined swizzle used to do bank/pipe rotation
2591b8e80941Smrg    UINT_32             pitchInElement;  ///< Pitch in elements (blocks for compressed formats)
2592b8e80941Smrg} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
2593b8e80941Smrg
2594b8e80941Smrg/**
2595b8e80941Smrg****************************************************************************************************
2596b8e80941Smrg*   ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2597b8e80941Smrg*
2598b8e80941Smrg*   @brief
2599b8e80941Smrg*       Output structure for Addr2ComputeSurfaceCoordFromAddr
2600b8e80941Smrg****************************************************************************************************
2601b8e80941Smrg*/
2602b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2603b8e80941Smrg{
2604b8e80941Smrg    UINT_32    size;       ///< Size of this structure in bytes
2605b8e80941Smrg
2606b8e80941Smrg    UINT_32    x;          ///< X coordinate
2607b8e80941Smrg    UINT_32    y;          ///< Y coordinate
2608b8e80941Smrg    UINT_32    slice;      ///< Index of slices
2609b8e80941Smrg    UINT_32    sample;     ///< Index of samples, means fragment index for EQAA
2610b8e80941Smrg    UINT_32    mipId;      ///< mipmap level id
2611b8e80941Smrg} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
2612b8e80941Smrg
2613b8e80941Smrg/**
2614b8e80941Smrg****************************************************************************************************
2615b8e80941Smrg*   Addr2ComputeSurfaceCoordFromAddr
2616b8e80941Smrg*
2617b8e80941Smrg*   @brief
2618b8e80941Smrg*       Compute coordinate from a given surface address
2619b8e80941Smrg****************************************************************************************************
2620b8e80941Smrg*/
2621b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
2622b8e80941Smrg    ADDR_HANDLE                                         hLib,
2623b8e80941Smrg    const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT*    pIn,
2624b8e80941Smrg    ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*         pOut);
2625b8e80941Smrg
2626b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
2627b8e80941Smrg//                                   HTile functions for Gfx9
2628b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
2629b8e80941Smrg
2630b8e80941Smrg/**
2631b8e80941Smrg****************************************************************************************************
2632b8e80941Smrg*   ADDR2_META_FLAGS
2633b8e80941Smrg*
2634b8e80941Smrg*   @brief
2635b8e80941Smrg*       Metadata flags
2636b8e80941Smrg****************************************************************************************************
2637b8e80941Smrg*/
2638b8e80941Smrgtypedef union _ADDR2_META_FLAGS
2639b8e80941Smrg{
2640b8e80941Smrg    struct
2641b8e80941Smrg    {
2642b8e80941Smrg        UINT_32 pipeAligned :  1;    ///< if Metadata being pipe aligned
2643b8e80941Smrg        UINT_32 rbAligned   :  1;    ///< if Metadata being RB aligned
2644b8e80941Smrg        UINT_32 linear      :  1;    ///< if Metadata linear, GFX9 does not suppord this!
2645b8e80941Smrg        UINT_32 reserved    : 29;    ///< Reserved bits
2646b8e80941Smrg    };
2647b8e80941Smrg
2648b8e80941Smrg    UINT_32 value;
2649b8e80941Smrg} ADDR2_META_FLAGS;
2650b8e80941Smrg
2651b8e80941Smrg/**
2652b8e80941Smrg****************************************************************************************************
2653b8e80941Smrg*   ADDR2_META_MIP_INFO
2654b8e80941Smrg*
2655b8e80941Smrg*   @brief
2656b8e80941Smrg*       Structure to store per mip metadata information
2657b8e80941Smrg****************************************************************************************************
2658b8e80941Smrg*/
2659b8e80941Smrgtypedef struct _ADDR2_META_MIP_INFO
2660b8e80941Smrg{
2661b8e80941Smrg    BOOL_32    inMiptail;
2662b8e80941Smrg    union
2663b8e80941Smrg    {
2664b8e80941Smrg        struct
2665b8e80941Smrg        {
2666b8e80941Smrg            UINT_32    startX;
2667b8e80941Smrg            UINT_32    startY;
2668b8e80941Smrg            UINT_32    startZ;
2669b8e80941Smrg            UINT_32    width;
2670b8e80941Smrg            UINT_32    height;
2671b8e80941Smrg            UINT_32    depth;
2672b8e80941Smrg        };
2673b8e80941Smrg
2674b8e80941Smrg        struct
2675b8e80941Smrg        {
2676b8e80941Smrg            UINT_32    offset;      ///< Metadata offset within one slice,
2677b8e80941Smrg                                    ///  the thickness of a slice is meta block depth.
2678b8e80941Smrg            UINT_32    sliceSize;   ///< Metadata size within one slice,
2679b8e80941Smrg                                    ///  the thickness of a slice is meta block depth.
2680b8e80941Smrg        };
2681b8e80941Smrg    };
2682b8e80941Smrg} ADDR2_META_MIP_INFO;
2683b8e80941Smrg
2684b8e80941Smrg/**
2685b8e80941Smrg****************************************************************************************************
2686b8e80941Smrg*   ADDR2_COMPUTE_HTILE_INFO_INPUT
2687b8e80941Smrg*
2688b8e80941Smrg*   @brief
2689b8e80941Smrg*       Input structure of Addr2ComputeHtileInfo
2690b8e80941Smrg****************************************************************************************************
2691b8e80941Smrg*/
2692b8e80941Smrgtypedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
2693b8e80941Smrg{
2694b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
2695b8e80941Smrg
2696b8e80941Smrg    ADDR2_META_FLAGS    hTileFlags;         ///< HTILE flags
2697b8e80941Smrg    ADDR2_SURFACE_FLAGS depthFlags;         ///< Depth surface flags
2698b8e80941Smrg    AddrSwizzleMode     swizzleMode;        ///< Depth surface swizzle mode
2699b8e80941Smrg    UINT_32             unalignedWidth;     ///< Depth surface original width (of mip0)
2700b8e80941Smrg    UINT_32             unalignedHeight;    ///< Depth surface original height (of mip0)
2701b8e80941Smrg    UINT_32             numSlices;          ///< Number of slices of depth surface (of mip0)
2702b8e80941Smrg    UINT_32             numMipLevels;       ///< Total mipmap levels of color surface
2703b8e80941Smrg    UINT_32             firstMipIdInTail;   ///  Id of the first mip in tail,
2704b8e80941Smrg                                            ///  if no mip is in tail, it should be set to
2705b8e80941Smrg                                            ///  number of mip levels
2706b8e80941Smrg} ADDR2_COMPUTE_HTILE_INFO_INPUT;
2707b8e80941Smrg
2708b8e80941Smrg/**
2709b8e80941Smrg****************************************************************************************************
2710b8e80941Smrg*   ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2711b8e80941Smrg*
2712b8e80941Smrg*   @brief
2713b8e80941Smrg*       Output structure of Addr2ComputeHtileInfo
2714b8e80941Smrg****************************************************************************************************
2715b8e80941Smrg*/
2716b8e80941Smrgtypedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2717b8e80941Smrg{
2718b8e80941Smrg    UINT_32    size;                ///< Size of this structure in bytes
2719b8e80941Smrg
2720b8e80941Smrg    UINT_32    pitch;               ///< Pitch in pixels of depth buffer represented in this
2721b8e80941Smrg                                    ///  HTile buffer. This might be larger than original depth
2722b8e80941Smrg                                    ///  buffer pitch when called with an unaligned pitch.
2723b8e80941Smrg    UINT_32    height;              ///< Height in pixels, as above
2724b8e80941Smrg    UINT_32    baseAlign;           ///< Base alignment
2725b8e80941Smrg    UINT_32    sliceSize;           ///< Slice size, in bytes.
2726b8e80941Smrg    UINT_32    htileBytes;          ///< Size of HTILE buffer, in bytes
2727b8e80941Smrg    UINT_32    metaBlkWidth;        ///< Meta block width
2728b8e80941Smrg    UINT_32    metaBlkHeight;       ///< Meta block height
2729b8e80941Smrg    UINT_32    metaBlkNumPerSlice;  ///< Number of metablock within one slice
2730b8e80941Smrg
2731b8e80941Smrg    ADDR2_META_MIP_INFO* pMipInfo;  ///< HTILE mip information
2732b8e80941Smrg} ADDR2_COMPUTE_HTILE_INFO_OUTPUT;
2733b8e80941Smrg
2734b8e80941Smrg/**
2735b8e80941Smrg****************************************************************************************************
2736b8e80941Smrg*   Addr2ComputeHtileInfo
2737b8e80941Smrg*
2738b8e80941Smrg*   @brief
2739b8e80941Smrg*       Compute Htile pitch, height, base alignment and size in bytes
2740b8e80941Smrg****************************************************************************************************
2741b8e80941Smrg*/
2742b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
2743b8e80941Smrg    ADDR_HANDLE                              hLib,
2744b8e80941Smrg    const ADDR2_COMPUTE_HTILE_INFO_INPUT*    pIn,
2745b8e80941Smrg    ADDR2_COMPUTE_HTILE_INFO_OUTPUT*         pOut);
2746b8e80941Smrg
2747b8e80941Smrg/**
2748b8e80941Smrg****************************************************************************************************
2749b8e80941Smrg*   ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2750b8e80941Smrg*
2751b8e80941Smrg*   @brief
2752b8e80941Smrg*       Input structure for Addr2ComputeHtileAddrFromCoord
2753b8e80941Smrg****************************************************************************************************
2754b8e80941Smrg*/
2755b8e80941Smrgtypedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2756b8e80941Smrg{
2757b8e80941Smrg    UINT_32             size;                ///< Size of this structure in bytes
2758b8e80941Smrg
2759b8e80941Smrg    UINT_32             x;                   ///< X coordinate
2760b8e80941Smrg    UINT_32             y;                   ///< Y coordinate
2761b8e80941Smrg    UINT_32             slice;               ///< Index of slices
2762b8e80941Smrg    UINT_32             mipId;               ///< mipmap level id
2763b8e80941Smrg
2764b8e80941Smrg    ADDR2_META_FLAGS    hTileFlags;          ///< HTILE flags
2765b8e80941Smrg    ADDR2_SURFACE_FLAGS depthflags;          ///< Depth surface flags
2766b8e80941Smrg    AddrSwizzleMode     swizzleMode;         ///< Depth surface swizzle mode
2767b8e80941Smrg    UINT_32             bpp;                 ///< Depth surface bits per pixel
2768b8e80941Smrg    UINT_32             unalignedWidth;      ///< Depth surface original width (of mip0)
2769b8e80941Smrg    UINT_32             unalignedHeight;     ///< Depth surface original height (of mip0)
2770b8e80941Smrg    UINT_32             numSlices;           ///< Depth surface original depth (of mip0)
2771b8e80941Smrg    UINT_32             numMipLevels;        ///< Depth surface total mipmap levels
2772b8e80941Smrg    UINT_32             numSamples;          ///< Depth surface number of samples
2773b8e80941Smrg    UINT_32             pipeXor;             ///< Pipe xor setting
2774b8e80941Smrg} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
2775b8e80941Smrg
2776b8e80941Smrg/**
2777b8e80941Smrg****************************************************************************************************
2778b8e80941Smrg*   ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2779b8e80941Smrg*
2780b8e80941Smrg*   @brief
2781b8e80941Smrg*       Output structure for Addr2ComputeHtileAddrFromCoord
2782b8e80941Smrg****************************************************************************************************
2783b8e80941Smrg*/
2784b8e80941Smrgtypedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2785b8e80941Smrg{
2786b8e80941Smrg    UINT_32    size;    ///< Size of this structure in bytes
2787b8e80941Smrg
2788b8e80941Smrg    UINT_64    addr;    ///< Address in bytes
2789b8e80941Smrg} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
2790b8e80941Smrg
2791b8e80941Smrg/**
2792b8e80941Smrg****************************************************************************************************
2793b8e80941Smrg*   Addr2ComputeHtileAddrFromCoord
2794b8e80941Smrg*
2795b8e80941Smrg*   @brief
2796b8e80941Smrg*       Compute Htile address according to coordinates (of depth buffer)
2797b8e80941Smrg****************************************************************************************************
2798b8e80941Smrg*/
2799b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
2800b8e80941Smrg    ADDR_HANDLE                                       hLib,
2801b8e80941Smrg    const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*    pIn,
2802b8e80941Smrg    ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*         pOut);
2803b8e80941Smrg
2804b8e80941Smrg/**
2805b8e80941Smrg****************************************************************************************************
2806b8e80941Smrg*   ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2807b8e80941Smrg*
2808b8e80941Smrg*   @brief
2809b8e80941Smrg*       Input structure for Addr2ComputeHtileCoordFromAddr
2810b8e80941Smrg****************************************************************************************************
2811b8e80941Smrg*/
2812b8e80941Smrgtypedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2813b8e80941Smrg{
2814b8e80941Smrg    UINT_32             size;                ///< Size of this structure in bytes
2815b8e80941Smrg
2816b8e80941Smrg    UINT_64             addr;                ///< Address
2817b8e80941Smrg
2818b8e80941Smrg    ADDR2_META_FLAGS    hTileFlags;          ///< HTILE flags
2819b8e80941Smrg    ADDR2_SURFACE_FLAGS depthFlags;          ///< Depth surface flags
2820b8e80941Smrg    AddrSwizzleMode     swizzleMode;         ///< Depth surface swizzle mode
2821b8e80941Smrg    UINT_32             bpp;                 ///< Depth surface bits per pixel
2822b8e80941Smrg    UINT_32             unalignedWidth;      ///< Depth surface original width (of mip0)
2823b8e80941Smrg    UINT_32             unalignedHeight;     ///< Depth surface original height (of mip0)
2824b8e80941Smrg    UINT_32             numSlices;           ///< Depth surface original depth (of mip0)
2825b8e80941Smrg    UINT_32             numMipLevels;        ///< Depth surface total mipmap levels
2826b8e80941Smrg    UINT_32             numSamples;          ///< Depth surface number of samples
2827b8e80941Smrg    UINT_32             pipeXor;             ///< Pipe xor setting
2828b8e80941Smrg} ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT;
2829b8e80941Smrg
2830b8e80941Smrg/**
2831b8e80941Smrg****************************************************************************************************
2832b8e80941Smrg*   ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2833b8e80941Smrg*
2834b8e80941Smrg*   @brief
2835b8e80941Smrg*       Output structure for Addr2ComputeHtileCoordFromAddr
2836b8e80941Smrg****************************************************************************************************
2837b8e80941Smrg*/
2838b8e80941Smrgtypedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2839b8e80941Smrg{
2840b8e80941Smrg    UINT_32    size;        ///< Size of this structure in bytes
2841b8e80941Smrg
2842b8e80941Smrg    UINT_32    x;           ///< X coordinate
2843b8e80941Smrg    UINT_32    y;           ///< Y coordinate
2844b8e80941Smrg    UINT_32    slice;       ///< Index of slices
2845b8e80941Smrg    UINT_32    mipId;       ///< mipmap level id
2846b8e80941Smrg} ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
2847b8e80941Smrg
2848b8e80941Smrg/**
2849b8e80941Smrg****************************************************************************************************
2850b8e80941Smrg*   Addr2ComputeHtileCoordFromAddr
2851b8e80941Smrg*
2852b8e80941Smrg*   @brief
2853b8e80941Smrg*       Compute coordinates within depth buffer (1st pixel of a micro tile) according to
2854b8e80941Smrg*       Htile address
2855b8e80941Smrg****************************************************************************************************
2856b8e80941Smrg*/
2857b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
2858b8e80941Smrg    ADDR_HANDLE                                       hLib,
2859b8e80941Smrg    const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT*    pIn,
2860b8e80941Smrg    ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*         pOut);
2861b8e80941Smrg
2862b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
2863b8e80941Smrg//                                     C-mask functions for Gfx9
2864b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
2865b8e80941Smrg
2866b8e80941Smrg/**
2867b8e80941Smrg****************************************************************************************************
2868b8e80941Smrg*   ADDR2_COMPUTE_CMASK_INFO_INPUT
2869b8e80941Smrg*
2870b8e80941Smrg*   @brief
2871b8e80941Smrg*       Input structure of Addr2ComputeCmaskInfo
2872b8e80941Smrg****************************************************************************************************
2873b8e80941Smrg*/
2874b8e80941Smrgtypedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT
2875b8e80941Smrg{
2876b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
2877b8e80941Smrg
2878b8e80941Smrg    ADDR2_META_FLAGS    cMaskFlags;         ///< CMASK flags
2879b8e80941Smrg    ADDR2_SURFACE_FLAGS colorFlags;         ///< Color surface flags
2880b8e80941Smrg    AddrResourceType    resourceType;       ///< Color surface type
2881b8e80941Smrg    AddrSwizzleMode     swizzleMode;        ///< FMask surface swizzle mode
2882b8e80941Smrg    UINT_32             unalignedWidth;     ///< Color surface original width
2883b8e80941Smrg    UINT_32             unalignedHeight;    ///< Color surface original height
2884b8e80941Smrg    UINT_32             numSlices;          ///< Number of slices of color buffer
2885b8e80941Smrg} ADDR2_COMPUTE_CMASK_INFO_INPUT;
2886b8e80941Smrg
2887b8e80941Smrg/**
2888b8e80941Smrg****************************************************************************************************
2889b8e80941Smrg*   ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2890b8e80941Smrg*
2891b8e80941Smrg*   @brief
2892b8e80941Smrg*       Output structure of Addr2ComputeCmaskInfo
2893b8e80941Smrg****************************************************************************************************
2894b8e80941Smrg*/
2895b8e80941Smrgtypedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2896b8e80941Smrg{
2897b8e80941Smrg    UINT_32    size;          ///< Size of this structure in bytes
2898b8e80941Smrg
2899b8e80941Smrg    UINT_32    pitch;         ///< Pitch in pixels of color buffer which
2900b8e80941Smrg                              ///  this Cmask matches. The size might be larger than
2901b8e80941Smrg                              ///  original color buffer pitch when called with
2902b8e80941Smrg                              ///  an unaligned pitch.
2903b8e80941Smrg    UINT_32    height;        ///< Height in pixels, as above
2904b8e80941Smrg    UINT_32    baseAlign;     ///< Base alignment
2905b8e80941Smrg    UINT_32    sliceSize;     ///< Slice size, in bytes.
2906b8e80941Smrg    UINT_32    cmaskBytes;    ///< Size in bytes of CMask buffer
2907b8e80941Smrg    UINT_32    metaBlkWidth;  ///< Meta block width
2908b8e80941Smrg    UINT_32    metaBlkHeight; ///< Meta block height
2909b8e80941Smrg
2910b8e80941Smrg    UINT_32    metaBlkNumPerSlice; ///< Number of metablock within one slice
2911b8e80941Smrg} ADDR2_COMPUTE_CMASK_INFO_OUTPUT;
2912b8e80941Smrg
2913b8e80941Smrg/**
2914b8e80941Smrg****************************************************************************************************
2915b8e80941Smrg*   Addr2ComputeCmaskInfo
2916b8e80941Smrg*
2917b8e80941Smrg*   @brief
2918b8e80941Smrg*       Compute Cmask pitch, height, base alignment and size in bytes from color buffer
2919b8e80941Smrg*       info
2920b8e80941Smrg****************************************************************************************************
2921b8e80941Smrg*/
2922b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
2923b8e80941Smrg    ADDR_HANDLE                              hLib,
2924b8e80941Smrg    const ADDR2_COMPUTE_CMASK_INFO_INPUT*    pIn,
2925b8e80941Smrg    ADDR2_COMPUTE_CMASK_INFO_OUTPUT*         pOut);
2926b8e80941Smrg
2927b8e80941Smrg/**
2928b8e80941Smrg****************************************************************************************************
2929b8e80941Smrg*   ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
2930b8e80941Smrg*
2931b8e80941Smrg*   @brief
2932b8e80941Smrg*       Input structure for Addr2ComputeCmaskAddrFromCoord
2933b8e80941Smrg*
2934b8e80941Smrg****************************************************************************************************
2935b8e80941Smrg*/
2936b8e80941Smrgtypedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
2937b8e80941Smrg{
2938b8e80941Smrg    UINT_32             size;                ///< Size of this structure in bytes
2939b8e80941Smrg
2940b8e80941Smrg    UINT_32             x;                   ///< X coordinate
2941b8e80941Smrg    UINT_32             y;                   ///< Y coordinate
2942b8e80941Smrg    UINT_32             slice;               ///< Index of slices
2943b8e80941Smrg
2944b8e80941Smrg    ADDR2_META_FLAGS    cMaskFlags;          ///< CMASK flags
2945b8e80941Smrg    ADDR2_SURFACE_FLAGS colorFlags;          ///< Color surface flags
2946b8e80941Smrg    AddrResourceType    resourceType;        ///< Color surface type
2947b8e80941Smrg    AddrSwizzleMode     swizzleMode;         ///< FMask surface swizzle mode
2948b8e80941Smrg
2949b8e80941Smrg    UINT_32             unalignedWidth;      ///< Color surface original width (of mip0)
2950b8e80941Smrg    UINT_32             unalignedHeight;     ///< Color surface original height (of mip0)
2951b8e80941Smrg    UINT_32             numSlices;           ///< Color surface original slices (of mip0)
2952b8e80941Smrg
2953b8e80941Smrg    UINT_32             numSamples;          ///< Color surfae sample number
2954b8e80941Smrg    UINT_32             numFrags;            ///< Color surface fragment number
2955b8e80941Smrg
2956b8e80941Smrg    UINT_32             pipeXor;             ///< pipe Xor setting
2957b8e80941Smrg} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
2958b8e80941Smrg
2959b8e80941Smrg/**
2960b8e80941Smrg****************************************************************************************************
2961b8e80941Smrg*   ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
2962b8e80941Smrg*
2963b8e80941Smrg*   @brief
2964b8e80941Smrg*       Output structure for Addr2ComputeCmaskAddrFromCoord
2965b8e80941Smrg****************************************************************************************************
2966b8e80941Smrg*/
2967b8e80941Smrgtypedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
2968b8e80941Smrg{
2969b8e80941Smrg    UINT_32    size;           ///< Size of this structure in bytes
2970b8e80941Smrg
2971b8e80941Smrg    UINT_64    addr;           ///< CMASK address in bytes
2972b8e80941Smrg    UINT_32    bitPosition;    ///< Bit position within addr, 0 or 4
2973b8e80941Smrg} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
2974b8e80941Smrg
2975b8e80941Smrg/**
2976b8e80941Smrg****************************************************************************************************
2977b8e80941Smrg*   Addr2ComputeCmaskAddrFromCoord
2978b8e80941Smrg*
2979b8e80941Smrg*   @brief
2980b8e80941Smrg*       Compute Cmask address according to coordinates (of MSAA color buffer)
2981b8e80941Smrg****************************************************************************************************
2982b8e80941Smrg*/
2983b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
2984b8e80941Smrg    ADDR_HANDLE                                      hLib,
2985b8e80941Smrg    const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*   pIn,
2986b8e80941Smrg    ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut);
2987b8e80941Smrg
2988b8e80941Smrg/**
2989b8e80941Smrg****************************************************************************************************
2990b8e80941Smrg*   ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
2991b8e80941Smrg*
2992b8e80941Smrg*   @brief
2993b8e80941Smrg*       Input structure for Addr2ComputeCmaskCoordFromAddr
2994b8e80941Smrg****************************************************************************************************
2995b8e80941Smrg*/
2996b8e80941Smrgtypedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
2997b8e80941Smrg{
2998b8e80941Smrg    UINT_32             size;                ///< Size of this structure in bytes
2999b8e80941Smrg
3000b8e80941Smrg    UINT_64             addr;                ///< CMASK address in bytes
3001b8e80941Smrg    UINT_32             bitPosition;         ///< Bit position within addr, 0 or 4
3002b8e80941Smrg
3003b8e80941Smrg    ADDR2_META_FLAGS    cMaskFlags;          ///< CMASK flags
3004b8e80941Smrg    ADDR2_SURFACE_FLAGS colorFlags;          ///< Color surface flags
3005b8e80941Smrg    AddrResourceType    resourceType;        ///< Color surface type
3006b8e80941Smrg    AddrSwizzleMode     swizzleMode;         ///< FMask surface swizzle mode
3007b8e80941Smrg
3008b8e80941Smrg    UINT_32             unalignedWidth;      ///< Color surface original width (of mip0)
3009b8e80941Smrg    UINT_32             unalignedHeight;     ///< Color surface original height (of mip0)
3010b8e80941Smrg    UINT_32             numSlices;           ///< Color surface original slices (of mip0)
3011b8e80941Smrg    UINT_32             numMipLevels;        ///< Color surface total mipmap levels.
3012b8e80941Smrg} ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT;
3013b8e80941Smrg
3014b8e80941Smrg/**
3015b8e80941Smrg****************************************************************************************************
3016b8e80941Smrg*   ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3017b8e80941Smrg*
3018b8e80941Smrg*   @brief
3019b8e80941Smrg*       Output structure for Addr2ComputeCmaskCoordFromAddr
3020b8e80941Smrg****************************************************************************************************
3021b8e80941Smrg*/
3022b8e80941Smrgtypedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3023b8e80941Smrg{
3024b8e80941Smrg    UINT_32    size;        ///< Size of this structure in bytes
3025b8e80941Smrg
3026b8e80941Smrg    UINT_32    x;           ///< X coordinate
3027b8e80941Smrg    UINT_32    y;           ///< Y coordinate
3028b8e80941Smrg    UINT_32    slice;       ///< Index of slices
3029b8e80941Smrg    UINT_32    mipId;       ///< mipmap level id
3030b8e80941Smrg} ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
3031b8e80941Smrg
3032b8e80941Smrg/**
3033b8e80941Smrg****************************************************************************************************
3034b8e80941Smrg*   Addr2ComputeCmaskCoordFromAddr
3035b8e80941Smrg*
3036b8e80941Smrg*   @brief
3037b8e80941Smrg*       Compute coordinates within color buffer (1st pixel of a micro tile) according to
3038b8e80941Smrg*       Cmask address
3039b8e80941Smrg****************************************************************************************************
3040b8e80941Smrg*/
3041b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
3042b8e80941Smrg    ADDR_HANDLE                                       hLib,
3043b8e80941Smrg    const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT*    pIn,
3044b8e80941Smrg    ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*         pOut);
3045b8e80941Smrg
3046b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
3047b8e80941Smrg//                                     F-mask functions for Gfx9
3048b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
3049b8e80941Smrg
3050b8e80941Smrg/**
3051b8e80941Smrg****************************************************************************************************
3052b8e80941Smrg*   ADDR2_FMASK_FLAGS
3053b8e80941Smrg*
3054b8e80941Smrg*   @brief
3055b8e80941Smrg*       FMASK flags
3056b8e80941Smrg****************************************************************************************************
3057b8e80941Smrg*/
3058b8e80941Smrgtypedef union _ADDR2_FMASK_FLAGS
3059b8e80941Smrg{
3060b8e80941Smrg    struct
3061b8e80941Smrg    {
3062b8e80941Smrg        UINT_32 resolved :  1;    ///< TRUE if this is a resolved fmask, used by H/W clients
3063b8e80941Smrg                                  ///  by H/W clients. S/W should always set it to FALSE.
3064b8e80941Smrg        UINT_32 reserved : 31;    ///< Reserved for future use.
3065b8e80941Smrg    };
3066b8e80941Smrg
3067b8e80941Smrg    UINT_32 value;
3068b8e80941Smrg} ADDR2_FMASK_FLAGS;
3069b8e80941Smrg
3070b8e80941Smrg/**
3071b8e80941Smrg****************************************************************************************************
3072b8e80941Smrg*   ADDR2_COMPUTE_FMASK_INFO_INPUT
3073b8e80941Smrg*
3074b8e80941Smrg*   @brief
3075b8e80941Smrg*       Input structure for Addr2ComputeFmaskInfo
3076b8e80941Smrg****************************************************************************************************
3077b8e80941Smrg*/
3078b8e80941Smrgtypedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT
3079b8e80941Smrg{
3080b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
3081b8e80941Smrg
3082b8e80941Smrg    AddrSwizzleMode     swizzleMode;        ///< FMask surface swizzle mode
3083b8e80941Smrg    UINT_32             unalignedWidth;     ///< Color surface original width
3084b8e80941Smrg    UINT_32             unalignedHeight;    ///< Color surface original height
3085b8e80941Smrg    UINT_32             numSlices;          ///< Number of slices/depth
3086b8e80941Smrg    UINT_32             numSamples;         ///< Number of samples
3087b8e80941Smrg    UINT_32             numFrags;           ///< Number of fragments, leave it zero or the same as
3088b8e80941Smrg                                            ///  number of samples for normal AA; Set it to the
3089b8e80941Smrg                                            ///  number of fragments for EQAA
3090b8e80941Smrg    ADDR2_FMASK_FLAGS   fMaskFlags;         ///< FMASK flags
3091b8e80941Smrg} ADDR2_COMPUTE_FMASK_INFO_INPUT;
3092b8e80941Smrg
3093b8e80941Smrg/**
3094b8e80941Smrg****************************************************************************************************
3095b8e80941Smrg*   ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3096b8e80941Smrg*
3097b8e80941Smrg*   @brief
3098b8e80941Smrg*       Output structure for Addr2ComputeFmaskInfo
3099b8e80941Smrg****************************************************************************************************
3100b8e80941Smrg*/
3101b8e80941Smrgtypedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3102b8e80941Smrg{
3103b8e80941Smrg    UINT_32    size;           ///< Size of this structure in bytes
3104b8e80941Smrg
3105b8e80941Smrg    UINT_32    pitch;          ///< Pitch of fmask in pixels
3106b8e80941Smrg    UINT_32    height;         ///< Height of fmask in pixels
3107b8e80941Smrg    UINT_32    baseAlign;      ///< Base alignment
3108b8e80941Smrg    UINT_32    numSlices;      ///< Slices of fmask
3109b8e80941Smrg    UINT_32    fmaskBytes;     ///< Size of fmask in bytes
3110b8e80941Smrg    UINT_32    bpp;            ///< Bits per pixel of FMASK is: number of bit planes
3111b8e80941Smrg    UINT_32    numSamples;     ///< Number of samples
3112b8e80941Smrg    UINT_32    sliceSize;      ///< Size of slice in bytes
3113b8e80941Smrg} ADDR2_COMPUTE_FMASK_INFO_OUTPUT;
3114b8e80941Smrg
3115b8e80941Smrg/**
3116b8e80941Smrg****************************************************************************************************
3117b8e80941Smrg*   Addr2ComputeFmaskInfo
3118b8e80941Smrg*
3119b8e80941Smrg*   @brief
3120b8e80941Smrg*       Compute Fmask pitch/height/slices/alignments and size in bytes
3121b8e80941Smrg****************************************************************************************************
3122b8e80941Smrg*/
3123b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
3124b8e80941Smrg    ADDR_HANDLE                              hLib,
3125b8e80941Smrg    const ADDR2_COMPUTE_FMASK_INFO_INPUT*    pIn,
3126b8e80941Smrg    ADDR2_COMPUTE_FMASK_INFO_OUTPUT*         pOut);
3127b8e80941Smrg
3128b8e80941Smrg/**
3129b8e80941Smrg****************************************************************************************************
3130b8e80941Smrg*   ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3131b8e80941Smrg*
3132b8e80941Smrg*   @brief
3133b8e80941Smrg*       Input structure for Addr2ComputeFmaskAddrFromCoord
3134b8e80941Smrg****************************************************************************************************
3135b8e80941Smrg*/
3136b8e80941Smrgtypedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3137b8e80941Smrg{
3138b8e80941Smrg    UINT_32            size;               ///< Size of this structure in bytes
3139b8e80941Smrg
3140b8e80941Smrg    AddrSwizzleMode    swizzleMode;        ///< FMask surface swizzle mode
3141b8e80941Smrg    UINT_32            x;                  ///< X coordinate
3142b8e80941Smrg    UINT_32            y;                  ///< Y coordinate
3143b8e80941Smrg    UINT_32            slice;              ///< Slice index
3144b8e80941Smrg    UINT_32            sample;             ///< Sample index (fragment index for EQAA)
3145b8e80941Smrg    UINT_32            plane;              ///< Plane number
3146b8e80941Smrg
3147b8e80941Smrg    UINT_32            unalignedWidth;     ///< Color surface original width
3148b8e80941Smrg    UINT_32            unalignedHeight;    ///< Color surface original height
3149b8e80941Smrg    UINT_32            numSamples;         ///< Number of samples
3150b8e80941Smrg    UINT_32            numFrags;           ///< Number of fragments, leave it zero or the same as
3151b8e80941Smrg                                           ///  number of samples for normal AA; Set it to the
3152b8e80941Smrg                                           ///  number of fragments for EQAA
3153b8e80941Smrg    UINT_32            tileSwizzle;        ///< Combined swizzle used to do bank/pipe rotation
3154b8e80941Smrg
3155b8e80941Smrg    ADDR2_FMASK_FLAGS  fMaskFlags; ///< FMASK flags
3156b8e80941Smrg} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
3157b8e80941Smrg
3158b8e80941Smrg/**
3159b8e80941Smrg****************************************************************************************************
3160b8e80941Smrg*   ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3161b8e80941Smrg*
3162b8e80941Smrg*   @brief
3163b8e80941Smrg*       Output structure for Addr2ComputeFmaskAddrFromCoord
3164b8e80941Smrg****************************************************************************************************
3165b8e80941Smrg*/
3166b8e80941Smrgtypedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3167b8e80941Smrg{
3168b8e80941Smrg    UINT_32    size;           ///< Size of this structure in bytes
3169b8e80941Smrg
3170b8e80941Smrg    UINT_64    addr;           ///< Fmask address
3171b8e80941Smrg    UINT_32    bitPosition;    ///< Bit position within fmaskAddr, 0-7.
3172b8e80941Smrg} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
3173b8e80941Smrg
3174b8e80941Smrg/**
3175b8e80941Smrg****************************************************************************************************
3176b8e80941Smrg*   Addr2ComputeFmaskAddrFromCoord
3177b8e80941Smrg*
3178b8e80941Smrg*   @brief
3179b8e80941Smrg*       Compute Fmask address according to coordinates (x,y,slice,sample,plane)
3180b8e80941Smrg****************************************************************************************************
3181b8e80941Smrg*/
3182b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
3183b8e80941Smrg    ADDR_HANDLE                                       hLib,
3184b8e80941Smrg    const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*    pIn,
3185b8e80941Smrg    ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*         pOut);
3186b8e80941Smrg
3187b8e80941Smrg/**
3188b8e80941Smrg****************************************************************************************************
3189b8e80941Smrg*   ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3190b8e80941Smrg*
3191b8e80941Smrg*   @brief
3192b8e80941Smrg*       Input structure for Addr2ComputeFmaskCoordFromAddr
3193b8e80941Smrg****************************************************************************************************
3194b8e80941Smrg*/
3195b8e80941Smrgtypedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3196b8e80941Smrg{
3197b8e80941Smrg    UINT_32            size;               ///< Size of this structure in bytes
3198b8e80941Smrg
3199b8e80941Smrg    UINT_64            addr;               ///< Address
3200b8e80941Smrg    UINT_32            bitPosition;        ///< Bit position within addr, 0-7.
3201b8e80941Smrg    AddrSwizzleMode    swizzleMode;        ///< FMask surface swizzle mode
3202b8e80941Smrg
3203b8e80941Smrg    UINT_32            unalignedWidth;     ///< Color surface original width
3204b8e80941Smrg    UINT_32            unalignedHeight;    ///< Color surface original height
3205b8e80941Smrg    UINT_32            numSamples;         ///< Number of samples
3206b8e80941Smrg    UINT_32            numFrags;           ///< Number of fragments
3207b8e80941Smrg
3208b8e80941Smrg    UINT_32            tileSwizzle;        ///< Combined swizzle used to do bank/pipe rotation
3209b8e80941Smrg
3210b8e80941Smrg    ADDR2_FMASK_FLAGS  fMaskFlags; ///< FMASK flags
3211b8e80941Smrg} ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT;
3212b8e80941Smrg
3213b8e80941Smrg/**
3214b8e80941Smrg****************************************************************************************************
3215b8e80941Smrg*   ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3216b8e80941Smrg*
3217b8e80941Smrg*   @brief
3218b8e80941Smrg*       Output structure for Addr2ComputeFmaskCoordFromAddr
3219b8e80941Smrg****************************************************************************************************
3220b8e80941Smrg*/
3221b8e80941Smrgtypedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3222b8e80941Smrg{
3223b8e80941Smrg    UINT_32    size;      ///< Size of this structure in bytes
3224b8e80941Smrg
3225b8e80941Smrg    UINT_32    x;         ///< X coordinate
3226b8e80941Smrg    UINT_32    y;         ///< Y coordinate
3227b8e80941Smrg    UINT_32    slice;     ///< Slice index
3228b8e80941Smrg    UINT_32    sample;    ///< Sample index (fragment index for EQAA)
3229b8e80941Smrg    UINT_32    plane;     ///< Plane number
3230b8e80941Smrg} ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
3231b8e80941Smrg
3232b8e80941Smrg/**
3233b8e80941Smrg****************************************************************************************************
3234b8e80941Smrg*   Addr2ComputeFmaskCoordFromAddr
3235b8e80941Smrg*
3236b8e80941Smrg*   @brief
3237b8e80941Smrg*       Compute FMASK coordinate from an given address
3238b8e80941Smrg****************************************************************************************************
3239b8e80941Smrg*/
3240b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
3241b8e80941Smrg    ADDR_HANDLE                                       hLib,
3242b8e80941Smrg    const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT*    pIn,
3243b8e80941Smrg    ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*         pOut);
3244b8e80941Smrg
3245b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
3246b8e80941Smrg//                                     DCC key functions for Gfx9
3247b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
3248b8e80941Smrg
3249b8e80941Smrg/**
3250b8e80941Smrg****************************************************************************************************
3251b8e80941Smrg*   _ADDR2_COMPUTE_DCCINFO_INPUT
3252b8e80941Smrg*
3253b8e80941Smrg*   @brief
3254b8e80941Smrg*       Input structure of Addr2ComputeDccInfo
3255b8e80941Smrg****************************************************************************************************
3256b8e80941Smrg*/
3257b8e80941Smrgtypedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
3258b8e80941Smrg{
3259b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
3260b8e80941Smrg
3261b8e80941Smrg    ADDR2_META_FLAGS    dccKeyFlags;        ///< DCC key flags
3262b8e80941Smrg    ADDR2_SURFACE_FLAGS colorFlags;         ///< Color surface flags
3263b8e80941Smrg    AddrResourceType    resourceType;       ///< Color surface type
3264b8e80941Smrg    AddrSwizzleMode     swizzleMode;        ///< Color surface swizzle mode
3265b8e80941Smrg    UINT_32             bpp;                ///< bits per pixel
3266b8e80941Smrg    UINT_32             unalignedWidth;     ///< Color surface original width (of mip0)
3267b8e80941Smrg    UINT_32             unalignedHeight;    ///< Color surface original height (of mip0)
3268b8e80941Smrg    UINT_32             numSlices;          ///< Number of slices, of color surface (of mip0)
3269b8e80941Smrg    UINT_32             numFrags;           ///< Fragment number of color surface
3270b8e80941Smrg    UINT_32             numMipLevels;       ///< Total mipmap levels of color surface
3271b8e80941Smrg    UINT_32             dataSurfaceSize;    ///< The padded size of all slices and mip levels
3272b8e80941Smrg                                            ///< useful in meta linear case
3273b8e80941Smrg    UINT_32             firstMipIdInTail;   ///< The id of first mip in tail, if no mip is in tail,
3274b8e80941Smrg                                            ///  it should be number of mip levels
3275b8e80941Smrg} ADDR2_COMPUTE_DCCINFO_INPUT;
3276b8e80941Smrg
3277b8e80941Smrg/**
3278b8e80941Smrg****************************************************************************************************
3279b8e80941Smrg*   ADDR2_COMPUTE_DCCINFO_OUTPUT
3280b8e80941Smrg*
3281b8e80941Smrg*   @brief
3282b8e80941Smrg*       Output structure of Addr2ComputeDccInfo
3283b8e80941Smrg****************************************************************************************************
3284b8e80941Smrg*/
3285b8e80941Smrgtypedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
3286b8e80941Smrg{
3287b8e80941Smrg    UINT_32    size;               ///< Size of this structure in bytes
3288b8e80941Smrg
3289b8e80941Smrg    UINT_32    dccRamBaseAlign;    ///< Base alignment of dcc key
3290b8e80941Smrg    UINT_32    dccRamSize;         ///< Size of dcc key
3291b8e80941Smrg
3292b8e80941Smrg    UINT_32    pitch;              ///< DCC surface mip chain pitch
3293b8e80941Smrg    UINT_32    height;             ///< DCC surface mip chain height
3294b8e80941Smrg    UINT_32    depth;              ///< DCC surface mip chain depth
3295b8e80941Smrg
3296b8e80941Smrg    UINT_32    compressBlkWidth;   ///< DCC compress block width
3297b8e80941Smrg    UINT_32    compressBlkHeight;  ///< DCC compress block height
3298b8e80941Smrg    UINT_32    compressBlkDepth;   ///< DCC compress block depth
3299b8e80941Smrg
3300b8e80941Smrg    UINT_32    metaBlkWidth;       ///< DCC meta block width
3301b8e80941Smrg    UINT_32    metaBlkHeight;      ///< DCC meta block height
3302b8e80941Smrg    UINT_32    metaBlkDepth;       ///< DCC meta block depth
3303b8e80941Smrg
3304b8e80941Smrg    UINT_32    metaBlkNumPerSlice; ///< Number of metablock within one slice
3305b8e80941Smrg
3306b8e80941Smrg    union
3307b8e80941Smrg    {
3308b8e80941Smrg        UINT_32 fastClearSizePerSlice;  ///< Size of DCC within a slice should be fast cleared
3309b8e80941Smrg        UINT_32 dccRamSliceSize;        ///< DCC ram size per slice. For mipmap, it's
3310b8e80941Smrg                                        ///  the slize size of a mip chain, the thickness of a
3311b8e80941Smrg                                        ///  a slice is meta block depth
3312b8e80941Smrg    };
3313b8e80941Smrg
3314b8e80941Smrg    ADDR2_META_MIP_INFO* pMipInfo;      ///< DCC mip information
3315b8e80941Smrg} ADDR2_COMPUTE_DCCINFO_OUTPUT;
3316b8e80941Smrg
3317b8e80941Smrg/**
3318b8e80941Smrg****************************************************************************************************
3319b8e80941Smrg*   Addr2ComputeDccInfo
3320b8e80941Smrg*
3321b8e80941Smrg*   @brief
3322b8e80941Smrg*       Compute DCC key size, base alignment
3323b8e80941Smrg*       info
3324b8e80941Smrg****************************************************************************************************
3325b8e80941Smrg*/
3326b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
3327b8e80941Smrg    ADDR_HANDLE                           hLib,
3328b8e80941Smrg    const ADDR2_COMPUTE_DCCINFO_INPUT*    pIn,
3329b8e80941Smrg    ADDR2_COMPUTE_DCCINFO_OUTPUT*         pOut);
3330b8e80941Smrg
3331b8e80941Smrg/**
3332b8e80941Smrg****************************************************************************************************
3333b8e80941Smrg*   ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3334b8e80941Smrg*
3335b8e80941Smrg*   @brief
3336b8e80941Smrg*       Input structure for Addr2ComputeDccAddrFromCoord
3337b8e80941Smrg*
3338b8e80941Smrg****************************************************************************************************
3339b8e80941Smrg*/
3340b8e80941Smrgtypedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3341b8e80941Smrg{
3342b8e80941Smrg    UINT_32             size;                ///< Size of this structure in bytes
3343b8e80941Smrg
3344b8e80941Smrg    UINT_32             x;                   ///< X coordinate
3345b8e80941Smrg    UINT_32             y;                   ///< Y coordinate
3346b8e80941Smrg    UINT_32             slice;               ///< Index of slices
3347b8e80941Smrg    UINT_32             sample;              ///< Index of samples, means fragment index for EQAA
3348b8e80941Smrg    UINT_32             mipId;               ///< mipmap level id
3349b8e80941Smrg
3350b8e80941Smrg    ADDR2_META_FLAGS    dccKeyFlags;         ///< DCC flags
3351b8e80941Smrg    ADDR2_SURFACE_FLAGS colorFlags;          ///< Color surface flags
3352b8e80941Smrg    AddrResourceType    resourceType;        ///< Color surface type
3353b8e80941Smrg    AddrSwizzleMode     swizzleMode;         ///< Color surface swizzle mode
3354b8e80941Smrg    UINT_32             bpp;                 ///< Color surface bits per pixel
3355b8e80941Smrg    UINT_32             unalignedWidth;      ///< Color surface original width (of mip0)
3356b8e80941Smrg    UINT_32             unalignedHeight;     ///< Color surface original height (of mip0)
3357b8e80941Smrg    UINT_32             numSlices;           ///< Color surface original slices (of mip0)
3358b8e80941Smrg    UINT_32             numMipLevels;        ///< Color surface mipmap levels
3359b8e80941Smrg    UINT_32             numFrags;            ///< Color surface fragment number
3360b8e80941Smrg
3361b8e80941Smrg    UINT_32             pipeXor;             ///< pipe Xor setting
3362b8e80941Smrg} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;
3363b8e80941Smrg
3364b8e80941Smrg/**
3365b8e80941Smrg****************************************************************************************************
3366b8e80941Smrg*   ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3367b8e80941Smrg*
3368b8e80941Smrg*   @brief
3369b8e80941Smrg*       Output structure for Addr2ComputeDccAddrFromCoord
3370b8e80941Smrg****************************************************************************************************
3371b8e80941Smrg*/
3372b8e80941Smrgtypedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3373b8e80941Smrg{
3374b8e80941Smrg    UINT_32    size;           ///< Size of this structure in bytes
3375b8e80941Smrg
3376b8e80941Smrg    UINT_64    addr;           ///< DCC address in bytes
3377b8e80941Smrg} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT;
3378b8e80941Smrg
3379b8e80941Smrg/**
3380b8e80941Smrg****************************************************************************************************
3381b8e80941Smrg*   Addr2ComputeDccAddrFromCoord
3382b8e80941Smrg*
3383b8e80941Smrg*   @brief
3384b8e80941Smrg*       Compute DCC address according to coordinates (of MSAA color buffer)
3385b8e80941Smrg****************************************************************************************************
3386b8e80941Smrg*/
3387b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(
3388b8e80941Smrg    ADDR_HANDLE                                    hLib,
3389b8e80941Smrg    const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT*   pIn,
3390b8e80941Smrg    ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*        pOut);
3391b8e80941Smrg
3392b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
3393b8e80941Smrg//                                     Misc functions for Gfx9
3394b8e80941Smrg////////////////////////////////////////////////////////////////////////////////////////////////////
3395b8e80941Smrg
3396b8e80941Smrg/**
3397b8e80941Smrg****************************************************************************************************
3398b8e80941Smrg*   ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3399b8e80941Smrg*
3400b8e80941Smrg*   @brief
3401b8e80941Smrg*       Input structure of Addr2ComputePipebankXor
3402b8e80941Smrg****************************************************************************************************
3403b8e80941Smrg*/
3404b8e80941Smrgtypedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3405b8e80941Smrg{
3406b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
3407b8e80941Smrg    UINT_32             surfIndex;          ///< Input surface index
3408b8e80941Smrg    ADDR2_SURFACE_FLAGS flags;              ///< Surface flag
3409b8e80941Smrg    AddrSwizzleMode     swizzleMode;        ///< Surface swizzle mode
3410b8e80941Smrg    AddrResourceType    resourceType;       ///< Surface resource type
3411b8e80941Smrg    AddrFormat          format;             ///< Surface format
3412b8e80941Smrg    UINT_32             numSamples;         ///< Number of samples
3413b8e80941Smrg    UINT_32             numFrags;           ///< Number of fragments, leave it zero or the same as
3414b8e80941Smrg                                            ///  number of samples for normal AA; Set it to the
3415b8e80941Smrg                                            ///  number of fragments for EQAA
3416b8e80941Smrg} ADDR2_COMPUTE_PIPEBANKXOR_INPUT;
3417b8e80941Smrg
3418b8e80941Smrg/**
3419b8e80941Smrg****************************************************************************************************
3420b8e80941Smrg*   ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3421b8e80941Smrg*
3422b8e80941Smrg*   @brief
3423b8e80941Smrg*       Output structure of Addr2ComputePipebankXor
3424b8e80941Smrg****************************************************************************************************
3425b8e80941Smrg*/
3426b8e80941Smrgtypedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3427b8e80941Smrg{
3428b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
3429b8e80941Smrg    UINT_32             pipeBankXor;        ///< Pipe bank xor
3430b8e80941Smrg} ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT;
3431b8e80941Smrg
3432b8e80941Smrg/**
3433b8e80941Smrg****************************************************************************************************
3434b8e80941Smrg*   Addr2ComputePipeBankXor
3435b8e80941Smrg*
3436b8e80941Smrg*   @brief
3437b8e80941Smrg*       Calculate a valid bank pipe xor value for client to use.
3438b8e80941Smrg****************************************************************************************************
3439b8e80941Smrg*/
3440b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor(
3441b8e80941Smrg    ADDR_HANDLE                            hLib,
3442b8e80941Smrg    const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
3443b8e80941Smrg    ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT*      pOut);
3444b8e80941Smrg
3445b8e80941Smrg/**
3446b8e80941Smrg****************************************************************************************************
3447b8e80941Smrg*   ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3448b8e80941Smrg*
3449b8e80941Smrg*   @brief
3450b8e80941Smrg*       Input structure of Addr2ComputeSlicePipeBankXor
3451b8e80941Smrg****************************************************************************************************
3452b8e80941Smrg*/
3453b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3454b8e80941Smrg{
3455b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
3456b8e80941Smrg    AddrSwizzleMode     swizzleMode;        ///< Surface swizzle mode
3457b8e80941Smrg    AddrResourceType    resourceType;       ///< Surface resource type
3458b8e80941Smrg    UINT_32             basePipeBankXor;    ///< Base pipe bank xor
3459b8e80941Smrg    UINT_32             slice;              ///< Slice id
3460b8e80941Smrg    UINT_32             numSamples;         ///< Number of samples
3461b8e80941Smrg} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT;
3462b8e80941Smrg
3463b8e80941Smrg/**
3464b8e80941Smrg****************************************************************************************************
3465b8e80941Smrg*   ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3466b8e80941Smrg*
3467b8e80941Smrg*   @brief
3468b8e80941Smrg*       Output structure of Addr2ComputeSlicePipeBankXor
3469b8e80941Smrg****************************************************************************************************
3470b8e80941Smrg*/
3471b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3472b8e80941Smrg{
3473b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
3474b8e80941Smrg    UINT_32             pipeBankXor;        ///< Pipe bank xor
3475b8e80941Smrg} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT;
3476b8e80941Smrg
3477b8e80941Smrg/**
3478b8e80941Smrg****************************************************************************************************
3479b8e80941Smrg*   Addr2ComputeSlicePipeBankXor
3480b8e80941Smrg*
3481b8e80941Smrg*   @brief
3482b8e80941Smrg*       Calculate slice pipe bank xor value based on base pipe bank xor and slice id.
3483b8e80941Smrg****************************************************************************************************
3484b8e80941Smrg*/
3485b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(
3486b8e80941Smrg    ADDR_HANDLE                                  hLib,
3487b8e80941Smrg    const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
3488b8e80941Smrg    ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT*      pOut);
3489b8e80941Smrg
3490b8e80941Smrg/**
3491b8e80941Smrg****************************************************************************************************
3492b8e80941Smrg*   ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3493b8e80941Smrg*
3494b8e80941Smrg*   @brief
3495b8e80941Smrg*       Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3496b8e80941Smrg****************************************************************************************************
3497b8e80941Smrg*/
3498b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3499b8e80941Smrg{
3500b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
3501b8e80941Smrg    AddrSwizzleMode     swizzleMode;        ///< Surface swizzle mode
3502b8e80941Smrg    AddrResourceType    resourceType;       ///< Surface resource type
3503b8e80941Smrg    UINT_32             pipeBankXor;        ///< Per resource xor
3504b8e80941Smrg    UINT_32             slice;              ///< Slice id
3505b8e80941Smrg    UINT_64             sliceSize;          ///< Slice size of a mip chain
3506b8e80941Smrg    UINT_64             macroBlockOffset;   ///< Macro block offset, returned in ADDR2_MIP_INFO
3507b8e80941Smrg    UINT_32             mipTailOffset;      ///< Mip tail offset, returned in ADDR2_MIP_INFO
3508b8e80941Smrg} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT;
3509b8e80941Smrg
3510b8e80941Smrg/**
3511b8e80941Smrg****************************************************************************************************
3512b8e80941Smrg*   ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3513b8e80941Smrg*
3514b8e80941Smrg*   @brief
3515b8e80941Smrg*       Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3516b8e80941Smrg****************************************************************************************************
3517b8e80941Smrg*/
3518b8e80941Smrgtypedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3519b8e80941Smrg{
3520b8e80941Smrg    UINT_32             size;               ///< Size of this structure in bytes
3521b8e80941Smrg    UINT_64             offset;             ///< offset
3522b8e80941Smrg} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT;
3523b8e80941Smrg
3524b8e80941Smrg/**
3525b8e80941Smrg****************************************************************************************************
3526b8e80941Smrg*   Addr2ComputeSubResourceOffsetForSwizzlePattern
3527b8e80941Smrg*
3528b8e80941Smrg*   @brief
3529b8e80941Smrg*       Calculate sub resource offset to support swizzle pattern.
3530b8e80941Smrg****************************************************************************************************
3531b8e80941Smrg*/
3532b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
3533b8e80941Smrg    ADDR_HANDLE                                                     hLib,
3534b8e80941Smrg    const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
3535b8e80941Smrg    ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT*      pOut);
3536b8e80941Smrg
3537b8e80941Smrg/**
3538b8e80941Smrg****************************************************************************************************
3539b8e80941Smrg*   ADDR2_BLOCK_SET
3540b8e80941Smrg*
3541b8e80941Smrg*   @brief
3542b8e80941Smrg*       Bit field that defines block type
3543b8e80941Smrg****************************************************************************************************
3544b8e80941Smrg*/
3545b8e80941Smrgtypedef union _ADDR2_BLOCK_SET
3546b8e80941Smrg{
3547b8e80941Smrg    struct
3548b8e80941Smrg    {
3549b8e80941Smrg        UINT_32 micro       : 1;   // 256B block for 2D resource
3550b8e80941Smrg        UINT_32 macro4KB    : 1;   // 4KB for 2D/3D resource
3551b8e80941Smrg        UINT_32 macro64KB   : 1;   // 64KB for 2D/3D resource
3552b8e80941Smrg        UINT_32 var         : 1;   // VAR block
3553b8e80941Smrg        UINT_32 linear      : 1;   // Linear block
3554b8e80941Smrg        UINT_32 reserved    : 27;
3555b8e80941Smrg    };
3556b8e80941Smrg
3557b8e80941Smrg    UINT_32 value;
3558b8e80941Smrg} ADDR2_BLOCK_SET;
3559b8e80941Smrg
3560b8e80941Smrg/**
3561b8e80941Smrg****************************************************************************************************
3562b8e80941Smrg*   ADDR2_SWTYPE_SET
3563b8e80941Smrg*
3564b8e80941Smrg*   @brief
3565b8e80941Smrg*       Bit field that defines swizzle type
3566b8e80941Smrg****************************************************************************************************
3567b8e80941Smrg*/
3568b8e80941Smrgtypedef union _ADDR2_SWTYPE_SET
3569b8e80941Smrg{
3570b8e80941Smrg    struct
3571b8e80941Smrg    {
3572b8e80941Smrg        UINT_32 sw_Z     : 1;   // SW_*_Z_*
3573b8e80941Smrg        UINT_32 sw_S     : 1;   // SW_*_S_*
3574b8e80941Smrg        UINT_32 sw_D     : 1;   // SW_*_D_*
3575b8e80941Smrg        UINT_32 sw_R     : 1;   // SW_*_R_*
3576b8e80941Smrg        UINT_32 reserved : 28;
3577b8e80941Smrg    };
3578b8e80941Smrg
3579b8e80941Smrg    UINT_32 value;
3580b8e80941Smrg} ADDR2_SWTYPE_SET;
3581b8e80941Smrg
3582b8e80941Smrg/**
3583b8e80941Smrg****************************************************************************************************
3584b8e80941Smrg*   ADDR2_SWMODE_SET
3585b8e80941Smrg*
3586b8e80941Smrg*   @brief
3587b8e80941Smrg*       Bit field that defines swizzle type
3588b8e80941Smrg****************************************************************************************************
3589b8e80941Smrg*/
3590b8e80941Smrgtypedef union _ADDR2_SWMODE_SET
3591b8e80941Smrg{
3592b8e80941Smrg    struct
3593b8e80941Smrg    {
3594b8e80941Smrg        UINT_32 swLinear   : 1;
3595b8e80941Smrg        UINT_32 sw256B_S   : 1;
3596b8e80941Smrg        UINT_32 sw256B_D   : 1;
3597b8e80941Smrg        UINT_32 sw256B_R   : 1;
3598b8e80941Smrg        UINT_32 sw4KB_Z    : 1;
3599b8e80941Smrg        UINT_32 sw4KB_S    : 1;
3600b8e80941Smrg        UINT_32 sw4KB_D    : 1;
3601b8e80941Smrg        UINT_32 sw4KB_R    : 1;
3602b8e80941Smrg        UINT_32 sw64KB_Z   : 1;
3603b8e80941Smrg        UINT_32 sw64KB_S   : 1;
3604b8e80941Smrg        UINT_32 sw64KB_D   : 1;
3605b8e80941Smrg        UINT_32 sw64KB_R   : 1;
3606b8e80941Smrg        UINT_32 swVar_Z    : 1;
3607b8e80941Smrg        UINT_32 swVar_S    : 1;
3608b8e80941Smrg        UINT_32 swVar_D    : 1;
3609b8e80941Smrg        UINT_32 swVar_R    : 1;
3610b8e80941Smrg        UINT_32 sw64KB_Z_T : 1;
3611b8e80941Smrg        UINT_32 sw64KB_S_T : 1;
3612b8e80941Smrg        UINT_32 sw64KB_D_T : 1;
3613b8e80941Smrg        UINT_32 sw64KB_R_T : 1;
3614b8e80941Smrg        UINT_32 sw4KB_Z_X  : 1;
3615b8e80941Smrg        UINT_32 sw4KB_S_X  : 1;
3616b8e80941Smrg        UINT_32 sw4KB_D_X  : 1;
3617b8e80941Smrg        UINT_32 sw4KB_R_X  : 1;
3618b8e80941Smrg        UINT_32 sw64KB_Z_X : 1;
3619b8e80941Smrg        UINT_32 sw64KB_S_X : 1;
3620b8e80941Smrg        UINT_32 sw64KB_D_X : 1;
3621b8e80941Smrg        UINT_32 sw64KB_R_X : 1;
3622b8e80941Smrg        UINT_32 swVar_Z_X  : 1;
3623b8e80941Smrg        UINT_32 swVar_S_X  : 1;
3624b8e80941Smrg        UINT_32 swVar_D_X  : 1;
3625b8e80941Smrg        UINT_32 swVar_R_X  : 1;
3626b8e80941Smrg    };
3627b8e80941Smrg
3628b8e80941Smrg    UINT_32 value;
3629b8e80941Smrg} ADDR2_SWMODE_SET;
3630b8e80941Smrg
3631b8e80941Smrg/**
3632b8e80941Smrg****************************************************************************************************
3633b8e80941Smrg*   ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3634b8e80941Smrg*
3635b8e80941Smrg*   @brief
3636b8e80941Smrg*       Input structure of Addr2GetPreferredSurfaceSetting
3637b8e80941Smrg****************************************************************************************************
3638b8e80941Smrg*/
3639b8e80941Smrgtypedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3640b8e80941Smrg{
3641b8e80941Smrg    UINT_32               size;              ///< Size of this structure in bytes
3642b8e80941Smrg
3643b8e80941Smrg    ADDR2_SURFACE_FLAGS   flags;             ///< Surface flags
3644b8e80941Smrg    AddrResourceType      resourceType;      ///< Surface type
3645b8e80941Smrg    AddrFormat            format;            ///< Surface format
3646b8e80941Smrg    AddrResrouceLocation  resourceLoction;   ///< Surface heap choice
3647b8e80941Smrg    ADDR2_BLOCK_SET       forbiddenBlock;    ///< Client can use it to disable some block setting
3648b8e80941Smrg                                             ///< such as linear for DXTn, tiled for YUV
3649b8e80941Smrg    ADDR2_SWTYPE_SET      preferredSwSet;    ///< Client can use it to specify sw type(s) wanted
3650b8e80941Smrg    BOOL_32               noXor;             ///< Do not use xor mode for this resource
3651b8e80941Smrg    UINT_32               bpp;               ///< bits per pixel
3652b8e80941Smrg    UINT_32               width;             ///< Width (of mip0), in pixels
3653b8e80941Smrg    UINT_32               height;            ///< Height (of mip0), in pixels
3654b8e80941Smrg    UINT_32               numSlices;         ///< Number surface slice/depth (of mip0),
3655b8e80941Smrg    UINT_32               numMipLevels;      ///< Total mipmap levels.
3656b8e80941Smrg    UINT_32               numSamples;        ///< Number of samples
3657b8e80941Smrg    UINT_32               numFrags;          ///< Number of fragments, leave it zero or the same as
3658b8e80941Smrg                                             ///  number of samples for normal AA; Set it to the
3659b8e80941Smrg                                             ///  number of fragments for EQAA
3660b8e80941Smrg    UINT_32               maxAlign;          ///< maximum base/size alignment requested by client
3661b8e80941Smrg    UINT_32               minSizeAlign;      ///< memory allocated for surface in client driver will
3662b8e80941Smrg                                             ///  be padded to multiple of this value (in bytes)
3663b8e80941Smrg} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;
3664b8e80941Smrg
3665b8e80941Smrg/**
3666b8e80941Smrg****************************************************************************************************
3667b8e80941Smrg*   ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3668b8e80941Smrg*
3669b8e80941Smrg*   @brief
3670b8e80941Smrg*       Output structure of Addr2GetPreferredSurfaceSetting
3671b8e80941Smrg****************************************************************************************************
3672b8e80941Smrg*/
3673b8e80941Smrgtypedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3674b8e80941Smrg{
3675b8e80941Smrg    UINT_32               size;                 ///< Size of this structure in bytes
3676b8e80941Smrg
3677b8e80941Smrg    AddrSwizzleMode       swizzleMode;          ///< Suggested swizzle mode to be used
3678b8e80941Smrg    AddrResourceType      resourceType;         ///< Suggested resource type to program HW
3679b8e80941Smrg    ADDR2_BLOCK_SET       validBlockSet;        ///< Valid block type bit conbination
3680b8e80941Smrg    BOOL_32               canXor;               ///< If client can use xor on a valid macro block
3681b8e80941Smrg                                                ///  type
3682b8e80941Smrg    ADDR2_SWTYPE_SET      validSwTypeSet;       ///< Valid swizzle type bit combination
3683b8e80941Smrg    ADDR2_SWTYPE_SET      clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
3684b8e80941Smrg    ADDR2_SWMODE_SET      validSwModeSet;       ///< Valid swizzle mode bit combination
3685b8e80941Smrg} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
3686b8e80941Smrg
3687b8e80941Smrg/**
3688b8e80941Smrg****************************************************************************************************
3689b8e80941Smrg*   Addr2GetPreferredSurfaceSetting
3690b8e80941Smrg*
3691b8e80941Smrg*   @brief
3692b8e80941Smrg*       Suggest a preferred setting for client driver to program HW register
3693b8e80941Smrg****************************************************************************************************
3694b8e80941Smrg*/
3695b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(
3696b8e80941Smrg    ADDR_HANDLE                                   hLib,
3697b8e80941Smrg    const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
3698b8e80941Smrg    ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT*      pOut);
3699b8e80941Smrg
3700b8e80941Smrg/**
3701b8e80941Smrg****************************************************************************************************
3702b8e80941Smrg*   Addr2IsValidDisplaySwizzleMode
3703b8e80941Smrg*
3704b8e80941Smrg*   @brief
3705b8e80941Smrg*       Return whether the swizzle mode is supported by DCE / DCN.
3706b8e80941Smrg****************************************************************************************************
3707b8e80941Smrg*/
3708b8e80941SmrgADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
3709b8e80941Smrg    ADDR_HANDLE     hLib,
3710b8e80941Smrg    AddrSwizzleMode swizzleMode,
3711b8e80941Smrg    UINT_32         bpp,
3712b8e80941Smrg    bool            *result);
3713b8e80941Smrg
3714b8e80941Smrg#if defined(__cplusplus)
3715b8e80941Smrg}
3716b8e80941Smrg#endif
3717b8e80941Smrg
3718b8e80941Smrg#endif // __ADDR_INTERFACE_H__
3719