1/* 2 * Copyright © 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 26#ifndef AC_SURFACE_H 27#define AC_SURFACE_H 28 29#include <stdint.h> 30#include <stdbool.h> 31 32#include "amd_family.h" 33 34#ifdef __cplusplus 35extern "C" { 36#endif 37 38/* Forward declarations. */ 39#ifndef ADDR_HANDLE_TYPEDEF 40#define ADDR_HANDLE_TYPEDEF 41typedef void* ADDR_HANDLE; 42#endif 43 44struct amdgpu_gpu_info; 45struct radeon_info; 46 47#define RADEON_SURF_MAX_LEVELS 15 48 49enum radeon_surf_mode { 50 RADEON_SURF_MODE_LINEAR_ALIGNED = 1, 51 RADEON_SURF_MODE_1D = 2, 52 RADEON_SURF_MODE_2D = 3, 53}; 54 55/* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */ 56enum radeon_micro_mode { 57 RADEON_MICRO_MODE_DISPLAY = 0, 58 RADEON_MICRO_MODE_THIN = 1, 59 RADEON_MICRO_MODE_DEPTH = 2, 60 RADEON_MICRO_MODE_ROTATED = 3, 61}; 62 63/* the first 16 bits are reserved for libdrm_radeon, don't use them */ 64#define RADEON_SURF_SCANOUT (1 << 16) 65#define RADEON_SURF_ZBUFFER (1 << 17) 66#define RADEON_SURF_SBUFFER (1 << 18) 67#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) 68/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */ 69#define RADEON_SURF_FMASK (1 << 21) 70#define RADEON_SURF_DISABLE_DCC (1 << 22) 71#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23) 72#define RADEON_SURF_IMPORTED (1 << 24) 73#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25) 74#define RADEON_SURF_SHAREABLE (1 << 26) 75#define RADEON_SURF_NO_RENDER_TARGET (1 << 27) 76 77struct legacy_surf_level { 78 uint64_t offset; 79 uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ 80 uint32_t dcc_offset; /* relative offset within DCC mip tree */ 81 uint32_t dcc_fast_clear_size; 82 unsigned nblk_x:15; 83 unsigned nblk_y:15; 84 enum radeon_surf_mode mode:2; 85}; 86 87struct legacy_surf_fmask { 88 unsigned slice_tile_max; /* max 4M */ 89 uint8_t tiling_index; /* max 31 */ 90 uint8_t bankh; /* max 8 */ 91 uint16_t pitch_in_pixels; 92}; 93 94struct legacy_surf_layout { 95 unsigned bankw:4; /* max 8 */ 96 unsigned bankh:4; /* max 8 */ 97 unsigned mtilea:4; /* max 8 */ 98 unsigned tile_split:13; /* max 4K */ 99 unsigned stencil_tile_split:13; /* max 4K */ 100 unsigned pipe_config:5; /* max 17 */ 101 unsigned num_banks:5; /* max 16 */ 102 unsigned macro_tile_index:4; /* max 15 */ 103 104 /* Whether the depth miptree or stencil miptree as used by the DB are 105 * adjusted from their TC compatible form to ensure depth/stencil 106 * compatibility. If either is true, the corresponding plane cannot be 107 * sampled from. 108 */ 109 unsigned depth_adjusted:1; 110 unsigned stencil_adjusted:1; 111 112 struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS]; 113 struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; 114 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; 115 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; 116 struct legacy_surf_fmask fmask; 117 unsigned cmask_slice_tile_max; 118}; 119 120/* Same as addrlib - AddrResourceType. */ 121enum gfx9_resource_type { 122 RADEON_RESOURCE_1D = 0, 123 RADEON_RESOURCE_2D, 124 RADEON_RESOURCE_3D, 125}; 126 127struct gfx9_surf_flags { 128 uint16_t swizzle_mode; /* tile mode */ 129 uint16_t epitch; /* (pitch - 1) or (height - 1) */ 130}; 131 132struct gfx9_surf_meta_flags { 133 unsigned rb_aligned:1; /* optimal for RBs */ 134 unsigned pipe_aligned:1; /* optimal for TC */ 135}; 136 137struct gfx9_surf_layout { 138 struct gfx9_surf_flags surf; /* color or depth surface */ 139 struct gfx9_surf_flags fmask; /* not added to surf_size */ 140 struct gfx9_surf_flags stencil; /* added to surf_size, use stencil_offset */ 141 142 struct gfx9_surf_meta_flags dcc; /* metadata of color */ 143 struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */ 144 struct gfx9_surf_meta_flags cmask; /* metadata of fmask */ 145 146 enum gfx9_resource_type resource_type; /* 1D, 2D or 3D */ 147 uint16_t surf_pitch; /* in blocks */ 148 uint16_t surf_height; 149 150 uint64_t surf_offset; /* 0 unless imported with an offset */ 151 /* The size of the 2D plane containing all mipmap levels. */ 152 uint64_t surf_slice_size; 153 /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */ 154 uint32_t offset[RADEON_SURF_MAX_LEVELS]; 155 156 uint64_t stencil_offset; /* separate stencil */ 157 158 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0. 159 * The 3D engine doesn't support that layout except for chips with 1 RB. 160 * All other chips must set rb_aligned=1. 161 * A compute shader needs to convert from aligned DCC to unaligned. 162 */ 163 uint32_t display_dcc_size; 164 uint32_t display_dcc_alignment; 165 uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */ 166 bool dcc_retile_use_uint16; /* if all values fit into uint16_t */ 167 uint32_t dcc_retile_num_elements; 168 uint32_t *dcc_retile_map; 169}; 170 171struct radeon_surf { 172 /* Format properties. */ 173 unsigned blk_w:4; 174 unsigned blk_h:4; 175 unsigned bpe:5; 176 /* Number of mipmap levels where DCC is enabled starting from level 0. 177 * Non-zero levels may be disabled due to alignment constraints, but not 178 * the first level. 179 */ 180 unsigned num_dcc_levels:4; 181 unsigned is_linear:1; 182 unsigned has_stencil:1; 183 /* This might be true even if micro_tile_mode isn't displayable or rotated. */ 184 unsigned is_displayable:1; 185 /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */ 186 unsigned micro_tile_mode:3; 187 uint32_t flags; 188 189 /* These are return values. Some of them can be set by the caller, but 190 * they will be treated as hints (e.g. bankw, bankh) and might be 191 * changed by the calculator. 192 */ 193 194 /* Tile swizzle can be OR'd with low bits of the BASE_256B address. 195 * The value is the same for all mipmap levels. Supported tile modes: 196 * - GFX6: Only macro tiling. 197 * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip 198 * tail. 199 * 200 * Only these surfaces are allowed to set it: 201 * - color (if it doesn't have to be displayable) 202 * - DCC (same tile swizzle as color) 203 * - FMASK 204 * - CMASK if it's TC-compatible or if the gen is GFX9 205 * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9 206 */ 207 uint8_t tile_swizzle; 208 uint8_t fmask_tile_swizzle; 209 210 uint64_t surf_size; 211 uint64_t fmask_size; 212 uint32_t surf_alignment; 213 uint32_t fmask_alignment; 214 215 /* DCC and HTILE are very small. */ 216 uint32_t dcc_size; 217 uint32_t dcc_alignment; 218 219 uint32_t htile_size; 220 uint32_t htile_slice_size; 221 uint32_t htile_alignment; 222 223 uint32_t cmask_size; 224 uint32_t cmask_alignment; 225 226 union { 227 /* R600-VI return values. 228 * 229 * Some of them can be set by the caller if certain parameters are 230 * desirable. The allocator will try to obey them. 231 */ 232 struct legacy_surf_layout legacy; 233 234 /* GFX9+ return values. */ 235 struct gfx9_surf_layout gfx9; 236 } u; 237}; 238 239struct ac_surf_info { 240 uint32_t width; 241 uint32_t height; 242 uint32_t depth; 243 uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */ 244 uint8_t storage_samples; /* For color: allocated samples */ 245 uint8_t levels; 246 uint8_t num_channels; /* heuristic for displayability */ 247 uint16_t array_size; 248 uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */ 249 uint32_t *fmask_surf_index; 250}; 251 252struct ac_surf_config { 253 struct ac_surf_info info; 254 unsigned is_3d : 1; 255 unsigned is_cube : 1; 256}; 257 258ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, 259 const struct amdgpu_gpu_info *amdinfo, 260 uint64_t *max_alignment); 261 262int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, 263 const struct ac_surf_config * config, 264 enum radeon_surf_mode mode, 265 struct radeon_surf *surf); 266 267void ac_compute_cmask(const struct radeon_info *info, 268 const struct ac_surf_config *config, 269 struct radeon_surf *surf); 270 271#ifdef __cplusplus 272} 273#endif 274 275#endif /* AC_SURFACE_H */ 276