1b8e80941Smrg/* 2b8e80941Smrg * Copyright (C) 2012-2018 Rob Clark <robclark@freedesktop.org> 3b8e80941Smrg * 4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5b8e80941Smrg * copy of this software and associated documentation files (the "Software"), 6b8e80941Smrg * to deal in the Software without restriction, including without limitation 7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the 9b8e80941Smrg * Software is furnished to do so, subject to the following conditions: 10b8e80941Smrg * 11b8e80941Smrg * The above copyright notice and this permission notice (including the next 12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the 13b8e80941Smrg * Software. 14b8e80941Smrg * 15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20b8e80941Smrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21b8e80941Smrg * SOFTWARE. 22b8e80941Smrg * 23b8e80941Smrg * Authors: 24b8e80941Smrg * Rob Clark <robclark@freedesktop.org> 25b8e80941Smrg */ 26b8e80941Smrg 27b8e80941Smrg#ifndef FREEDRENO_DRMIF_H_ 28b8e80941Smrg#define FREEDRENO_DRMIF_H_ 29b8e80941Smrg 30b8e80941Smrg#include <stdint.h> 31b8e80941Smrg 32b8e80941Smrg#include "util/u_debug.h" 33b8e80941Smrg 34b8e80941Smrgstruct fd_bo; 35b8e80941Smrgstruct fd_pipe; 36b8e80941Smrgstruct fd_device; 37b8e80941Smrg 38b8e80941Smrgenum fd_pipe_id { 39b8e80941Smrg FD_PIPE_3D = 1, 40b8e80941Smrg FD_PIPE_2D = 2, 41b8e80941Smrg /* some devices have two 2d blocks.. not really sure how to 42b8e80941Smrg * use that yet, so just ignoring the 2nd 2d pipe for now 43b8e80941Smrg */ 44b8e80941Smrg FD_PIPE_MAX 45b8e80941Smrg}; 46b8e80941Smrg 47b8e80941Smrgenum fd_param_id { 48b8e80941Smrg FD_DEVICE_ID, 49b8e80941Smrg FD_GMEM_SIZE, 50b8e80941Smrg FD_GMEM_BASE, 51b8e80941Smrg FD_GPU_ID, 52b8e80941Smrg FD_CHIP_ID, 53b8e80941Smrg FD_MAX_FREQ, 54b8e80941Smrg FD_TIMESTAMP, 55b8e80941Smrg FD_NR_RINGS, /* # of rings == # of distinct priority levels */ 56b8e80941Smrg FD_PP_PGTABLE, /* are per-process pagetables used for the pipe/ctx */ 57b8e80941Smrg FD_CTX_FAULTS, /* # of per context faults */ 58b8e80941Smrg FD_GLOBAL_FAULTS, /* # of global (all context) faults */ 59b8e80941Smrg}; 60b8e80941Smrg 61b8e80941Smrg/* bo flags: */ 62b8e80941Smrg#define DRM_FREEDRENO_GEM_TYPE_SMI 0x00000001 63b8e80941Smrg#define DRM_FREEDRENO_GEM_TYPE_KMEM 0x00000002 64b8e80941Smrg#define DRM_FREEDRENO_GEM_TYPE_MEM_MASK 0x0000000f 65b8e80941Smrg#define DRM_FREEDRENO_GEM_CACHE_NONE 0x00000000 66b8e80941Smrg#define DRM_FREEDRENO_GEM_CACHE_WCOMBINE 0x00100000 67b8e80941Smrg#define DRM_FREEDRENO_GEM_CACHE_WTHROUGH 0x00200000 68b8e80941Smrg#define DRM_FREEDRENO_GEM_CACHE_WBACK 0x00400000 69b8e80941Smrg#define DRM_FREEDRENO_GEM_CACHE_WBACKWA 0x00800000 70b8e80941Smrg#define DRM_FREEDRENO_GEM_CACHE_MASK 0x00f00000 71b8e80941Smrg#define DRM_FREEDRENO_GEM_GPUREADONLY 0x01000000 72b8e80941Smrg#define DRM_FREEDRENO_GEM_SCANOUT 0x02000000 73b8e80941Smrg 74b8e80941Smrg/* bo access flags: (keep aligned to MSM_PREP_x) */ 75b8e80941Smrg#define DRM_FREEDRENO_PREP_READ 0x01 76b8e80941Smrg#define DRM_FREEDRENO_PREP_WRITE 0x02 77b8e80941Smrg#define DRM_FREEDRENO_PREP_NOSYNC 0x04 78b8e80941Smrg 79b8e80941Smrg/* device functions: 80b8e80941Smrg */ 81b8e80941Smrg 82b8e80941Smrgstruct fd_device * fd_device_new(int fd); 83b8e80941Smrgstruct fd_device * fd_device_new_dup(int fd); 84b8e80941Smrgstruct fd_device * fd_device_ref(struct fd_device *dev); 85b8e80941Smrgvoid fd_device_del(struct fd_device *dev); 86b8e80941Smrgint fd_device_fd(struct fd_device *dev); 87b8e80941Smrg 88b8e80941Smrgenum fd_version { 89b8e80941Smrg FD_VERSION_MADVISE = 1, /* kernel supports madvise */ 90b8e80941Smrg FD_VERSION_UNLIMITED_CMDS = 1, /* submits w/ >4 cmd buffers (growable ringbuffer) */ 91b8e80941Smrg FD_VERSION_FENCE_FD = 2, /* submit command supports in/out fences */ 92b8e80941Smrg FD_VERSION_GMEM_BASE = 3, /* supports querying GMEM base address */ 93b8e80941Smrg FD_VERSION_SUBMIT_QUEUES = 3, /* submit queues and multiple priority levels */ 94b8e80941Smrg FD_VERSION_BO_IOVA = 3, /* supports fd_bo_get/put_iova() */ 95b8e80941Smrg FD_VERSION_SOFTPIN = 4, /* adds softpin, bo name, and dump flag */ 96b8e80941Smrg FD_VERSION_ROBUSTNESS = 5, /* adds FD_NR_FAULTS and FD_PP_PGTABLE */ 97b8e80941Smrg}; 98b8e80941Smrgenum fd_version fd_device_version(struct fd_device *dev); 99b8e80941Smrg 100b8e80941Smrg/* pipe functions: 101b8e80941Smrg */ 102b8e80941Smrg 103b8e80941Smrgstruct fd_pipe * fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id); 104b8e80941Smrgstruct fd_pipe * fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio); 105b8e80941Smrgstruct fd_pipe * fd_pipe_ref(struct fd_pipe *pipe); 106b8e80941Smrgvoid fd_pipe_del(struct fd_pipe *pipe); 107b8e80941Smrgint fd_pipe_get_param(struct fd_pipe *pipe, enum fd_param_id param, 108b8e80941Smrg uint64_t *value); 109b8e80941Smrgint fd_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp); 110b8e80941Smrg/* timeout in nanosec */ 111b8e80941Smrgint fd_pipe_wait_timeout(struct fd_pipe *pipe, uint32_t timestamp, 112b8e80941Smrg uint64_t timeout); 113b8e80941Smrg 114b8e80941Smrg 115b8e80941Smrg/* buffer-object functions: 116b8e80941Smrg */ 117b8e80941Smrg 118b8e80941Smrgstruct fd_bo * _fd_bo_new(struct fd_device *dev, 119b8e80941Smrg uint32_t size, uint32_t flags); 120b8e80941Smrgvoid _fd_bo_set_name(struct fd_bo *bo, const char *fmt, va_list ap); 121b8e80941Smrg 122b8e80941Smrgstatic inline void 123b8e80941Smrgfd_bo_set_name(struct fd_bo *bo, const char *fmt, ...) _util_printf_format(2, 3); 124b8e80941Smrg 125b8e80941Smrgstatic inline void 126b8e80941Smrgfd_bo_set_name(struct fd_bo *bo, const char *fmt, ...) 127b8e80941Smrg{ 128b8e80941Smrg#ifndef NDEBUG 129b8e80941Smrg va_list ap; 130b8e80941Smrg va_start(ap, fmt); 131b8e80941Smrg _fd_bo_set_name(bo, fmt, ap); 132b8e80941Smrg va_end(ap); 133b8e80941Smrg#endif 134b8e80941Smrg} 135b8e80941Smrg 136b8e80941Smrgstatic inline struct fd_bo * 137b8e80941Smrgfd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags, 138b8e80941Smrg const char *fmt, ...) _util_printf_format(4, 5); 139b8e80941Smrg 140b8e80941Smrgstatic inline struct fd_bo * 141b8e80941Smrgfd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags, 142b8e80941Smrg const char *fmt, ...) 143b8e80941Smrg{ 144b8e80941Smrg struct fd_bo *bo = _fd_bo_new(dev, size, flags); 145b8e80941Smrg#ifndef NDEBUG 146b8e80941Smrg if (fmt) { 147b8e80941Smrg va_list ap; 148b8e80941Smrg va_start(ap, fmt); 149b8e80941Smrg _fd_bo_set_name(bo, fmt, ap); 150b8e80941Smrg va_end(ap); 151b8e80941Smrg } 152b8e80941Smrg#endif 153b8e80941Smrg return bo; 154b8e80941Smrg} 155b8e80941Smrg 156b8e80941Smrgstruct fd_bo *fd_bo_from_handle(struct fd_device *dev, 157b8e80941Smrg uint32_t handle, uint32_t size); 158b8e80941Smrgstruct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name); 159b8e80941Smrgstruct fd_bo * fd_bo_from_dmabuf(struct fd_device *dev, int fd); 160b8e80941Smrguint64_t fd_bo_get_iova(struct fd_bo *bo); 161b8e80941Smrgvoid fd_bo_put_iova(struct fd_bo *bo); 162b8e80941Smrgstruct fd_bo * fd_bo_ref(struct fd_bo *bo); 163b8e80941Smrgvoid fd_bo_del(struct fd_bo *bo); 164b8e80941Smrgint fd_bo_get_name(struct fd_bo *bo, uint32_t *name); 165b8e80941Smrguint32_t fd_bo_handle(struct fd_bo *bo); 166b8e80941Smrgint fd_bo_dmabuf(struct fd_bo *bo); 167b8e80941Smrguint32_t fd_bo_size(struct fd_bo *bo); 168b8e80941Smrgvoid * fd_bo_map(struct fd_bo *bo); 169b8e80941Smrgint fd_bo_cpu_prep(struct fd_bo *bo, struct fd_pipe *pipe, uint32_t op); 170b8e80941Smrgvoid fd_bo_cpu_fini(struct fd_bo *bo); 171b8e80941Smrg 172b8e80941Smrg#endif /* FREEDRENO_DRMIF_H_ */ 173