1/* 2 * Copyright (c) 2014-2015 Etnaviv Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Wladimir J. van der Laan <laanwj@gmail.com> 25 */ 26 27#include "etnaviv_emit.h" 28 29#include "etnaviv_blend.h" 30#include "etnaviv_compiler.h" 31#include "etnaviv_context.h" 32#include "etnaviv_rasterizer.h" 33#include "etnaviv_resource.h" 34#include "etnaviv_rs.h" 35#include "etnaviv_screen.h" 36#include "etnaviv_shader.h" 37#include "etnaviv_texture.h" 38#include "etnaviv_translate.h" 39#include "etnaviv_uniforms.h" 40#include "etnaviv_util.h" 41#include "etnaviv_zsa.h" 42#include "hw/common.xml.h" 43#include "hw/state.xml.h" 44#include "hw/state_blt.xml.h" 45#include "util/u_math.h" 46 47/* Queue a STALL command (queues 2 words) */ 48static inline void 49CMD_STALL(struct etna_cmd_stream *stream, uint32_t from, uint32_t to) 50{ 51 etna_cmd_stream_emit(stream, VIV_FE_STALL_HEADER_OP_STALL); 52 etna_cmd_stream_emit(stream, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to)); 53} 54 55void 56etna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to) 57{ 58 bool blt = (from == SYNC_RECIPIENT_BLT) || (to == SYNC_RECIPIENT_BLT); 59 etna_cmd_stream_reserve(stream, blt ? 8 : 4); 60 61 if (blt) { 62 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0); 63 etna_cmd_stream_emit(stream, 1); 64 } 65 66 /* TODO: set bit 28/29 of token after BLT COPY_BUFFER */ 67 etna_emit_load_state(stream, VIVS_GL_SEMAPHORE_TOKEN >> 2, 1, 0); 68 etna_cmd_stream_emit(stream, VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | VIVS_GL_SEMAPHORE_TOKEN_TO(to)); 69 70 if (from == SYNC_RECIPIENT_FE) { 71 /* if the frontend is to be stalled, queue a STALL frontend command */ 72 CMD_STALL(stream, from, to); 73 } else { 74 /* otherwise, load the STALL token state */ 75 etna_emit_load_state(stream, VIVS_GL_STALL_TOKEN >> 2, 1, 0); 76 etna_cmd_stream_emit(stream, VIVS_GL_STALL_TOKEN_FROM(from) | VIVS_GL_STALL_TOKEN_TO(to)); 77 } 78 79 if (blt) { 80 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0); 81 etna_cmd_stream_emit(stream, 0); 82 } 83} 84 85#define EMIT_STATE(state_name, src_value) \ 86 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value) 87 88#define EMIT_STATE_FIXP(state_name, src_value) \ 89 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value) 90 91#define EMIT_STATE_RELOC(state_name, src_value) \ 92 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value) 93 94#define ETNA_3D_CONTEXT_SIZE (400) /* keep this number above "Total state updates (fixed)" from gen_weave_state tool */ 95 96static unsigned 97required_stream_size(struct etna_context *ctx) 98{ 99 unsigned size = ETNA_3D_CONTEXT_SIZE; 100 101 /* stall + flush */ 102 size += 2 + 4; 103 104 /* vertex elements */ 105 size += ctx->vertex_elements->num_elements + 1; 106 107 /* uniforms - worst case (2 words per uniform load) */ 108 size += ctx->shader.vs->uniforms.const_count * 2; 109 size += ctx->shader.fs->uniforms.const_count * 2; 110 111 /* shader */ 112 size += ctx->shader_state.vs_inst_mem_size + 1; 113 size += ctx->shader_state.ps_inst_mem_size + 1; 114 115 /* DRAW_INDEXED_PRIMITIVES command */ 116 size += 6; 117 118 /* reserve for alignment etc. */ 119 size += 64; 120 121 return size; 122} 123 124/* Emit state that only exists on HALTI5+ */ 125static void 126emit_halti5_only_state(struct etna_context *ctx, int vs_output_count) 127{ 128 struct etna_cmd_stream *stream = ctx->stream; 129 uint32_t dirty = ctx->dirty; 130 struct etna_coalesce coalesce; 131 132 etna_coalesce_start(stream, &coalesce); 133 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 134 /* Magic states (load balancing, inter-unit sync, buffers) */ 135 /*00870*/ EMIT_STATE(VS_HALTI5_OUTPUT_COUNT, vs_output_count | ((vs_output_count * 0x10) << 8)); 136 /*008A0*/ EMIT_STATE(VS_HALTI5_UNK008A0, 0x0001000e | ((0x110/vs_output_count) << 20)); 137 for (int x = 0; x < 4; ++x) { 138 /*008E0*/ EMIT_STATE(VS_HALTI5_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]); 139 } 140 } 141 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) { 142 for (int x = 0; x < 4; ++x) { 143 /*008C0*/ EMIT_STATE(VS_HALTI5_INPUT(x), ctx->shader_state.VS_INPUT[x]); 144 } 145 } 146 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 147 /*00A90*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS); 148 /*00AA8*/ EMIT_STATE(PA_VS_OUTPUT_COUNT, vs_output_count); 149 /*01080*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS); 150 /*03888*/ EMIT_STATE(GL_HALTI5_SH_SPECIALS, ctx->shader_state.GL_HALTI5_SH_SPECIALS); 151 } 152 etna_coalesce_end(stream, &coalesce); 153} 154 155/* Emit state that no longer exists on HALTI5 */ 156static void 157emit_pre_halti5_state(struct etna_context *ctx) 158{ 159 struct etna_cmd_stream *stream = ctx->stream; 160 uint32_t dirty = ctx->dirty; 161 struct etna_coalesce coalesce; 162 163 etna_coalesce_start(stream, &coalesce); 164 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 165 /*00800*/ EMIT_STATE(VS_END_PC, ctx->shader_state.VS_END_PC); 166 } 167 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 168 for (int x = 0; x < 4; ++x) { 169 /*00810*/ EMIT_STATE(VS_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]); 170 } 171 } 172 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) { 173 for (int x = 0; x < 4; ++x) { 174 /*00820*/ EMIT_STATE(VS_INPUT(x), ctx->shader_state.VS_INPUT[x]); 175 } 176 } 177 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 178 /*00838*/ EMIT_STATE(VS_START_PC, ctx->shader_state.VS_START_PC); 179 } 180 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 181 for (int x = 0; x < 10; ++x) { 182 /*00A40*/ EMIT_STATE(PA_SHADER_ATTRIBUTES(x), ctx->shader_state.PA_SHADER_ATTRIBUTES[x]); 183 } 184 } 185 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { 186 /*00E04*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E04, ctx->framebuffer.RA_MULTISAMPLE_UNK00E04); 187 for (int x = 0; x < 4; ++x) { 188 /*00E10*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E10(x), ctx->framebuffer.RA_MULTISAMPLE_UNK00E10[x]); 189 } 190 for (int x = 0; x < 16; ++x) { 191 /*00E40*/ EMIT_STATE(RA_CENTROID_TABLE(x), ctx->framebuffer.RA_CENTROID_TABLE[x]); 192 } 193 } 194 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) { 195 /*01000*/ EMIT_STATE(PS_END_PC, ctx->shader_state.PS_END_PC); 196 } 197 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) { 198 /*01018*/ EMIT_STATE(PS_START_PC, ctx->shader_state.PS_START_PC); 199 } 200 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 201 /*03820*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS, ctx->shader_state.GL_VARYING_NUM_COMPONENTS); 202 for (int x = 0; x < 2; ++x) { 203 /*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), ctx->shader_state.GL_VARYING_COMPONENT_USE[x]); 204 } 205 } 206 etna_coalesce_end(stream, &coalesce); 207} 208 209/* Weave state before draw operation. This function merges all the compiled 210 * state blocks under the context into one device register state. Parts of 211 * this state that are changed since last call (dirty) will be uploaded as 212 * state changes in the command buffer. */ 213void 214etna_emit_state(struct etna_context *ctx) 215{ 216 struct etna_cmd_stream *stream = ctx->stream; 217 218 /* Pre-reserve the command buffer space which we are likely to need. 219 * This must cover all the state emitted below, and the following 220 * draw command. */ 221 etna_cmd_stream_reserve(stream, required_stream_size(ctx)); 222 223 uint32_t dirty = ctx->dirty; 224 225 /* Pre-processing: see what caches we need to flush before making state changes. */ 226 uint32_t to_flush = 0; 227 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) { 228 /* Need flush COLOR when changing PE.COLOR_FORMAT.OVERWRITE. */ 229#if 0 230 /* TODO*/ 231 if ((ctx->gpu3d.PE_COLOR_FORMAT & VIVS_PE_COLOR_FORMAT_OVERWRITE) != 232 (etna_blend_state(ctx->blend)->PE_COLOR_FORMAT & VIVS_PE_COLOR_FORMAT_OVERWRITE)) 233#endif 234 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR; 235 } 236 if (unlikely(dirty & (ETNA_DIRTY_TEXTURE_CACHES))) 237 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE; 238 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) /* Framebuffer config changed? */ 239 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH; 240 if (DBG_ENABLED(ETNA_DBG_CFLUSH_ALL)) 241 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE | VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH; 242 243 if (to_flush) { 244 etna_set_state(stream, VIVS_GL_FLUSH_CACHE, to_flush); 245 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE); 246 } 247 248 /* Flush TS cache before changing TS configuration. */ 249 if (unlikely(dirty & ETNA_DIRTY_TS)) { 250 etna_set_state(stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH); 251 } 252 253 /* Update vertex elements. This is different from any of the other states, in that 254 * a) the number of vertex elements written matters: so write only active ones 255 * b) the vertex element states must all be written: do not skip entries that stay the same */ 256 if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) { 257 if (ctx->specs.halti >= 5) { 258 /*17800*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0), 259 ctx->vertex_elements->num_elements, 260 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG0); 261 /*17A00*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_SCALE(0), 262 ctx->vertex_elements->num_elements, 263 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE); 264 /*17A80*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG1(0), 265 ctx->vertex_elements->num_elements, 266 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG1); 267 } else { 268 /* Special case: vertex elements must always be sent in full if changed */ 269 /*00600*/ etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0), 270 ctx->vertex_elements->num_elements, 271 ctx->vertex_elements->FE_VERTEX_ELEMENT_CONFIG); 272 if (ctx->specs.halti >= 2) { 273 /*00780*/ etna_set_state_multi(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0), 274 ctx->vertex_elements->num_elements, 275 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE); 276 } 277 } 278 } 279 unsigned vs_output_count = etna_rasterizer_state(ctx->rasterizer)->point_size_per_vertex 280 ? ctx->shader_state.VS_OUTPUT_COUNT_PSIZE 281 : ctx->shader_state.VS_OUTPUT_COUNT; 282 283 /* The following code is originally generated by gen_merge_state.py, to 284 * emit state in increasing order of address (this makes it possible to merge 285 * consecutive register updates into one SET_STATE command) 286 * 287 * There have been some manual changes, where the weaving operation is not 288 * simply bitwise or: 289 * - scissor fixp 290 * - num vertex elements 291 * - scissor handling 292 * - num samplers 293 * - texture lod 294 * - ETNA_DIRTY_TS 295 * - removed ETNA_DIRTY_BASE_SETUP statements -- these are guaranteed to not 296 * change anyway 297 * - PS / framebuffer interaction for MSAA 298 * - move update of GL_MULTI_SAMPLE_CONFIG first 299 * - add unlikely()/likely() 300 */ 301 struct etna_coalesce coalesce; 302 303 etna_coalesce_start(stream, &coalesce); 304 305 /* begin only EMIT_STATE -- make sure no new etna_reserve calls are done here 306 * directly 307 * or indirectly */ 308 /* multi sample config is set first, and outside of the normal sorting 309 * order, as changing the multisample state clobbers PS.INPUT_COUNT (and 310 * possibly PS.TEMP_REGISTER_CONTROL). 311 */ 312 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_SAMPLE_MASK))) { 313 uint32_t val = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(ctx->sample_mask); 314 val |= ctx->framebuffer.GL_MULTI_SAMPLE_CONFIG; 315 316 /*03818*/ EMIT_STATE(GL_MULTI_SAMPLE_CONFIG, val); 317 } 318 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) { 319 /*00644*/ EMIT_STATE_RELOC(FE_INDEX_STREAM_BASE_ADDR, &ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR); 320 /*00648*/ EMIT_STATE(FE_INDEX_STREAM_CONTROL, ctx->index_buffer.FE_INDEX_STREAM_CONTROL); 321 } 322 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) { 323 /*00674*/ EMIT_STATE(FE_PRIMITIVE_RESTART_INDEX, ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX); 324 } 325 if (likely(dirty & (ETNA_DIRTY_VERTEX_BUFFERS))) { 326 if (ctx->specs.halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */ 327 for (int x = 0; x < ctx->vertex_buffer.count; ++x) { 328 /*14600*/ EMIT_STATE_RELOC(NFE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR); 329 } 330 for (int x = 0; x < ctx->vertex_buffer.count; ++x) { 331 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) { 332 /*14640*/ EMIT_STATE(NFE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_CONTROL); 333 } 334 } 335 for (int x = 0; x < ctx->vertex_buffer.count; ++x) { 336 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) { 337 /*14680*/ EMIT_STATE(NFE_VERTEX_STREAMS_UNK14680(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_UNK14680); 338 } 339 } 340 } else if(ctx->specs.stream_count >= 1) { /* hw w/ multiple vertex streams */ 341 for (int x = 0; x < ctx->vertex_buffer.count; ++x) { 342 /*00680*/ EMIT_STATE_RELOC(FE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR); 343 } 344 for (int x = 0; x < ctx->vertex_buffer.count; ++x) { 345 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) { 346 /*006A0*/ EMIT_STATE(FE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_CONTROL); 347 } 348 } 349 } else { /* hw w/ single vertex stream */ 350 /*0064C*/ EMIT_STATE_RELOC(FE_VERTEX_STREAM_BASE_ADDR, &ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_BASE_ADDR); 351 /*00650*/ EMIT_STATE(FE_VERTEX_STREAM_CONTROL, ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_CONTROL); 352 } 353 } 354 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_RASTERIZER))) { 355 356 /*00804*/ EMIT_STATE(VS_OUTPUT_COUNT, vs_output_count); 357 } 358 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) { 359 /*00808*/ EMIT_STATE(VS_INPUT_COUNT, ctx->shader_state.VS_INPUT_COUNT); 360 /*0080C*/ EMIT_STATE(VS_TEMP_REGISTER_CONTROL, ctx->shader_state.VS_TEMP_REGISTER_CONTROL); 361 } 362 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 363 /*00830*/ EMIT_STATE(VS_LOAD_BALANCING, ctx->shader_state.VS_LOAD_BALANCING); 364 } 365 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) { 366 /*00A00*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_X, ctx->viewport.PA_VIEWPORT_SCALE_X); 367 /*00A04*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_Y, ctx->viewport.PA_VIEWPORT_SCALE_Y); 368 /*00A08*/ EMIT_STATE(PA_VIEWPORT_SCALE_Z, ctx->viewport.PA_VIEWPORT_SCALE_Z); 369 /*00A0C*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_X, ctx->viewport.PA_VIEWPORT_OFFSET_X); 370 /*00A10*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_Y, ctx->viewport.PA_VIEWPORT_OFFSET_Y); 371 /*00A14*/ EMIT_STATE(PA_VIEWPORT_OFFSET_Z, ctx->viewport.PA_VIEWPORT_OFFSET_Z); 372 } 373 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) { 374 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); 375 376 /*00A18*/ EMIT_STATE(PA_LINE_WIDTH, rasterizer->PA_LINE_WIDTH); 377 /*00A1C*/ EMIT_STATE(PA_POINT_SIZE, rasterizer->PA_POINT_SIZE); 378 /*00A28*/ EMIT_STATE(PA_SYSTEM_MODE, rasterizer->PA_SYSTEM_MODE); 379 } 380 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 381 /*00A30*/ EMIT_STATE(PA_ATTRIBUTE_ELEMENT_COUNT, ctx->shader_state.PA_ATTRIBUTE_ELEMENT_COUNT); 382 } 383 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_SHADER))) { 384 uint32_t val = etna_rasterizer_state(ctx->rasterizer)->PA_CONFIG; 385 /*00A34*/ EMIT_STATE(PA_CONFIG, val & ctx->shader_state.PA_CONFIG); 386 } 387 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) { 388 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); 389 /*00A38*/ EMIT_STATE(PA_WIDE_LINE_WIDTH0, rasterizer->PA_LINE_WIDTH); 390 /*00A3C*/ EMIT_STATE(PA_WIDE_LINE_WIDTH1, rasterizer->PA_LINE_WIDTH); 391 } 392 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER | 393 ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) { 394 /* this is a bit of a mess: rasterizer.scissor determines whether to use 395 * only the framebuffer scissor, or specific scissor state, and the 396 * viewport clips too so the logic spans four CSOs */ 397 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); 398 399 uint32_t scissor_left = 400 MAX2(ctx->framebuffer.SE_SCISSOR_LEFT, ctx->viewport.SE_SCISSOR_LEFT); 401 uint32_t scissor_top = 402 MAX2(ctx->framebuffer.SE_SCISSOR_TOP, ctx->viewport.SE_SCISSOR_TOP); 403 uint32_t scissor_right = 404 MIN2(ctx->framebuffer.SE_SCISSOR_RIGHT, ctx->viewport.SE_SCISSOR_RIGHT); 405 uint32_t scissor_bottom = 406 MIN2(ctx->framebuffer.SE_SCISSOR_BOTTOM, ctx->viewport.SE_SCISSOR_BOTTOM); 407 408 if (rasterizer->scissor) { 409 scissor_left = MAX2(ctx->scissor.SE_SCISSOR_LEFT, scissor_left); 410 scissor_top = MAX2(ctx->scissor.SE_SCISSOR_TOP, scissor_top); 411 scissor_right = MIN2(ctx->scissor.SE_SCISSOR_RIGHT, scissor_right); 412 scissor_bottom = MIN2(ctx->scissor.SE_SCISSOR_BOTTOM, scissor_bottom); 413 } 414 415 /*00C00*/ EMIT_STATE_FIXP(SE_SCISSOR_LEFT, scissor_left); 416 /*00C04*/ EMIT_STATE_FIXP(SE_SCISSOR_TOP, scissor_top); 417 /*00C08*/ EMIT_STATE_FIXP(SE_SCISSOR_RIGHT, scissor_right); 418 /*00C0C*/ EMIT_STATE_FIXP(SE_SCISSOR_BOTTOM, scissor_bottom); 419 } 420 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) { 421 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); 422 423 /*00C10*/ EMIT_STATE(SE_DEPTH_SCALE, rasterizer->SE_DEPTH_SCALE); 424 /*00C14*/ EMIT_STATE(SE_DEPTH_BIAS, rasterizer->SE_DEPTH_BIAS); 425 /*00C18*/ EMIT_STATE(SE_CONFIG, rasterizer->SE_CONFIG); 426 } 427 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER | 428 ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) { 429 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); 430 431 uint32_t clip_right = 432 MIN2(ctx->framebuffer.SE_CLIP_RIGHT, ctx->viewport.SE_CLIP_RIGHT); 433 uint32_t clip_bottom = 434 MIN2(ctx->framebuffer.SE_CLIP_BOTTOM, ctx->viewport.SE_CLIP_BOTTOM); 435 436 if (rasterizer->scissor) { 437 clip_right = MIN2(ctx->scissor.SE_CLIP_RIGHT, clip_right); 438 clip_bottom = MIN2(ctx->scissor.SE_CLIP_BOTTOM, clip_bottom); 439 } 440 441 /*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, clip_right); 442 /*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, clip_bottom); 443 } 444 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 445 /*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL); 446 } 447 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) { 448 /*01004*/ EMIT_STATE(PS_OUTPUT_REG, ctx->shader_state.PS_OUTPUT_REG); 449 /*01008*/ EMIT_STATE(PS_INPUT_COUNT, 450 ctx->framebuffer.msaa_mode 451 ? ctx->shader_state.PS_INPUT_COUNT_MSAA 452 : ctx->shader_state.PS_INPUT_COUNT); 453 /*0100C*/ EMIT_STATE(PS_TEMP_REGISTER_CONTROL, 454 ctx->framebuffer.msaa_mode 455 ? ctx->shader_state.PS_TEMP_REGISTER_CONTROL_MSAA 456 : ctx->shader_state.PS_TEMP_REGISTER_CONTROL); 457 /*01010*/ EMIT_STATE(PS_CONTROL, ctx->shader_state.PS_CONTROL); 458 } 459 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_FRAMEBUFFER))) { 460 uint32_t val = etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG; 461 /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, val | ctx->framebuffer.PE_DEPTH_CONFIG); 462 } 463 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) { 464 /*01404*/ EMIT_STATE(PE_DEPTH_NEAR, ctx->viewport.PE_DEPTH_NEAR); 465 /*01408*/ EMIT_STATE(PE_DEPTH_FAR, ctx->viewport.PE_DEPTH_FAR); 466 } 467 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { 468 /*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE); 469 470 if (ctx->specs.pixel_pipes == 1) { 471 /*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR); 472 } 473 474 /*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE); 475 } 476 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) { 477 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP; 478 /*01418*/ EMIT_STATE(PE_STENCIL_OP, val); 479 } 480 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF))) { 481 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG; 482 /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG); 483 } 484 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) { 485 uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP; 486 /*01420*/ EMIT_STATE(PE_ALPHA_OP, val); 487 } 488 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR))) { 489 /*01424*/ EMIT_STATE(PE_ALPHA_BLEND_COLOR, ctx->blend_color.PE_ALPHA_BLEND_COLOR); 490 } 491 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) { 492 uint32_t val = etna_blend_state(ctx->blend)->PE_ALPHA_CONFIG; 493 /*01428*/ EMIT_STATE(PE_ALPHA_CONFIG, val); 494 } 495 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) { 496 uint32_t val; 497 /* Use the components and overwrite bits in framebuffer.PE_COLOR_FORMAT 498 * as a mask to enable the bits from blend PE_COLOR_FORMAT */ 499 val = ~(VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK | 500 VIVS_PE_COLOR_FORMAT_OVERWRITE); 501 val |= etna_blend_state(ctx->blend)->PE_COLOR_FORMAT; 502 val &= ctx->framebuffer.PE_COLOR_FORMAT; 503 /*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val); 504 } 505 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { 506 if (ctx->specs.pixel_pipes == 1) { 507 /*01430*/ EMIT_STATE_RELOC(PE_COLOR_ADDR, &ctx->framebuffer.PE_COLOR_ADDR); 508 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE); 509 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL); 510 } else if (ctx->specs.pixel_pipes == 2) { 511 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE); 512 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL); 513 /*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]); 514 /*01464*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(1), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[1]); 515 /*01480*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(0), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[0]); 516 /*01484*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(1), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[1]); 517 } else { 518 abort(); 519 } 520 } 521 if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF))) { 522 /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, ctx->stencil_ref.PE_STENCIL_CONFIG_EXT); 523 } 524 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) { 525 struct etna_blend_state *blend = etna_blend_state(ctx->blend); 526 /*014A4*/ EMIT_STATE(PE_LOGIC_OP, blend->PE_LOGIC_OP | ctx->framebuffer.PE_LOGIC_OP); 527 } 528 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) { 529 struct etna_blend_state *blend = etna_blend_state(ctx->blend); 530 for (int x = 0; x < 2; ++x) { 531 /*014A8*/ EMIT_STATE(PE_DITHER(x), blend->PE_DITHER[x]); 532 } 533 } 534 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) { 535 /*01654*/ EMIT_STATE(TS_MEM_CONFIG, ctx->framebuffer.TS_MEM_CONFIG); 536 /*01658*/ EMIT_STATE_RELOC(TS_COLOR_STATUS_BASE, &ctx->framebuffer.TS_COLOR_STATUS_BASE); 537 /*0165C*/ EMIT_STATE_RELOC(TS_COLOR_SURFACE_BASE, &ctx->framebuffer.TS_COLOR_SURFACE_BASE); 538 /*01660*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE, ctx->framebuffer.TS_COLOR_CLEAR_VALUE); 539 /*01664*/ EMIT_STATE_RELOC(TS_DEPTH_STATUS_BASE, &ctx->framebuffer.TS_DEPTH_STATUS_BASE); 540 /*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, &ctx->framebuffer.TS_DEPTH_SURFACE_BASE); 541 /*0166C*/ EMIT_STATE(TS_DEPTH_CLEAR_VALUE, ctx->framebuffer.TS_DEPTH_CLEAR_VALUE); 542 } 543 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { 544 /*0381C*/ EMIT_STATE(GL_VARYING_TOTAL_COMPONENTS, ctx->shader_state.GL_VARYING_TOTAL_COMPONENTS); 545 } 546 etna_coalesce_end(stream, &coalesce); 547 /* end only EMIT_STATE */ 548 549 /* Emit strongly architecture-specific state */ 550 if (ctx->specs.halti >= 5) 551 emit_halti5_only_state(ctx, vs_output_count); 552 else 553 emit_pre_halti5_state(ctx); 554 555 ctx->emit_texture_state(ctx); 556 557 /* Insert a FE/PE stall as changing the shader instructions (and maybe 558 * the uniforms) can corrupt the previous in-progress draw operation. 559 * Observed with amoeba on GC2000 during the right-to-left rendering 560 * of PI, and can cause GPU hangs immediately after. 561 * I summise that this is because the "new" locations at 0xc000 are not 562 * properly protected against updates as other states seem to be. Hence, 563 * we detect the "new" vertex shader instruction offset to apply this. */ 564 if (ctx->dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF) && ctx->specs.vs_offset > 0x4000) 565 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 566 567 /* We need to update the uniform cache only if one of the following bits are 568 * set in ctx->dirty: 569 * - ETNA_DIRTY_SHADER 570 * - ETNA_DIRTY_CONSTBUF 571 * - uniforms_dirty_bits 572 * 573 * In case of ETNA_DIRTY_SHADER we need load all uniforms from the cache. In 574 * all 575 * other cases we can load on the changed uniforms. 576 */ 577 static const uint32_t uniform_dirty_bits = 578 ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF; 579 580 if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits)) 581 etna_uniforms_write( 582 ctx, ctx->shader.vs, &ctx->constant_buffer[PIPE_SHADER_VERTEX], 583 ctx->shader_state.VS_UNIFORMS, &ctx->shader_state.vs_uniforms_size); 584 585 if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits)) 586 etna_uniforms_write( 587 ctx, ctx->shader.fs, &ctx->constant_buffer[PIPE_SHADER_FRAGMENT], 588 ctx->shader_state.PS_UNIFORMS, &ctx->shader_state.ps_uniforms_size); 589 590 /**** Large dynamically-sized state ****/ 591 bool do_uniform_flush = ctx->specs.halti < 5; 592 if (dirty & (ETNA_DIRTY_SHADER)) { 593 /* Special case: a new shader was loaded; simply re-load all uniforms and 594 * shader code at once */ 595 /* This sequence is special, do not change ordering unless necessary. According to comment 596 snippets in the Vivante kernel driver a process called "steering" goes on while programming 597 shader state. This (as I understand it) means certain unified states are "steered" 598 toward a specific shader unit (VS/PS/...) based on either explicit flags in register 599 00860, or what other state is written before "auto-steering". So this means some 600 state can legitimately be programmed multiple times. 601 */ 602 603 if (ctx->specs.halti >= 5) { /* ICACHE (HALTI5) */ 604 assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo); 605 /* Set icache (VS) */ 606 etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0); 607 etna_set_state(stream, VIVS_VS_NEWRANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4); 608 assert(ctx->shader_state.VS_INST_ADDR.bo); 609 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR); 610 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002); 611 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE); 612 etna_set_state(stream, VIVS_VS_ICACHE_COUNT, ctx->shader_state.vs_inst_mem_size / 4 - 1); 613 614 /* Set icache (PS) */ 615 etna_set_state(stream, VIVS_PS_NEWRANGE_LOW, 0); 616 etna_set_state(stream, VIVS_PS_NEWRANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4); 617 assert(ctx->shader_state.PS_INST_ADDR.bo); 618 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR); 619 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002); 620 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE); 621 etna_set_state(stream, VIVS_PS_ICACHE_COUNT, ctx->shader_state.ps_inst_mem_size / 4 - 1); 622 623 } else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) { 624 /* ICACHE (pre-HALTI5) */ 625 assert(ctx->specs.has_icache && ctx->specs.has_shader_range_registers); 626 /* Set icache (VS) */ 627 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16); 628 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, 629 VIVS_VS_ICACHE_CONTROL_ENABLE | 630 VIVS_VS_ICACHE_CONTROL_FLUSH_VS); 631 assert(ctx->shader_state.VS_INST_ADDR.bo); 632 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR); 633 634 /* Set icache (PS) */ 635 etna_set_state(stream, VIVS_PS_RANGE, (ctx->shader_state.ps_inst_mem_size / 4 - 1) << 16); 636 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, 637 VIVS_VS_ICACHE_CONTROL_ENABLE | 638 VIVS_VS_ICACHE_CONTROL_FLUSH_PS); 639 assert(ctx->shader_state.PS_INST_ADDR.bo); 640 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR); 641 } else { 642 /* Upload shader directly, first flushing and disabling icache if 643 * supported on this hw */ 644 if (ctx->specs.has_icache) { 645 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, 646 VIVS_VS_ICACHE_CONTROL_FLUSH_PS | 647 VIVS_VS_ICACHE_CONTROL_FLUSH_VS); 648 } 649 if (ctx->specs.has_shader_range_registers) { 650 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16); 651 etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) | 652 0x100); 653 } 654 etna_set_state_multi(stream, ctx->specs.vs_offset, 655 ctx->shader_state.vs_inst_mem_size, 656 ctx->shader_state.VS_INST_MEM); 657 etna_set_state_multi(stream, ctx->specs.ps_offset, 658 ctx->shader_state.ps_inst_mem_size, 659 ctx->shader_state.PS_INST_MEM); 660 } 661 662 if (ctx->specs.has_unified_uniforms) { 663 etna_set_state(stream, VIVS_VS_UNIFORM_BASE, 0); 664 etna_set_state(stream, VIVS_PS_UNIFORM_BASE, ctx->specs.max_vs_uniforms); 665 } 666 667 if (do_uniform_flush) 668 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH); 669 etna_set_state_multi(stream, ctx->specs.vs_uniforms_offset, 670 ctx->shader_state.vs_uniforms_size, 671 ctx->shader_state.VS_UNIFORMS); 672 if (do_uniform_flush) 673 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS); 674 etna_set_state_multi(stream, ctx->specs.ps_uniforms_offset, 675 ctx->shader_state.ps_uniforms_size, 676 ctx->shader_state.PS_UNIFORMS); 677 678 /* Copy uniforms to gpu3d, so that incremental updates to uniforms are 679 * possible as long as the 680 * same shader remains bound */ 681 memcpy(ctx->gpu3d.VS_UNIFORMS, ctx->shader_state.VS_UNIFORMS, 682 ctx->shader_state.vs_uniforms_size * 4); 683 memcpy(ctx->gpu3d.PS_UNIFORMS, ctx->shader_state.PS_UNIFORMS, 684 ctx->shader_state.ps_uniforms_size * 4); 685 686 if (ctx->specs.halti >= 5) { 687 /* HALTI5 needs to be prompted to pre-fetch shaders */ 688 etna_set_state(stream, VIVS_VS_ICACHE_PREFETCH, 0x00000000); 689 etna_set_state(stream, VIVS_PS_ICACHE_PREFETCH, 0x00000000); 690 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE); 691 } 692 } else { 693 /* ideally this cache would only be flushed if there are VS uniform changes */ 694 if (do_uniform_flush) 695 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH); 696 etna_coalesce_start(stream, &coalesce); 697 for (int x = 0; x < ctx->shader.vs->uniforms.const_count; ++x) { 698 if (ctx->gpu3d.VS_UNIFORMS[x] != ctx->shader_state.VS_UNIFORMS[x]) { 699 etna_coalsence_emit(stream, &coalesce, ctx->specs.vs_uniforms_offset + x*4, ctx->shader_state.VS_UNIFORMS[x]); 700 ctx->gpu3d.VS_UNIFORMS[x] = ctx->shader_state.VS_UNIFORMS[x]; 701 } 702 } 703 etna_coalesce_end(stream, &coalesce); 704 705 /* ideally this cache would only be flushed if there are PS uniform changes */ 706 if (do_uniform_flush) 707 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS); 708 etna_coalesce_start(stream, &coalesce); 709 for (int x = 0; x < ctx->shader.fs->uniforms.const_count; ++x) { 710 if (ctx->gpu3d.PS_UNIFORMS[x] != ctx->shader_state.PS_UNIFORMS[x]) { 711 etna_coalsence_emit(stream, &coalesce, ctx->specs.ps_uniforms_offset + x*4, ctx->shader_state.PS_UNIFORMS[x]); 712 ctx->gpu3d.PS_UNIFORMS[x] = ctx->shader_state.PS_UNIFORMS[x]; 713 } 714 } 715 etna_coalesce_end(stream, &coalesce); 716 } 717/**** End of state update ****/ 718#undef EMIT_STATE 719#undef EMIT_STATE_FIXP 720#undef EMIT_STATE_RELOC 721 ctx->dirty = 0; 722 ctx->dirty_sampler_views = 0; 723} 724