1b8e80941Smrg/*
2b8e80941Smrg * Copyright (c) 2012-2013 Etnaviv Project
3b8e80941Smrg *
4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5b8e80941Smrg * copy of this software and associated documentation files (the "Software"),
6b8e80941Smrg * to deal in the Software without restriction, including without limitation
7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sub license,
8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the
9b8e80941Smrg * Software is furnished to do so, subject to the following conditions:
10b8e80941Smrg *
11b8e80941Smrg * The above copyright notice and this permission notice (including the
12b8e80941Smrg * next paragraph) shall be included in all copies or substantial portions
13b8e80941Smrg * of the Software.
14b8e80941Smrg *
15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21b8e80941Smrg * DEALINGS IN THE SOFTWARE.
22b8e80941Smrg *
23b8e80941Smrg * Authors:
24b8e80941Smrg *    Wladimir J. van der Laan <laanwj@gmail.com>
25b8e80941Smrg */
26b8e80941Smrg
27b8e80941Smrg#include "etnaviv_surface.h"
28b8e80941Smrg#include "etnaviv_screen.h"
29b8e80941Smrg
30b8e80941Smrg#include "etnaviv_clear_blit.h"
31b8e80941Smrg#include "etnaviv_context.h"
32b8e80941Smrg#include "etnaviv_translate.h"
33b8e80941Smrg#include "pipe/p_defines.h"
34b8e80941Smrg#include "pipe/p_state.h"
35b8e80941Smrg#include "util/u_inlines.h"
36b8e80941Smrg#include "util/u_memory.h"
37b8e80941Smrg
38b8e80941Smrg#include "hw/common.xml.h"
39b8e80941Smrg
40b8e80941Smrgstatic struct pipe_surface *
41b8e80941Smrgetna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
42b8e80941Smrg                    const struct pipe_surface *templat)
43b8e80941Smrg{
44b8e80941Smrg   struct etna_context *ctx = etna_context(pctx);
45b8e80941Smrg   struct etna_resource *rsc = etna_resource(prsc);
46b8e80941Smrg   struct etna_surface *surf = CALLOC_STRUCT(etna_surface);
47b8e80941Smrg
48b8e80941Smrg   if (!surf)
49b8e80941Smrg      return NULL;
50b8e80941Smrg
51b8e80941Smrg   assert(templat->u.tex.first_layer == templat->u.tex.last_layer);
52b8e80941Smrg   unsigned layer = templat->u.tex.first_layer;
53b8e80941Smrg   unsigned level = templat->u.tex.level;
54b8e80941Smrg   assert(layer < rsc->base.array_size);
55b8e80941Smrg
56b8e80941Smrg   surf->base.context = pctx;
57b8e80941Smrg
58b8e80941Smrg   pipe_reference_init(&surf->base.reference, 1);
59b8e80941Smrg   pipe_resource_reference(&surf->base.texture, &rsc->base);
60b8e80941Smrg
61b8e80941Smrg   /* Allocate a TS for the resource if there isn't one yet,
62b8e80941Smrg    * and it is allowed by the hw (width is a multiple of 16).
63b8e80941Smrg    * Avoid doing this for GPUs with MC1.0, as kernel sources
64b8e80941Smrg    * indicate the tile status module bypasses the memory
65b8e80941Smrg    * offset and MMU. */
66b8e80941Smrg
67b8e80941Smrg   if (VIV_FEATURE(ctx->screen, chipFeatures, FAST_CLEAR) &&
68b8e80941Smrg       VIV_FEATURE(ctx->screen, chipMinorFeatures0, MC20) &&
69b8e80941Smrg       !rsc->ts_bo &&
70b8e80941Smrg       (rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
71b8e80941Smrg       (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0) {
72b8e80941Smrg      etna_screen_resource_alloc_ts(pctx->screen, rsc);
73b8e80941Smrg   }
74b8e80941Smrg
75b8e80941Smrg   surf->base.texture = &rsc->base;
76b8e80941Smrg   surf->base.format = rsc->base.format;
77b8e80941Smrg   surf->base.width = rsc->levels[level].width;
78b8e80941Smrg   surf->base.height = rsc->levels[level].height;
79b8e80941Smrg   surf->base.writable = templat->writable; /* what is this for anyway */
80b8e80941Smrg   surf->base.u = templat->u;
81b8e80941Smrg
82b8e80941Smrg   surf->level = &rsc->levels[level]; /* Keep pointer to actual level to set
83b8e80941Smrg                                       * clear color on underlying resource
84b8e80941Smrg                                       * instead of surface */
85b8e80941Smrg   surf->surf = rsc->levels [level];  /* Make copy of level to narrow down
86b8e80941Smrg                                       * address to layer */
87b8e80941Smrg
88b8e80941Smrg   /* XXX we don't really need a copy but it's convenient */
89b8e80941Smrg   surf->surf.offset += layer * surf->surf.layer_stride;
90b8e80941Smrg
91b8e80941Smrg   struct etna_resource_level *lev = &rsc->levels[level];
92b8e80941Smrg
93b8e80941Smrg   /* Setup template relocations for this surface */
94b8e80941Smrg   for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) {
95b8e80941Smrg      surf->reloc[pipe].bo = rsc->bo;
96b8e80941Smrg      surf->reloc[pipe].offset = surf->surf.offset;
97b8e80941Smrg      surf->reloc[pipe].flags = 0;
98b8e80941Smrg   }
99b8e80941Smrg
100b8e80941Smrg   /* In single buffer mode, both pixel pipes must point to the same address,
101b8e80941Smrg    * for multi-tiled surfaces on the other hand the second pipe is expected to
102b8e80941Smrg    * point halfway the image vertically.
103b8e80941Smrg    */
104b8e80941Smrg   if (rsc->layout & ETNA_LAYOUT_BIT_MULTI)
105b8e80941Smrg      surf->reloc[1].offset = surf->surf.offset + lev->stride * lev->padded_height / 2;
106b8e80941Smrg
107b8e80941Smrg   if (surf->surf.ts_size) {
108b8e80941Smrg      unsigned int layer_offset = layer * surf->surf.ts_layer_stride;
109b8e80941Smrg      assert(layer_offset < surf->surf.ts_size);
110b8e80941Smrg
111b8e80941Smrg      surf->surf.ts_offset += layer_offset;
112b8e80941Smrg      surf->surf.ts_size -= layer_offset;
113b8e80941Smrg      surf->surf.ts_valid = false;
114b8e80941Smrg
115b8e80941Smrg      surf->ts_reloc.bo = rsc->ts_bo;
116b8e80941Smrg      surf->ts_reloc.offset = surf->surf.ts_offset;
117b8e80941Smrg      surf->ts_reloc.flags = 0;
118b8e80941Smrg
119b8e80941Smrg      if (!ctx->specs.use_blt) {
120b8e80941Smrg         /* This (ab)uses the RS as a plain buffer memset().
121b8e80941Smrg          * Currently uses a fixed row size of 64 bytes. Some benchmarking with
122b8e80941Smrg          * different sizes may be in order. */
123b8e80941Smrg         struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
124b8e80941Smrg         etna_compile_rs_state(ctx, &surf->clear_command, &(struct rs_state) {
125b8e80941Smrg            .source_format = RS_FORMAT_A8R8G8B8,
126b8e80941Smrg            .dest_format = RS_FORMAT_A8R8G8B8,
127b8e80941Smrg            .dest = ts_bo,
128b8e80941Smrg            .dest_offset = surf->surf.ts_offset,
129b8e80941Smrg            .dest_stride = 0x40,
130b8e80941Smrg            .dest_tiling = ETNA_LAYOUT_TILED,
131b8e80941Smrg            .dither = {0xffffffff, 0xffffffff},
132b8e80941Smrg            .width = 16,
133b8e80941Smrg            .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
134b8e80941Smrg            .clear_value = {ctx->specs.ts_clear_value},
135b8e80941Smrg            .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
136b8e80941Smrg            .clear_bits = 0xffff
137b8e80941Smrg         });
138b8e80941Smrg      }
139b8e80941Smrg   } else {
140b8e80941Smrg      if (!ctx->specs.use_blt)
141b8e80941Smrg         etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
142b8e80941Smrg   }
143b8e80941Smrg
144b8e80941Smrg   return &surf->base;
145b8e80941Smrg}
146b8e80941Smrg
147b8e80941Smrgstatic void
148b8e80941Smrgetna_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf)
149b8e80941Smrg{
150b8e80941Smrg   pipe_resource_reference(&psurf->texture, NULL);
151b8e80941Smrg   FREE(psurf);
152b8e80941Smrg}
153b8e80941Smrg
154b8e80941Smrgvoid
155b8e80941Smrgetna_surface_init(struct pipe_context *pctx)
156b8e80941Smrg{
157b8e80941Smrg   pctx->create_surface = etna_create_surface;
158b8e80941Smrg   pctx->surface_destroy = etna_surface_destroy;
159b8e80941Smrg}
160