1/* 2 * Copyright (C) 2019 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include "pipe/p_state.h" 28 29#include "freedreno_resource.h" 30 31#include "fd6_compute.h" 32#include "fd6_context.h" 33#include "fd6_emit.h" 34 35struct fd6_compute_stateobj { 36 struct ir3_shader *shader; 37}; 38 39 40static void * 41fd6_create_compute_state(struct pipe_context *pctx, 42 const struct pipe_compute_state *cso) 43{ 44 struct fd_context *ctx = fd_context(pctx); 45 46 /* req_input_mem will only be non-zero for cl kernels (ie. clover). 47 * This isn't a perfect test because I guess it is possible (but 48 * uncommon) for none for the kernel parameters to be a global, 49 * but ctx->set_global_bindings() can't fail, so this is the next 50 * best place to fail if we need a newer version of kernel driver: 51 */ 52 if ((cso->req_input_mem > 0) && 53 fd_device_version(ctx->dev) < FD_VERSION_BO_IOVA) { 54 return NULL; 55 } 56 57 struct ir3_compiler *compiler = ctx->screen->compiler; 58 struct fd6_compute_stateobj *so = CALLOC_STRUCT(fd6_compute_stateobj); 59 so->shader = ir3_shader_create_compute(compiler, cso, &ctx->debug, pctx->screen); 60 return so; 61} 62 63static void 64fd6_delete_compute_state(struct pipe_context *pctx, void *hwcso) 65{ 66 struct fd6_compute_stateobj *so = hwcso; 67 ir3_shader_destroy(so->shader); 68 free(so); 69} 70 71/* maybe move to fd6_program? */ 72static void 73cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v, 74 const struct pipe_grid_info *info) 75{ 76 const struct ir3_info *i = &v->info; 77 enum a3xx_threadsize thrsz = FOUR_QUADS; 78 79 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1); 80 OUT_RING(ring, 0xff); 81 82 unsigned constlen = align(v->constlen, 4); 83 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1); 84 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) | 85 A6XX_HLSQ_CS_CNTL_ENABLED); 86 87 OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2); 88 OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED | 89 A6XX_SP_CS_CONFIG_NIBO(v->image_mapping.num_ibo) | 90 A6XX_SP_CS_CONFIG_NTEX(v->num_samp) | 91 A6XX_SP_CS_CONFIG_NSAMP(v->num_samp)); /* SP_VS_CONFIG */ 92 OUT_RING(ring, v->instrlen); /* SP_VS_INSTRLEN */ 93 94 OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1); 95 OUT_RING(ring, A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) | 96 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) | 97 A6XX_SP_CS_CTRL_REG0_MERGEDREGS | 98 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) | 99 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE)); 100 101 OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1); 102 OUT_RING(ring, 0x41); 103 104 uint32_t local_invocation_id, work_group_id; 105 local_invocation_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID); 106 work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID); 107 108 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2); 109 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) | 110 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) | 111 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) | 112 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id)); 113 OUT_RING(ring, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */ 114 115 OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2); 116 OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */ 117 118 if (v->instrlen > 0) 119 fd6_emit_shader(ring, v); 120} 121 122static void 123fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) 124{ 125 struct fd6_compute_stateobj *so = ctx->compute; 126 struct ir3_shader_key key = {}; 127 struct ir3_shader_variant *v; 128 struct fd_ringbuffer *ring = ctx->batch->draw; 129 unsigned i, nglobal = 0; 130 131 fd6_emit_restore(ctx->batch, ring); 132 133 v = ir3_shader_variant(so->shader, key, false, &ctx->debug); 134 if (!v) 135 return; 136 137 if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG) 138 cs_program_emit(ring, v, info); 139 140 fd6_emit_cs_state(ctx, ring, v); 141 ir3_emit_cs_consts(v, ring, ctx, info); 142 143 foreach_bit(i, ctx->global_bindings.enabled_mask) 144 nglobal++; 145 146 if (nglobal > 0) { 147 /* global resources don't otherwise get an OUT_RELOC(), since 148 * the raw ptr address is emitted in ir3_emit_cs_consts(). 149 * So to make the kernel aware that these buffers are referenced 150 * by the batch, emit dummy reloc's as part of a no-op packet 151 * payload: 152 */ 153 OUT_PKT7(ring, CP_NOP, 2 * nglobal); 154 foreach_bit(i, ctx->global_bindings.enabled_mask) { 155 struct pipe_resource *prsc = ctx->global_bindings.buf[i]; 156 OUT_RELOCW(ring, fd_resource(prsc)->bo, 0, 0, 0); 157 } 158 } 159 160 OUT_PKT7(ring, CP_SET_MARKER, 1); 161 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x8)); 162 163 const unsigned *local_size = info->block; // v->shader->nir->info->cs.local_size; 164 const unsigned *num_groups = info->grid; 165 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */ 166 const unsigned work_dim = info->work_dim ? info->work_dim : 3; 167 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_NDRANGE_0, 7); 168 OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) | 169 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) | 170 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) | 171 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1)); 172 OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0])); 173 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */ 174 OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1])); 175 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */ 176 OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2])); 177 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */ 178 179 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3); 180 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_X */ 181 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Y */ 182 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Z */ 183 184 if (info->indirect) { 185 struct fd_resource *rsc = fd_resource(info->indirect); 186 187 OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4); 188 OUT_RING(ring, 0x00000000); 189 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ 190 OUT_RING(ring, A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) | 191 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) | 192 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1)); 193 } else { 194 OUT_PKT7(ring, CP_EXEC_CS, 4); 195 OUT_RING(ring, 0x00000000); 196 OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0])); 197 OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1])); 198 OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2])); 199 } 200 201 OUT_WFI5(ring); 202 203 fd6_cache_flush(ctx->batch, ring); 204} 205 206void 207fd6_compute_init(struct pipe_context *pctx) 208{ 209 struct fd_context *ctx = fd_context(pctx); 210 ctx->launch_grid = fd6_launch_grid; 211 pctx->create_compute_state = fd6_create_compute_state; 212 pctx->delete_compute_state = fd6_delete_compute_state; 213} 214