1/*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 *    Rob Clark <robclark@freedesktop.org>
26 */
27
28
29#include "pipe/p_state.h"
30#include "util/u_string.h"
31#include "util/u_memory.h"
32
33#include "fd6_zsa.h"
34#include "fd6_context.h"
35#include "fd6_format.h"
36
37void *
38fd6_zsa_state_create(struct pipe_context *pctx,
39		const struct pipe_depth_stencil_alpha_state *cso)
40{
41	struct fd_context *ctx = fd_context(pctx);
42	struct fd6_zsa_stateobj *so;
43
44	so = CALLOC_STRUCT(fd6_zsa_stateobj);
45	if (!so)
46		return NULL;
47
48	so->base = *cso;
49
50	switch (cso->depth.func) {
51	case PIPE_FUNC_LESS:
52	case PIPE_FUNC_LEQUAL:
53		so->gras_lrz_cntl = A6XX_GRAS_LRZ_CNTL_ENABLE;
54		so->rb_lrz_cntl = A6XX_RB_LRZ_CNTL_ENABLE;
55		break;
56
57	case PIPE_FUNC_GREATER:
58	case PIPE_FUNC_GEQUAL:
59		so->gras_lrz_cntl = A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_GREATER;
60		so->rb_lrz_cntl = A6XX_RB_LRZ_CNTL_ENABLE;
61		break;
62
63	default:
64		/* LRZ not enabled */
65		so->gras_lrz_cntl = 0;
66		break;
67	}
68
69	if (cso->depth.writemask) {
70		if (cso->depth.enabled)
71			so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_UNK4;
72		so->lrz_write = true;
73	}
74
75	so->rb_depth_cntl |=
76		A6XX_RB_DEPTH_CNTL_ZFUNC(cso->depth.func); /* maps 1:1 */
77
78	if (cso->depth.enabled)
79		so->rb_depth_cntl |=
80			A6XX_RB_DEPTH_CNTL_Z_ENABLE |
81			A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
82
83	if (cso->depth.writemask)
84		so->rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
85
86	if (cso->stencil[0].enabled) {
87		const struct pipe_stencil_state *s = &cso->stencil[0];
88
89		so->rb_stencil_control |=
90			A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
91			A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
92			A6XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
93			A6XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
94			A6XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
95			A6XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
96
97		so->rb_stencilmask = A6XX_RB_STENCILMASK_MASK(s->valuemask);
98		so->rb_stencilwrmask = A6XX_RB_STENCILWRMASK_WRMASK(s->writemask);
99
100		if (cso->stencil[1].enabled) {
101			const struct pipe_stencil_state *bs = &cso->stencil[1];
102
103			so->rb_stencil_control |=
104				A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
105				A6XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
106				A6XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
107				A6XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
108				A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
109
110			so->rb_stencilmask |= A6XX_RB_STENCILMASK_BFMASK(bs->valuemask);
111			so->rb_stencilwrmask |= A6XX_RB_STENCILWRMASK_BFWRMASK(bs->writemask);
112		}
113	}
114
115	if (cso->alpha.enabled) {
116		uint32_t ref = cso->alpha.ref_value * 255.0;
117		so->rb_alpha_control =
118			A6XX_RB_ALPHA_CONTROL_ALPHA_TEST |
119			A6XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |
120			A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha.func);
121//		so->rb_depth_control |=
122//			A6XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
123	}
124
125	so->stateobj = fd_ringbuffer_new_object(ctx->pipe, 9 * 4);
126	struct fd_ringbuffer *ring = so->stateobj;
127
128	OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
129	OUT_RING(ring, so->rb_alpha_control);
130
131	OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
132	OUT_RING(ring, so->rb_stencil_control);
133
134	OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
135	OUT_RING(ring, so->rb_depth_cntl);
136
137	OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
138	OUT_RING(ring, so->rb_stencilmask);
139	OUT_RING(ring, so->rb_stencilwrmask);
140
141	so->stateobj_no_alpha = fd_ringbuffer_new_object(ctx->pipe, 9 * 4);
142	ring = so->stateobj_no_alpha;
143
144	OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
145	OUT_RING(ring, so->rb_alpha_control & ~A6XX_RB_ALPHA_CONTROL_ALPHA_TEST);
146
147	OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
148	OUT_RING(ring, so->rb_stencil_control);
149
150	OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
151	OUT_RING(ring, so->rb_depth_cntl);
152
153	OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
154	OUT_RING(ring, so->rb_stencilmask);
155	OUT_RING(ring, so->rb_stencilwrmask);
156
157	return so;
158}
159
160void
161fd6_depth_stencil_alpha_state_delete(struct pipe_context *pctx, void *hwcso)
162{
163	struct fd6_zsa_stateobj *so = hwcso;
164
165	fd_ringbuffer_del(so->stateobj);
166	fd_ringbuffer_del(so->stateobj_no_alpha);
167	FREE(hwcso);
168}
169