1848b8605Smrg/*
2848b8605Smrg * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3848b8605Smrg *
4848b8605Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5848b8605Smrg * copy of this software and associated documentation files (the "Software"),
6848b8605Smrg * to deal in the Software without restriction, including without limitation
7848b8605Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8848b8605Smrg * and/or sell copies of the Software, and to permit persons to whom the
9848b8605Smrg * Software is furnished to do so, subject to the following conditions:
10848b8605Smrg *
11848b8605Smrg * The above copyright notice and this permission notice (including the next
12848b8605Smrg * paragraph) shall be included in all copies or substantial portions of the
13848b8605Smrg * Software.
14848b8605Smrg *
15848b8605Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16848b8605Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17848b8605Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18848b8605Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19848b8605Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20848b8605Smrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21848b8605Smrg * SOFTWARE.
22848b8605Smrg *
23848b8605Smrg * Authors:
24848b8605Smrg *    Rob Clark <robclark@freedesktop.org>
25848b8605Smrg */
26848b8605Smrg
27848b8605Smrg#ifndef FREEDRENO_CONTEXT_H_
28848b8605Smrg#define FREEDRENO_CONTEXT_H_
29848b8605Smrg
30848b8605Smrg#include "pipe/p_context.h"
31848b8605Smrg#include "indices/u_primconvert.h"
32848b8605Smrg#include "util/u_blitter.h"
33b8e80941Smrg#include "util/list.h"
34b8e80941Smrg#include "util/slab.h"
35848b8605Smrg#include "util/u_string.h"
36848b8605Smrg
37b8e80941Smrg#include "freedreno_batch.h"
38848b8605Smrg#include "freedreno_screen.h"
39848b8605Smrg#include "freedreno_gmem.h"
40848b8605Smrg#include "freedreno_util.h"
41848b8605Smrg
42b8e80941Smrg#define BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE)
43b8e80941Smrg
44848b8605Smrgstruct fd_vertex_stateobj;
45848b8605Smrg
46848b8605Smrgstruct fd_texture_stateobj {
47848b8605Smrg	struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
48848b8605Smrg	unsigned num_textures;
49b8e80941Smrg	unsigned valid_textures;
50848b8605Smrg	struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
51848b8605Smrg	unsigned num_samplers;
52b8e80941Smrg	unsigned valid_samplers;
53b8e80941Smrg	/* number of samples per sampler, 2 bits per sampler: */
54b8e80941Smrg	uint32_t samples;
55848b8605Smrg};
56848b8605Smrg
57848b8605Smrgstruct fd_program_stateobj {
58848b8605Smrg	void *vp, *fp;
59848b8605Smrg};
60848b8605Smrg
61848b8605Smrgstruct fd_constbuf_stateobj {
62848b8605Smrg	struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
63848b8605Smrg	uint32_t enabled_mask;
64b8e80941Smrg};
65b8e80941Smrg
66b8e80941Smrgstruct fd_shaderbuf_stateobj {
67b8e80941Smrg	struct pipe_shader_buffer sb[PIPE_MAX_SHADER_BUFFERS];
68b8e80941Smrg	uint32_t enabled_mask;
69b8e80941Smrg};
70b8e80941Smrg
71b8e80941Smrgstruct fd_shaderimg_stateobj {
72b8e80941Smrg	struct pipe_image_view si[PIPE_MAX_SHADER_IMAGES];
73b8e80941Smrg	uint32_t enabled_mask;
74848b8605Smrg};
75848b8605Smrg
76848b8605Smrgstruct fd_vertexbuf_stateobj {
77848b8605Smrg	struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
78848b8605Smrg	unsigned count;
79848b8605Smrg	uint32_t enabled_mask;
80848b8605Smrg};
81848b8605Smrg
82848b8605Smrgstruct fd_vertex_stateobj {
83848b8605Smrg	struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
84848b8605Smrg	unsigned num_elements;
85848b8605Smrg};
86848b8605Smrg
87b8e80941Smrgstruct fd_streamout_stateobj {
88b8e80941Smrg	struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
89b8e80941Smrg	unsigned num_targets;
90b8e80941Smrg	/* Track offset from vtxcnt for streamout data.  This counter
91b8e80941Smrg	 * is just incremented by # of vertices on each draw until
92b8e80941Smrg	 * reset or new streamout buffer bound.
93b8e80941Smrg	 *
94b8e80941Smrg	 * When we eventually have GS, the CPU won't actually know the
95b8e80941Smrg	 * number of vertices per draw, so I think we'll have to do
96b8e80941Smrg	 * something more clever.
97b8e80941Smrg	 */
98b8e80941Smrg	unsigned offsets[PIPE_MAX_SO_BUFFERS];
99b8e80941Smrg};
100b8e80941Smrg
101b8e80941Smrg#define MAX_GLOBAL_BUFFERS 16
102b8e80941Smrgstruct fd_global_bindings_stateobj {
103b8e80941Smrg	struct pipe_resource *buf[MAX_GLOBAL_BUFFERS];
104b8e80941Smrg	uint32_t enabled_mask;
105b8e80941Smrg};
106b8e80941Smrg
107848b8605Smrg/* group together the vertex and vertexbuf state.. for ease of passing
108848b8605Smrg * around, and because various internal operations (gmem<->mem, etc)
109848b8605Smrg * need their own vertex state:
110848b8605Smrg */
111848b8605Smrgstruct fd_vertex_state {
112848b8605Smrg	struct fd_vertex_stateobj *vtx;
113848b8605Smrg	struct fd_vertexbuf_stateobj vertexbuf;
114848b8605Smrg};
115848b8605Smrg
116b8e80941Smrg/* global 3d pipeline dirty state: */
117b8e80941Smrgenum fd_dirty_3d_state {
118b8e80941Smrg	FD_DIRTY_BLEND       = BIT(0),
119b8e80941Smrg	FD_DIRTY_RASTERIZER  = BIT(1),
120b8e80941Smrg	FD_DIRTY_ZSA         = BIT(2),
121b8e80941Smrg	FD_DIRTY_BLEND_COLOR = BIT(3),
122b8e80941Smrg	FD_DIRTY_STENCIL_REF = BIT(4),
123b8e80941Smrg	FD_DIRTY_SAMPLE_MASK = BIT(5),
124b8e80941Smrg	FD_DIRTY_FRAMEBUFFER = BIT(6),
125b8e80941Smrg	FD_DIRTY_STIPPLE     = BIT(7),
126b8e80941Smrg	FD_DIRTY_VIEWPORT    = BIT(8),
127b8e80941Smrg	FD_DIRTY_VTXSTATE    = BIT(9),
128b8e80941Smrg	FD_DIRTY_VTXBUF      = BIT(10),
129b8e80941Smrg	FD_DIRTY_MIN_SAMPLES = BIT(11),
130b8e80941Smrg
131b8e80941Smrg	FD_DIRTY_SCISSOR     = BIT(12),
132b8e80941Smrg	FD_DIRTY_STREAMOUT   = BIT(13),
133b8e80941Smrg	FD_DIRTY_UCP         = BIT(14),
134b8e80941Smrg	FD_DIRTY_BLEND_DUAL  = BIT(15),
135b8e80941Smrg
136b8e80941Smrg	/* These are a bit redundent with fd_dirty_shader_state, and possibly
137b8e80941Smrg	 * should be removed.  (But OTOH kinda convenient in some places)
138848b8605Smrg	 */
139b8e80941Smrg	FD_DIRTY_PROG        = BIT(16),
140b8e80941Smrg	FD_DIRTY_CONST       = BIT(17),
141b8e80941Smrg	FD_DIRTY_TEX         = BIT(18),
142b8e80941Smrg
143b8e80941Smrg	/* only used by a2xx.. possibly can be removed.. */
144b8e80941Smrg	FD_DIRTY_TEXSTATE    = BIT(19),
145848b8605Smrg};
146848b8605Smrg
147b8e80941Smrg/* per shader-stage dirty state: */
148b8e80941Smrgenum fd_dirty_shader_state {
149b8e80941Smrg	FD_DIRTY_SHADER_PROG  = BIT(0),
150b8e80941Smrg	FD_DIRTY_SHADER_CONST = BIT(1),
151b8e80941Smrg	FD_DIRTY_SHADER_TEX   = BIT(2),
152b8e80941Smrg	FD_DIRTY_SHADER_SSBO  = BIT(3),
153b8e80941Smrg	FD_DIRTY_SHADER_IMAGE = BIT(4),
154b8e80941Smrg};
155848b8605Smrg
156848b8605Smrgstruct fd_context {
157848b8605Smrg	struct pipe_context base;
158848b8605Smrg
159848b8605Smrg	struct fd_device *dev;
160848b8605Smrg	struct fd_screen *screen;
161b8e80941Smrg	struct fd_pipe *pipe;
162b8e80941Smrg
163b8e80941Smrg	struct util_queue flush_queue;
164848b8605Smrg
165848b8605Smrg	struct blitter_context *blitter;
166b8e80941Smrg	void *clear_rs_state;
167848b8605Smrg	struct primconvert_context *primconvert;
168848b8605Smrg
169848b8605Smrg	/* slab for pipe_transfer allocations: */
170b8e80941Smrg	struct slab_child_pool transfer_pool;
171848b8605Smrg
172b8e80941Smrg	/**
173b8e80941Smrg	 * query related state:
174848b8605Smrg	 */
175b8e80941Smrg	/*@{*/
176b8e80941Smrg	/* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
177b8e80941Smrg	struct slab_mempool sample_pool;
178b8e80941Smrg	struct slab_mempool sample_period_pool;
179848b8605Smrg
180848b8605Smrg	/* sample-providers for hw queries: */
181b8e80941Smrg	const struct fd_hw_sample_provider *hw_sample_providers[MAX_HW_SAMPLE_PROVIDERS];
182848b8605Smrg
183848b8605Smrg	/* list of active queries: */
184b8e80941Smrg	struct list_head hw_active_queries;
185848b8605Smrg
186b8e80941Smrg	/* sample-providers for accumulating hw queries: */
187b8e80941Smrg	const struct fd_acc_sample_provider *acc_sample_providers[MAX_HW_SAMPLE_PROVIDERS];
188848b8605Smrg
189b8e80941Smrg	/* list of active accumulating queries: */
190b8e80941Smrg	struct list_head acc_active_queries;
191b8e80941Smrg	/*@}*/
192848b8605Smrg
193848b8605Smrg	/* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
194848b8605Smrg	 * DI_PT_x value to use for draw initiator.  There are some
195848b8605Smrg	 * slight differences between generation:
196848b8605Smrg	 */
197848b8605Smrg	const uint8_t *primtypes;
198848b8605Smrg	uint32_t primtype_mask;
199848b8605Smrg
200848b8605Smrg	/* shaders used by clear, and gmem->mem blits: */
201848b8605Smrg	struct fd_program_stateobj solid_prog; // TODO move to screen?
202848b8605Smrg
203848b8605Smrg	/* shaders used by mem->gmem blits: */
204b8e80941Smrg	struct fd_program_stateobj blit_prog[MAX_RENDER_TARGETS]; // TODO move to screen?
205b8e80941Smrg	struct fd_program_stateobj blit_z, blit_zs;
206848b8605Smrg
207848b8605Smrg	/* Stats/counters:
208848b8605Smrg	 */
209848b8605Smrg	struct {
210848b8605Smrg		uint64_t prims_emitted;
211b8e80941Smrg		uint64_t prims_generated;
212848b8605Smrg		uint64_t draw_calls;
213b8e80941Smrg		uint64_t batch_total, batch_sysmem, batch_gmem, batch_nondraw, batch_restore;
214b8e80941Smrg		uint64_t staging_uploads, shadow_uploads;
215b8e80941Smrg		uint64_t vs_regs, fs_regs;
216848b8605Smrg	} stats;
217848b8605Smrg
218b8e80941Smrg	/* Current batch.. the rule here is that you can deref ctx->batch
219b8e80941Smrg	 * in codepaths from pipe_context entrypoints.  But not in code-
220b8e80941Smrg	 * paths from fd_batch_flush() (basically, the stuff that gets
221b8e80941Smrg	 * called from GMEM code), since in those code-paths the batch
222b8e80941Smrg	 * you care about is not necessarily the same as ctx->batch.
223848b8605Smrg	 */
224b8e80941Smrg	struct fd_batch *batch;
225848b8605Smrg
226b8e80941Smrg	/* NULL if there has been rendering since last flush.  Otherwise
227b8e80941Smrg	 * keeps a reference to the last fence so we can re-use it rather
228b8e80941Smrg	 * than having to flush no-op batch.
229b8e80941Smrg	 */
230b8e80941Smrg	struct pipe_fence_handle *last_fence;
231848b8605Smrg
232b8e80941Smrg	/* track last known reset status globally and per-context to
233b8e80941Smrg	 * determine if more resets occurred since then.  If global reset
234b8e80941Smrg	 * count increases, it means some other context crashed.  If
235b8e80941Smrg	 * per-context reset count increases, it means we crashed the
236b8e80941Smrg	 * gpu.
237848b8605Smrg	 */
238b8e80941Smrg	uint32_t context_reset_count, global_reset_count;
239848b8605Smrg
240b8e80941Smrg	/* Are we in process of shadowing a resource? Used to detect recursion
241b8e80941Smrg	 * in transfer_map, and skip unneeded synchronization.
242b8e80941Smrg	 */
243b8e80941Smrg	bool in_shadow : 1;
244848b8605Smrg
245b8e80941Smrg	/* Ie. in blit situation where we no longer care about previous framebuffer
246b8e80941Smrg	 * contents.  Main point is to eliminate blits from fd_try_shadow_resource().
247b8e80941Smrg	 * For example, in case of texture upload + gen-mipmaps.
248848b8605Smrg	 */
249b8e80941Smrg	bool in_blit : 1;
250848b8605Smrg
251848b8605Smrg	struct pipe_scissor_state scissor;
252848b8605Smrg
253848b8605Smrg	/* we don't have a disable/enable bit for scissor, so instead we keep
254848b8605Smrg	 * a disabled-scissor state which matches the entire bound framebuffer
255848b8605Smrg	 * and use that when scissor is not enabled.
256848b8605Smrg	 */
257848b8605Smrg	struct pipe_scissor_state disabled_scissor;
258848b8605Smrg
259848b8605Smrg	/* Current gmem/tiling configuration.. gets updated on render_tiles()
260848b8605Smrg	 * if out of date with current maximal-scissor/cpp:
261b8e80941Smrg	 *
262b8e80941Smrg	 * (NOTE: this is kind of related to the batch, but moving it there
263b8e80941Smrg	 * means we'd always have to recalc tiles ever batch)
264848b8605Smrg	 */
265848b8605Smrg	struct fd_gmem_stateobj gmem;
266b8e80941Smrg	struct fd_vsc_pipe      vsc_pipe[32];
267b8e80941Smrg	struct fd_tile          tile[512];
268848b8605Smrg
269848b8605Smrg	/* which state objects need to be re-emit'd: */
270b8e80941Smrg	enum fd_dirty_3d_state dirty;
271b8e80941Smrg
272b8e80941Smrg	/* per shader-stage dirty status: */
273b8e80941Smrg	enum fd_dirty_shader_state dirty_shader[PIPE_SHADER_TYPES];
274848b8605Smrg
275b8e80941Smrg	void *compute;
276848b8605Smrg	struct pipe_blend_state *blend;
277848b8605Smrg	struct pipe_rasterizer_state *rasterizer;
278848b8605Smrg	struct pipe_depth_stencil_alpha_state *zsa;
279848b8605Smrg
280b8e80941Smrg	struct fd_texture_stateobj tex[PIPE_SHADER_TYPES];
281848b8605Smrg
282848b8605Smrg	struct fd_program_stateobj prog;
283848b8605Smrg
284848b8605Smrg	struct fd_vertex_state vtx;
285848b8605Smrg
286848b8605Smrg	struct pipe_blend_color blend_color;
287848b8605Smrg	struct pipe_stencil_ref stencil_ref;
288848b8605Smrg	unsigned sample_mask;
289b8e80941Smrg	unsigned min_samples;
290b8e80941Smrg	/* local context fb state, for when ctx->batch is null: */
291848b8605Smrg	struct pipe_framebuffer_state framebuffer;
292848b8605Smrg	struct pipe_poly_stipple stipple;
293848b8605Smrg	struct pipe_viewport_state viewport;
294b8e80941Smrg	struct pipe_scissor_state viewport_scissor;
295848b8605Smrg	struct fd_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
296b8e80941Smrg	struct fd_shaderbuf_stateobj shaderbuf[PIPE_SHADER_TYPES];
297b8e80941Smrg	struct fd_shaderimg_stateobj shaderimg[PIPE_SHADER_TYPES];
298b8e80941Smrg	struct fd_streamout_stateobj streamout;
299b8e80941Smrg	struct fd_global_bindings_stateobj global_bindings;
300b8e80941Smrg	struct pipe_clip_state ucp;
301b8e80941Smrg
302b8e80941Smrg	struct pipe_query *cond_query;
303b8e80941Smrg	bool cond_cond; /* inverted rendering condition */
304b8e80941Smrg	uint cond_mode;
305b8e80941Smrg
306b8e80941Smrg	struct pipe_debug_callback debug;
307848b8605Smrg
308848b8605Smrg	/* GMEM/tile handling fxns: */
309b8e80941Smrg	void (*emit_tile_init)(struct fd_batch *batch);
310b8e80941Smrg	void (*emit_tile_prep)(struct fd_batch *batch, struct fd_tile *tile);
311b8e80941Smrg	void (*emit_tile_mem2gmem)(struct fd_batch *batch, struct fd_tile *tile);
312b8e80941Smrg	void (*emit_tile_renderprep)(struct fd_batch *batch, struct fd_tile *tile);
313b8e80941Smrg	void (*emit_tile_gmem2mem)(struct fd_batch *batch, struct fd_tile *tile);
314b8e80941Smrg	void (*emit_tile_fini)(struct fd_batch *batch);   /* optional */
315848b8605Smrg
316848b8605Smrg	/* optional, for GMEM bypass: */
317b8e80941Smrg	void (*emit_sysmem_prep)(struct fd_batch *batch);
318b8e80941Smrg	void (*emit_sysmem_fini)(struct fd_batch *batch);
319848b8605Smrg
320848b8605Smrg	/* draw: */
321b8e80941Smrg	bool (*draw_vbo)(struct fd_context *ctx, const struct pipe_draw_info *info,
322b8e80941Smrg			unsigned index_offset);
323b8e80941Smrg	bool (*clear)(struct fd_context *ctx, unsigned buffers,
324848b8605Smrg			const union pipe_color_union *color, double depth, unsigned stencil);
325b8e80941Smrg
326b8e80941Smrg	/* compute: */
327b8e80941Smrg	void (*launch_grid)(struct fd_context *ctx, const struct pipe_grid_info *info);
328b8e80941Smrg
329b8e80941Smrg	/* constant emit:  (note currently not used/needed for a2xx) */
330b8e80941Smrg	void (*emit_const)(struct fd_ringbuffer *ring, gl_shader_stage type,
331b8e80941Smrg			uint32_t regid, uint32_t offset, uint32_t sizedwords,
332b8e80941Smrg			const uint32_t *dwords, struct pipe_resource *prsc);
333b8e80941Smrg	/* emit bo addresses as constant: */
334b8e80941Smrg	void (*emit_const_bo)(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
335b8e80941Smrg			uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets);
336b8e80941Smrg
337b8e80941Smrg	/* indirect-branch emit: */
338b8e80941Smrg	void (*emit_ib)(struct fd_ringbuffer *ring, struct fd_ringbuffer *target);
339b8e80941Smrg
340b8e80941Smrg	/* query: */
341b8e80941Smrg	struct fd_query * (*create_query)(struct fd_context *ctx, unsigned query_type);
342b8e80941Smrg	void (*query_prepare)(struct fd_batch *batch, uint32_t num_tiles);
343b8e80941Smrg	void (*query_prepare_tile)(struct fd_batch *batch, uint32_t n,
344b8e80941Smrg			struct fd_ringbuffer *ring);
345b8e80941Smrg	void (*query_set_stage)(struct fd_batch *batch, enum fd_render_stage stage);
346b8e80941Smrg
347b8e80941Smrg	/* blitter: */
348b8e80941Smrg	bool (*blit)(struct fd_context *ctx, const struct pipe_blit_info *info);
349b8e80941Smrg
350b8e80941Smrg	/* simple gpu "memcpy": */
351b8e80941Smrg	void (*mem_to_mem)(struct fd_ringbuffer *ring, struct pipe_resource *dst,
352b8e80941Smrg			unsigned dst_off, struct pipe_resource *src, unsigned src_off,
353b8e80941Smrg			unsigned sizedwords);
354b8e80941Smrg
355b8e80941Smrg	/* handling for barriers: */
356b8e80941Smrg	void (*framebuffer_barrier)(struct fd_context *ctx);
357b8e80941Smrg
358b8e80941Smrg	/*
359b8e80941Smrg	 * Common pre-cooked VBO state (used for a3xx and later):
360b8e80941Smrg	 */
361b8e80941Smrg
362b8e80941Smrg	/* for clear/gmem->mem vertices, and mem->gmem */
363b8e80941Smrg	struct pipe_resource *solid_vbuf;
364b8e80941Smrg
365b8e80941Smrg	/* for mem->gmem tex coords: */
366b8e80941Smrg	struct pipe_resource *blit_texcoord_vbuf;
367b8e80941Smrg
368b8e80941Smrg	/* vertex state for solid_vbuf:
369b8e80941Smrg	 *    - solid_vbuf / 12 / R32G32B32_FLOAT
370b8e80941Smrg	 */
371b8e80941Smrg	struct fd_vertex_state solid_vbuf_state;
372b8e80941Smrg
373b8e80941Smrg	/* vertex state for blit_prog:
374b8e80941Smrg	 *    - blit_texcoord_vbuf / 8 / R32G32_FLOAT
375b8e80941Smrg	 *    - solid_vbuf / 12 / R32G32B32_FLOAT
376b8e80941Smrg	 */
377b8e80941Smrg	struct fd_vertex_state blit_vbuf_state;
378848b8605Smrg};
379848b8605Smrg
380b8e80941Smrgstatic inline struct fd_context *
381848b8605Smrgfd_context(struct pipe_context *pctx)
382848b8605Smrg{
383848b8605Smrg	return (struct fd_context *)pctx;
384848b8605Smrg}
385848b8605Smrg
386b8e80941Smrgstatic inline void
387b8e80941Smrgfd_context_assert_locked(struct fd_context *ctx)
388b8e80941Smrg{
389b8e80941Smrg	pipe_mutex_assert_locked(ctx->screen->lock);
390b8e80941Smrg}
391b8e80941Smrg
392b8e80941Smrgstatic inline void
393b8e80941Smrgfd_context_lock(struct fd_context *ctx)
394b8e80941Smrg{
395b8e80941Smrg	mtx_lock(&ctx->screen->lock);
396b8e80941Smrg}
397b8e80941Smrg
398b8e80941Smrgstatic inline void
399b8e80941Smrgfd_context_unlock(struct fd_context *ctx)
400b8e80941Smrg{
401b8e80941Smrg	mtx_unlock(&ctx->screen->lock);
402b8e80941Smrg}
403b8e80941Smrg
404b8e80941Smrg/* mark all state dirty: */
405b8e80941Smrgstatic inline void
406b8e80941Smrgfd_context_all_dirty(struct fd_context *ctx)
407b8e80941Smrg{
408b8e80941Smrg	ctx->dirty = ~0;
409b8e80941Smrg	for (unsigned i = 0; i < PIPE_SHADER_TYPES; i++)
410b8e80941Smrg		ctx->dirty_shader[i] = ~0;
411b8e80941Smrg}
412b8e80941Smrg
413b8e80941Smrgstatic inline void
414b8e80941Smrgfd_context_all_clean(struct fd_context *ctx)
415b8e80941Smrg{
416b8e80941Smrg	ctx->dirty = 0;
417b8e80941Smrg	for (unsigned i = 0; i < PIPE_SHADER_TYPES; i++) {
418b8e80941Smrg		/* don't mark compute state as clean, since it is not emitted
419b8e80941Smrg		 * during normal draw call.  The places that call _all_dirty(),
420b8e80941Smrg		 * it is safe to mark compute state dirty as well, but the
421b8e80941Smrg		 * inverse is not true.
422b8e80941Smrg		 */
423b8e80941Smrg		if (i == PIPE_SHADER_COMPUTE)
424b8e80941Smrg			continue;
425b8e80941Smrg		ctx->dirty_shader[i] = 0;
426b8e80941Smrg	}
427b8e80941Smrg}
428b8e80941Smrg
429b8e80941Smrgstatic inline struct pipe_scissor_state *
430848b8605Smrgfd_context_get_scissor(struct fd_context *ctx)
431848b8605Smrg{
432848b8605Smrg	if (ctx->rasterizer && ctx->rasterizer->scissor)
433848b8605Smrg		return &ctx->scissor;
434848b8605Smrg	return &ctx->disabled_scissor;
435848b8605Smrg}
436848b8605Smrg
437b8e80941Smrgstatic inline bool
438848b8605Smrgfd_supported_prim(struct fd_context *ctx, unsigned prim)
439848b8605Smrg{
440848b8605Smrg	return (1 << prim) & ctx->primtype_mask;
441848b8605Smrg}
442848b8605Smrg
443b8e80941Smrgstatic inline struct fd_batch *
444b8e80941Smrgfd_context_batch(struct fd_context *ctx)
445848b8605Smrg{
446b8e80941Smrg	if (unlikely(!ctx->batch)) {
447b8e80941Smrg		struct fd_batch *batch =
448b8e80941Smrg			fd_batch_from_fb(&ctx->screen->batch_cache, ctx, &ctx->framebuffer);
449b8e80941Smrg		util_copy_framebuffer_state(&batch->framebuffer, &ctx->framebuffer);
450b8e80941Smrg		ctx->batch = batch;
451b8e80941Smrg		fd_context_all_dirty(ctx);
452848b8605Smrg	}
453b8e80941Smrg	return ctx->batch;
454848b8605Smrg}
455848b8605Smrg
456848b8605Smrgstatic inline void
457b8e80941Smrgfd_batch_set_stage(struct fd_batch *batch, enum fd_render_stage stage)
458848b8605Smrg{
459b8e80941Smrg	struct fd_context *ctx = batch->ctx;
460b8e80941Smrg
461b8e80941Smrg	/* special case: internal blits (like mipmap level generation)
462b8e80941Smrg	 * go through normal draw path (via util_blitter_blit()).. but
463b8e80941Smrg	 * we need to ignore the FD_STAGE_DRAW which will be set, so we
464b8e80941Smrg	 * don't enable queries which should be paused during internal
465b8e80941Smrg	 * blits:
466b8e80941Smrg	 */
467b8e80941Smrg	if ((batch->stage == FD_STAGE_BLIT) &&
468b8e80941Smrg			(stage != FD_STAGE_NULL))
469b8e80941Smrg		return;
470b8e80941Smrg
471b8e80941Smrg	if (ctx->query_set_stage)
472b8e80941Smrg		ctx->query_set_stage(batch, stage);
473b8e80941Smrg
474b8e80941Smrg	batch->stage = stage;
475848b8605Smrg}
476848b8605Smrg
477b8e80941Smrgvoid fd_context_setup_common_vbos(struct fd_context *ctx);
478b8e80941Smrgvoid fd_context_cleanup_common_vbos(struct fd_context *ctx);
479b8e80941Smrg
480848b8605Smrgstruct pipe_context * fd_context_init(struct fd_context *ctx,
481848b8605Smrg		struct pipe_screen *pscreen, const uint8_t *primtypes,
482b8e80941Smrg		void *priv, unsigned flags);
483848b8605Smrg
484848b8605Smrgvoid fd_context_destroy(struct pipe_context *pctx);
485848b8605Smrg
486848b8605Smrg#endif /* FREEDRENO_CONTEXT_H_ */
487