1/* 2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27 28#include "pipe/p_defines.h" 29#include "pipe/p_screen.h" 30#include "pipe/p_state.h" 31 32#include "util/u_memory.h" 33#include "util/u_inlines.h" 34#include "util/u_format.h" 35#include "util/u_format_s3tc.h" 36#include "util/u_screen.h" 37#include "util/u_string.h" 38#include "util/u_debug.h" 39 40#include "util/os_time.h" 41 42#include "drm-uapi/drm_fourcc.h" 43#include <errno.h> 44#include <stdio.h> 45#include <stdlib.h> 46#include <sys/sysinfo.h> 47 48#include "freedreno_screen.h" 49#include "freedreno_resource.h" 50#include "freedreno_fence.h" 51#include "freedreno_query.h" 52#include "freedreno_util.h" 53 54#include "a2xx/fd2_screen.h" 55#include "a3xx/fd3_screen.h" 56#include "a4xx/fd4_screen.h" 57#include "a5xx/fd5_screen.h" 58#include "a6xx/fd6_screen.h" 59 60 61#include "ir3/ir3_nir.h" 62#include "a2xx/ir2.h" 63 64/* XXX this should go away */ 65#include "state_tracker/drm_driver.h" 66 67static const struct debug_named_value debug_options[] = { 68 {"msgs", FD_DBG_MSGS, "Print debug messages"}, 69 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"}, 70 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"}, 71 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"}, 72 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"}, 73 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"}, 74 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"}, 75 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"}, 76 {"nobin", FD_DBG_NOBIN, "Disable hw binning"}, 77 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"}, 78 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"}, 79 {"flush", FD_DBG_FLUSH, "Force flush after every draw"}, 80 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"}, 81 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"}, 82 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"}, 83 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"}, 84 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx+)"}, 85 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"}, 86 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"}, 87 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"}, 88 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a5xx)"}, 89 {"perfcntrs", FD_DBG_PERFC, "Expose performance counters"}, 90 {"softpin", FD_DBG_SOFTPIN,"Enable softpin command submission (experimental)"}, 91 {"ubwc", FD_DBG_UBWC, "Enable UBWC for all internal buffers (experimental)"}, 92 DEBUG_NAMED_VALUE_END 93}; 94 95DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0) 96 97int fd_mesa_debug = 0; 98bool fd_binning_enabled = true; 99static bool glsl120 = false; 100 101static const char * 102fd_screen_get_name(struct pipe_screen *pscreen) 103{ 104 static char buffer[128]; 105 util_snprintf(buffer, sizeof(buffer), "FD%03d", 106 fd_screen(pscreen)->device_id); 107 return buffer; 108} 109 110static const char * 111fd_screen_get_vendor(struct pipe_screen *pscreen) 112{ 113 return "freedreno"; 114} 115 116static const char * 117fd_screen_get_device_vendor(struct pipe_screen *pscreen) 118{ 119 return "Qualcomm"; 120} 121 122 123static uint64_t 124fd_screen_get_timestamp(struct pipe_screen *pscreen) 125{ 126 struct fd_screen *screen = fd_screen(pscreen); 127 128 if (screen->has_timestamp) { 129 uint64_t n; 130 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n); 131 debug_assert(screen->max_freq > 0); 132 return n * 1000000000 / screen->max_freq; 133 } else { 134 int64_t cpu_time = os_time_get() * 1000; 135 return cpu_time + screen->cpu_gpu_time_delta; 136 } 137 138} 139 140static void 141fd_screen_destroy(struct pipe_screen *pscreen) 142{ 143 struct fd_screen *screen = fd_screen(pscreen); 144 145 if (screen->pipe) 146 fd_pipe_del(screen->pipe); 147 148 if (screen->dev) 149 fd_device_del(screen->dev); 150 151 if (screen->ro) 152 FREE(screen->ro); 153 154 fd_bc_fini(&screen->batch_cache); 155 156 slab_destroy_parent(&screen->transfer_pool); 157 158 mtx_destroy(&screen->lock); 159 160 ralloc_free(screen->compiler); 161 162 free(screen->perfcntr_queries); 163 free(screen); 164} 165 166/* 167TODO either move caps to a2xx/a3xx specific code, or maybe have some 168tables for things that differ if the delta is not too much.. 169 */ 170static int 171fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 172{ 173 struct fd_screen *screen = fd_screen(pscreen); 174 175 /* this is probably not totally correct.. but it's a start: */ 176 switch (param) { 177 /* Supported features (boolean caps). */ 178 case PIPE_CAP_NPOT_TEXTURES: 179 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 180 case PIPE_CAP_ANISOTROPIC_FILTER: 181 case PIPE_CAP_POINT_SPRITE: 182 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 183 case PIPE_CAP_TEXTURE_SWIZZLE: 184 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 185 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 186 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 187 case PIPE_CAP_SEAMLESS_CUBE_MAP: 188 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 189 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 190 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 191 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 192 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 193 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 194 case PIPE_CAP_STRING_MARKER: 195 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 196 case PIPE_CAP_TEXTURE_BARRIER: 197 case PIPE_CAP_INVALIDATE_BUFFER: 198 return 1; 199 200 case PIPE_CAP_PACKED_UNIFORMS: 201 return !is_a2xx(screen); 202 203 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 204 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: 205 return screen->has_robustness; 206 207 case PIPE_CAP_VERTEXID_NOBASE: 208 return is_a3xx(screen) || is_a4xx(screen); 209 210 case PIPE_CAP_COMPUTE: 211 return has_compute(screen); 212 213 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 214 case PIPE_CAP_PCI_GROUP: 215 case PIPE_CAP_PCI_BUS: 216 case PIPE_CAP_PCI_DEVICE: 217 case PIPE_CAP_PCI_FUNCTION: 218 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: 219 return 0; 220 221 case PIPE_CAP_SM3: 222 case PIPE_CAP_PRIMITIVE_RESTART: 223 case PIPE_CAP_TGSI_INSTANCEID: 224 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 225 case PIPE_CAP_INDEP_BLEND_ENABLE: 226 case PIPE_CAP_INDEP_BLEND_FUNC: 227 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 228 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 229 case PIPE_CAP_CONDITIONAL_RENDER: 230 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 231 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 232 case PIPE_CAP_CLIP_HALFZ: 233 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen); 234 235 case PIPE_CAP_FAKE_SW_MSAA: 236 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE); 237 238 case PIPE_CAP_TEXTURE_MULTISAMPLE: 239 return is_a5xx(screen) || is_a6xx(screen); 240 241 case PIPE_CAP_SURFACE_SAMPLE_COUNT: 242 return is_a6xx(screen); 243 244 case PIPE_CAP_DEPTH_CLIP_DISABLE: 245 return is_a3xx(screen) || is_a4xx(screen); 246 247 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 248 return is_a5xx(screen) || is_a6xx(screen); 249 250 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 251 if (is_a3xx(screen)) return 16; 252 if (is_a4xx(screen)) return 32; 253 if (is_a5xx(screen)) return 32; 254 if (is_a6xx(screen)) return 64; 255 return 0; 256 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: 257 /* We could possibly emulate more by pretending 2d/rect textures and 258 * splitting high bits of index into 2nd dimension.. 259 */ 260 if (is_a3xx(screen)) return 8192; 261 if (is_a4xx(screen)) return 16384; 262 if (is_a5xx(screen)) return 16384; 263 if (is_a6xx(screen)) return 1 << 27; 264 return 0; 265 266 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 267 case PIPE_CAP_CUBE_MAP_ARRAY: 268 case PIPE_CAP_SAMPLER_VIEW_TARGET: 269 case PIPE_CAP_TEXTURE_QUERY_LOD: 270 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen); 271 272 case PIPE_CAP_START_INSTANCE: 273 /* Note that a5xx can do this, it just can't (at least with 274 * current firmware) do draw_indirect with base_instance. 275 * Since draw_indirect is needed sooner (gles31 and gl40 vs 276 * gl42), hide base_instance on a5xx. :-/ 277 */ 278 return is_a4xx(screen); 279 280 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 281 return 64; 282 283 case PIPE_CAP_GLSL_FEATURE_LEVEL: 284 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 285 if (glsl120) 286 return 120; 287 return is_ir3(screen) ? 140 : 120; 288 289 case PIPE_CAP_ESSL_FEATURE_LEVEL: 290 /* we can probably enable 320 for a5xx too, but need to test: */ 291 if (is_a6xx(screen)) return 320; 292 if (is_a5xx(screen)) return 310; 293 if (is_ir3(screen)) return 300; 294 return 120; 295 296 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 297 if (is_a6xx(screen)) return 64; 298 if (is_a5xx(screen)) return 4; 299 return 0; 300 301 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 302 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) 303 return 4; 304 return 0; 305 306 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */ 307 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 308 return 0; 309 310 case PIPE_CAP_TGSI_FS_FBFETCH: 311 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE && 312 is_a6xx(screen)) 313 return 1; 314 return 0; 315 case PIPE_CAP_SAMPLE_SHADING: 316 if (is_a6xx(screen)) return 1; 317 return 0; 318 319 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 320 return 0; 321 322 case PIPE_CAP_CONTEXT_PRIORITY_MASK: 323 return screen->priority_mask; 324 325 case PIPE_CAP_DRAW_INDIRECT: 326 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) 327 return 1; 328 return 0; 329 330 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 331 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) 332 return 1; 333 return 0; 334 335 case PIPE_CAP_LOAD_CONSTBUF: 336 /* name is confusing, but this turns on std430 packing */ 337 if (is_ir3(screen)) 338 return 1; 339 return 0; 340 341 case PIPE_CAP_MAX_VIEWPORTS: 342 return 1; 343 344 case PIPE_CAP_MAX_VARYINGS: 345 return 16; 346 347 case PIPE_CAP_SHAREABLE_SHADERS: 348 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: 349 /* manage the variants for these ourself, to avoid breaking precompile: */ 350 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 351 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 352 if (is_ir3(screen)) 353 return 1; 354 return 0; 355 356 /* Stream output. */ 357 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 358 if (is_ir3(screen)) 359 return PIPE_MAX_SO_BUFFERS; 360 return 0; 361 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 362 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 363 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 364 if (is_ir3(screen)) 365 return 1; 366 return 0; 367 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 368 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 369 if (is_ir3(screen)) 370 return 16 * 4; /* should only be shader out limit? */ 371 return 0; 372 373 /* Texturing. */ 374 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 375 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 376 return MAX_MIP_LEVELS; 377 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 378 return 11; 379 380 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 381 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0; 382 383 /* Render targets. */ 384 case PIPE_CAP_MAX_RENDER_TARGETS: 385 return screen->max_rts; 386 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 387 return is_a3xx(screen) ? 1 : 0; 388 389 /* Queries. */ 390 case PIPE_CAP_OCCLUSION_QUERY: 391 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen); 392 case PIPE_CAP_QUERY_TIMESTAMP: 393 case PIPE_CAP_QUERY_TIME_ELAPSED: 394 /* only a4xx, requires new enough kernel so we know max_freq: */ 395 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)); 396 397 case PIPE_CAP_VENDOR_ID: 398 return 0x5143; 399 case PIPE_CAP_DEVICE_ID: 400 return 0xFFFFFFFF; 401 case PIPE_CAP_ACCELERATED: 402 return 1; 403 case PIPE_CAP_VIDEO_MEMORY: 404 DBG("FINISHME: The value returned is incorrect\n"); 405 return 10; 406 case PIPE_CAP_UMA: 407 return 1; 408 case PIPE_CAP_NATIVE_FENCE_FD: 409 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD; 410 default: 411 return u_pipe_screen_get_param_defaults(pscreen, param); 412 } 413} 414 415static float 416fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 417{ 418 switch (param) { 419 case PIPE_CAPF_MAX_LINE_WIDTH: 420 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 421 /* NOTE: actual value is 127.0f, but this is working around a deqp 422 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide 423 * uses too small of a render target size, and gets confused when 424 * the lines start going offscreen. 425 * 426 * See: https://code.google.com/p/android/issues/detail?id=206513 427 */ 428 if (fd_mesa_debug & FD_DBG_DEQP) 429 return 48.0f; 430 return 127.0f; 431 case PIPE_CAPF_MAX_POINT_WIDTH: 432 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 433 return 4092.0f; 434 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 435 return 16.0f; 436 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 437 return 15.0f; 438 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 439 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 440 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 441 return 0.0f; 442 } 443 debug_printf("unknown paramf %d\n", param); 444 return 0; 445} 446 447static int 448fd_screen_get_shader_param(struct pipe_screen *pscreen, 449 enum pipe_shader_type shader, 450 enum pipe_shader_cap param) 451{ 452 struct fd_screen *screen = fd_screen(pscreen); 453 454 switch(shader) 455 { 456 case PIPE_SHADER_FRAGMENT: 457 case PIPE_SHADER_VERTEX: 458 break; 459 case PIPE_SHADER_COMPUTE: 460 if (has_compute(screen)) 461 break; 462 return 0; 463 case PIPE_SHADER_GEOMETRY: 464 /* maye we could emulate.. */ 465 return 0; 466 default: 467 DBG("unknown shader type %d", shader); 468 return 0; 469 } 470 471 /* this is probably not totally correct.. but it's a start: */ 472 switch (param) { 473 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 474 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 475 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 476 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 477 return 16384; 478 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 479 return 8; /* XXX */ 480 case PIPE_SHADER_CAP_MAX_INPUTS: 481 case PIPE_SHADER_CAP_MAX_OUTPUTS: 482 return 16; 483 case PIPE_SHADER_CAP_MAX_TEMPS: 484 return 64; /* Max native temporaries. */ 485 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: 486 /* NOTE: seems to be limit for a3xx is actually 512 but 487 * split between VS and FS. Use lower limit of 256 to 488 * avoid getting into impossible situations: 489 */ 490 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]); 491 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 492 return is_ir3(screen) ? 16 : 1; 493 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 494 return 1; 495 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 496 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 497 /* Technically this should be the same as for TEMP/CONST, since 498 * everything is just normal registers. This is just temporary 499 * hack until load_input/store_output handle arrays in a similar 500 * way as load_var/store_var.. 501 */ 502 return 0; 503 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 504 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 505 /* a2xx compiler doesn't handle indirect: */ 506 return is_ir3(screen) ? 1 : 0; 507 case PIPE_SHADER_CAP_SUBROUTINES: 508 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: 509 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: 510 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: 511 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: 512 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 513 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 514 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: 515 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: 516 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 517 return 0; 518 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 519 return 1; 520 case PIPE_SHADER_CAP_INTEGERS: 521 if (glsl120) 522 return 0; 523 return is_ir3(screen) ? 1 : 0; 524 case PIPE_SHADER_CAP_INT64_ATOMICS: 525 return 0; 526 case PIPE_SHADER_CAP_FP16: 527 return 0; 528 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 529 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 530 return 16; 531 case PIPE_SHADER_CAP_PREFERRED_IR: 532 return PIPE_SHADER_IR_NIR; 533 case PIPE_SHADER_CAP_SUPPORTED_IRS: 534 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI); 535 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: 536 return 32; 537 case PIPE_SHADER_CAP_SCALAR_ISA: 538 return is_ir3(screen) ? 1 : 0; 539 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 540 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 541 if (is_a5xx(screen) || is_a6xx(screen)) { 542 /* a5xx (and a4xx for that matter) has one state-block 543 * for compute-shader SSBO's and another that is shared 544 * by VS/HS/DS/GS/FS.. so to simplify things for now 545 * just advertise SSBOs for FS and CS. We could possibly 546 * do what blob does, and partition the space for 547 * VS/HS/DS/GS/FS. The blob advertises: 548 * 549 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4 550 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4 551 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4 552 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4 553 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4 554 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24 555 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24 556 * 557 * I think that way we could avoid having to patch shaders 558 * for actual SSBO indexes by using a static partitioning. 559 * 560 * Note same state block is used for images and buffers, 561 * but images also need texture state for read access 562 * (isam/isam.3d) 563 */ 564 switch(shader) 565 { 566 case PIPE_SHADER_FRAGMENT: 567 case PIPE_SHADER_COMPUTE: 568 return 24; 569 default: 570 return 0; 571 } 572 } 573 return 0; 574 } 575 debug_printf("unknown shader param %d\n", param); 576 return 0; 577} 578 579/* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this 580 * into per-generation backend? 581 */ 582static int 583fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type, 584 enum pipe_compute_cap param, void *ret) 585{ 586 struct fd_screen *screen = fd_screen(pscreen); 587 const char * const ir = "ir3"; 588 589 if (!has_compute(screen)) 590 return 0; 591 592#define RET(x) do { \ 593 if (ret) \ 594 memcpy(ret, x, sizeof(x)); \ 595 return sizeof(x); \ 596} while (0) 597 598 switch (param) { 599 case PIPE_COMPUTE_CAP_ADDRESS_BITS: 600// don't expose 64b pointer support yet, until ir3 supports 64b 601// math, otherwise spir64 target is used and we get 64b pointer 602// calculations that we can't do yet 603// if (is_a5xx(screen)) 604// RET((uint32_t []){ 64 }); 605 RET((uint32_t []){ 32 }); 606 607 case PIPE_COMPUTE_CAP_IR_TARGET: 608 if (ret) 609 sprintf(ret, ir); 610 return strlen(ir) * sizeof(char); 611 612 case PIPE_COMPUTE_CAP_GRID_DIMENSION: 613 RET((uint64_t []) { 3 }); 614 615 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 616 RET(((uint64_t []) { 65535, 65535, 65535 })); 617 618 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 619 RET(((uint64_t []) { 1024, 1024, 64 })); 620 621 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 622 RET((uint64_t []) { 1024 }); 623 624 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: 625 RET((uint64_t []) { screen->ram_size }); 626 627 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 628 RET((uint64_t []) { 32768 }); 629 630 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: 631 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: 632 RET((uint64_t []) { 4096 }); 633 634 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: 635 RET((uint64_t []) { screen->ram_size }); 636 637 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: 638 RET((uint32_t []) { screen->max_freq / 1000000 }); 639 640 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: 641 RET((uint32_t []) { 9999 }); // TODO 642 643 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: 644 RET((uint32_t []) { 1 }); 645 646 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: 647 RET((uint32_t []) { 32 }); // TODO 648 649 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: 650 RET((uint64_t []) { 1024 }); // TODO 651 } 652 653 return 0; 654} 655 656static const void * 657fd_get_compiler_options(struct pipe_screen *pscreen, 658 enum pipe_shader_ir ir, unsigned shader) 659{ 660 struct fd_screen *screen = fd_screen(pscreen); 661 662 if (is_ir3(screen)) 663 return ir3_get_compiler_options(screen->compiler); 664 665 return ir2_get_compiler_options(); 666} 667 668boolean 669fd_screen_bo_get_handle(struct pipe_screen *pscreen, 670 struct fd_bo *bo, 671 struct renderonly_scanout *scanout, 672 unsigned stride, 673 struct winsys_handle *whandle) 674{ 675 whandle->stride = stride; 676 677 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { 678 return fd_bo_get_name(bo, &whandle->handle) == 0; 679 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) { 680 if (renderonly_get_handle(scanout, whandle)) 681 return TRUE; 682 whandle->handle = fd_bo_handle(bo); 683 return TRUE; 684 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { 685 whandle->handle = fd_bo_dmabuf(bo); 686 return TRUE; 687 } else { 688 return FALSE; 689 } 690} 691 692static void 693fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen, 694 enum pipe_format format, 695 int max, uint64_t *modifiers, 696 unsigned int *external_only, 697 int *count) 698{ 699 struct fd_screen *screen = fd_screen(pscreen); 700 int i, num = 0; 701 702 max = MIN2(max, screen->num_supported_modifiers); 703 704 if (!max) { 705 max = screen->num_supported_modifiers; 706 external_only = NULL; 707 modifiers = NULL; 708 } 709 710 for (i = 0; i < max; i++) { 711 if (modifiers) 712 modifiers[num] = screen->supported_modifiers[i]; 713 714 if (external_only) 715 external_only[num] = 0; 716 717 num++; 718 } 719 720 *count = num; 721} 722 723struct fd_bo * 724fd_screen_bo_from_handle(struct pipe_screen *pscreen, 725 struct winsys_handle *whandle) 726{ 727 struct fd_screen *screen = fd_screen(pscreen); 728 struct fd_bo *bo; 729 730 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { 731 bo = fd_bo_from_name(screen->dev, whandle->handle); 732 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) { 733 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0); 734 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { 735 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle); 736 } else { 737 DBG("Attempt to import unsupported handle type %d", whandle->type); 738 return NULL; 739 } 740 741 if (!bo) { 742 DBG("ref name 0x%08x failed", whandle->handle); 743 return NULL; 744 } 745 746 return bo; 747} 748 749struct pipe_screen * 750fd_screen_create(struct fd_device *dev, struct renderonly *ro) 751{ 752 struct fd_screen *screen = CALLOC_STRUCT(fd_screen); 753 struct pipe_screen *pscreen; 754 uint64_t val; 755 756 fd_mesa_debug = debug_get_option_fd_mesa_debug(); 757 758 if (fd_mesa_debug & FD_DBG_NOBIN) 759 fd_binning_enabled = false; 760 761 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120); 762 763 if (!screen) 764 return NULL; 765 766 pscreen = &screen->base; 767 768 screen->dev = dev; 769 screen->refcnt = 1; 770 771 if (ro) { 772 screen->ro = renderonly_dup(ro); 773 if (!screen->ro) { 774 DBG("could not create renderonly object"); 775 goto fail; 776 } 777 } 778 779 // maybe this should be in context? 780 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D); 781 if (!screen->pipe) { 782 DBG("could not create 3d pipe"); 783 goto fail; 784 } 785 786 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) { 787 DBG("could not get GMEM size"); 788 goto fail; 789 } 790 screen->gmemsize_bytes = val; 791 792 if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) { 793 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base); 794 } 795 796 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) { 797 DBG("could not get device-id"); 798 goto fail; 799 } 800 screen->device_id = val; 801 802 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) { 803 DBG("could not get gpu freq"); 804 /* this limits what performance related queries are 805 * supported but is not fatal 806 */ 807 screen->max_freq = 0; 808 } else { 809 screen->max_freq = val; 810 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0) 811 screen->has_timestamp = true; 812 } 813 814 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) { 815 DBG("could not get gpu-id"); 816 goto fail; 817 } 818 screen->gpu_id = val; 819 820 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) { 821 DBG("could not get chip-id"); 822 /* older kernels may not have this property: */ 823 unsigned core = screen->gpu_id / 100; 824 unsigned major = (screen->gpu_id % 100) / 10; 825 unsigned minor = screen->gpu_id % 10; 826 unsigned patch = 0; /* assume the worst */ 827 val = (patch & 0xff) | ((minor & 0xff) << 8) | 828 ((major & 0xff) << 16) | ((core & 0xff) << 24); 829 } 830 screen->chip_id = val; 831 832 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) { 833 DBG("could not get # of rings"); 834 screen->priority_mask = 0; 835 } else { 836 /* # of rings equates to number of unique priority values: */ 837 screen->priority_mask = (1 << val) - 1; 838 } 839 840 if ((fd_device_version(dev) >= FD_VERSION_ROBUSTNESS) && 841 (fd_pipe_get_param(screen->pipe, FD_PP_PGTABLE, &val) == 0)) { 842 screen->has_robustness = val; 843 } 844 845 struct sysinfo si; 846 sysinfo(&si); 847 screen->ram_size = si.totalram; 848 849 DBG("Pipe Info:"); 850 DBG(" GPU-id: %d", screen->gpu_id); 851 DBG(" Chip-id: 0x%08x", screen->chip_id); 852 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes); 853 854 /* explicitly checking for GPU revisions that are known to work. This 855 * may be overly conservative for a3xx, where spoofing the gpu_id with 856 * the blob driver seems to generate identical cmdstream dumps. But 857 * on a2xx, there seem to be small differences between the GPU revs 858 * so it is probably better to actually test first on real hardware 859 * before enabling: 860 * 861 * If you have a different adreno version, feel free to add it to one 862 * of the cases below and see what happens. And if it works, please 863 * send a patch ;-) 864 */ 865 switch (screen->gpu_id) { 866 case 200: 867 case 201: 868 case 205: 869 case 220: 870 fd2_screen_init(pscreen); 871 break; 872 case 305: 873 case 307: 874 case 320: 875 case 330: 876 fd3_screen_init(pscreen); 877 break; 878 case 420: 879 case 430: 880 fd4_screen_init(pscreen); 881 break; 882 case 530: 883 fd5_screen_init(pscreen); 884 break; 885 case 630: 886 fd6_screen_init(pscreen); 887 break; 888 default: 889 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id); 890 goto fail; 891 } 892 893 if (screen->gpu_id >= 600) { 894 screen->gmem_alignw = 32; 895 screen->gmem_alignh = 32; 896 screen->num_vsc_pipes = 32; 897 } else if (screen->gpu_id >= 500) { 898 screen->gmem_alignw = 64; 899 screen->gmem_alignh = 32; 900 screen->num_vsc_pipes = 16; 901 } else { 902 screen->gmem_alignw = 32; 903 screen->gmem_alignh = 32; 904 screen->num_vsc_pipes = 8; 905 } 906 907 /* NOTE: don't enable if we have too old of a kernel to support 908 * growable cmdstream buffers, since memory requirement for cmdstream 909 * buffers would be too much otherwise. 910 */ 911 if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS) 912 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER); 913 914 fd_bc_init(&screen->batch_cache); 915 916 (void) mtx_init(&screen->lock, mtx_plain); 917 918 pscreen->destroy = fd_screen_destroy; 919 pscreen->get_param = fd_screen_get_param; 920 pscreen->get_paramf = fd_screen_get_paramf; 921 pscreen->get_shader_param = fd_screen_get_shader_param; 922 pscreen->get_compute_param = fd_get_compute_param; 923 pscreen->get_compiler_options = fd_get_compiler_options; 924 925 fd_resource_screen_init(pscreen); 926 fd_query_screen_init(pscreen); 927 928 pscreen->get_name = fd_screen_get_name; 929 pscreen->get_vendor = fd_screen_get_vendor; 930 pscreen->get_device_vendor = fd_screen_get_device_vendor; 931 932 pscreen->get_timestamp = fd_screen_get_timestamp; 933 934 pscreen->fence_reference = fd_fence_ref; 935 pscreen->fence_finish = fd_fence_finish; 936 pscreen->fence_get_fd = fd_fence_get_fd; 937 938 pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers; 939 940 if (!screen->supported_modifiers) { 941 static const uint64_t supported_modifiers[] = { 942 DRM_FORMAT_MOD_LINEAR, 943 }; 944 945 screen->supported_modifiers = supported_modifiers; 946 screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers); 947 } 948 949 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16); 950 951 return pscreen; 952 953fail: 954 fd_screen_destroy(pscreen); 955 return NULL; 956} 957