1/* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23#include <stdio.h> 24#include <errno.h> 25#include "pipe/p_defines.h" 26#include "pipe/p_state.h" 27#include "pipe/p_context.h" 28#include "pipe/p_screen.h" 29#include "util/u_inlines.h" 30#include "util/u_format.h" 31#include "util/u_upload_mgr.h" 32#include "util/ralloc.h" 33#include "iris_context.h" 34#include "iris_resource.h" 35#include "iris_screen.h" 36#include "intel/compiler/brw_compiler.h" 37#include "util/format_srgb.h" 38 39static bool 40iris_is_color_fast_clear_compatible(struct iris_context *ice, 41 enum isl_format format, 42 const union isl_color_value color) 43{ 44 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 45 const struct gen_device_info *devinfo = &batch->screen->devinfo; 46 47 if (isl_format_has_int_channel(format)) { 48 perf_debug(&ice->dbg, "Integer fast clear not enabled for %s", 49 isl_format_get_name(format)); 50 return false; 51 } 52 53 for (int i = 0; i < 4; i++) { 54 if (!isl_format_has_color_component(format, i)) { 55 continue; 56 } 57 58 if (devinfo->gen < 9 && 59 color.f32[i] != 0.0f && color.f32[i] != 1.0f) { 60 return false; 61 } 62 } 63 64 return true; 65} 66 67static bool 68can_fast_clear_color(struct iris_context *ice, 69 struct pipe_resource *p_res, 70 unsigned level, 71 const struct pipe_box *box, 72 enum isl_format format, 73 enum isl_format render_format, 74 union isl_color_value color) 75{ 76 struct iris_resource *res = (void *) p_res; 77 78 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 79 const struct gen_device_info *devinfo = &batch->screen->devinfo; 80 81 if (res->aux.usage == ISL_AUX_USAGE_NONE) 82 return false; 83 84 /* Surface state can only record one fast clear color value. Therefore 85 * unless different levels/layers agree on the color it can be used to 86 * represent only single level/layer. Here it will be reserved for the 87 * first slice (level 0, layer 0). 88 */ 89 if (level > 0 || box->z > 0 || box->depth > 1) 90 return false; 91 92 /* Check for partial clear */ 93 if (box->x > 0 || box->y > 0 || 94 box->width < p_res->width0 || 95 box->height < p_res->height0) { 96 return false; 97 } 98 99 /* We store clear colors as floats or uints as needed. If there are 100 * texture views in play, the formats will not properly be respected 101 * during resolves because the resolve operations only know about the 102 * resource and not the renderbuffer. 103 */ 104 if (isl_format_srgb_to_linear(render_format) != 105 isl_format_srgb_to_linear(format)) { 106 return false; 107 } 108 109 /* XXX: if (irb->mt->supports_fast_clear) 110 * see intel_miptree_create_for_dri_image() 111 */ 112 113 if (!iris_is_color_fast_clear_compatible(ice, format, color)) 114 return false; 115 116 return true; 117} 118 119static union isl_color_value 120convert_fast_clear_color(struct iris_context *ice, 121 struct iris_resource *res, 122 enum isl_format render_format, 123 const union isl_color_value color) 124{ 125 union isl_color_value override_color = color; 126 struct pipe_resource *p_res = (void *) res; 127 128 const enum pipe_format format = p_res->format; 129 const struct util_format_description *desc = 130 util_format_description(format); 131 unsigned colormask = util_format_colormask(desc); 132 133 if (util_format_is_intensity(format) || 134 util_format_is_luminance(format) || 135 util_format_is_luminance_alpha(format)) { 136 override_color.u32[1] = override_color.u32[0]; 137 override_color.u32[2] = override_color.u32[0]; 138 if (util_format_is_intensity(format)) 139 override_color.u32[3] = override_color.u32[0]; 140 } else { 141 for (int chan = 0; chan < 3; chan++) { 142 if (!(colormask & (1 << chan))) 143 override_color.u32[chan] = 0; 144 } 145 } 146 147 if (util_format_is_unorm(format)) { 148 for (int i = 0; i < 4; i++) 149 override_color.f32[i] = CLAMP(override_color.f32[i], 0.0f, 1.0f); 150 } else if (util_format_is_snorm(format)) { 151 for (int i = 0; i < 4; i++) 152 override_color.f32[i] = CLAMP(override_color.f32[i], -1.0f, 1.0f); 153 } else if (util_format_is_pure_uint(format)) { 154 for (int i = 0; i < 4; i++) { 155 unsigned bits = util_format_get_component_bits( 156 format, UTIL_FORMAT_COLORSPACE_RGB, i); 157 if (bits < 32) { 158 uint32_t max = (1u << bits) - 1; 159 override_color.u32[i] = MIN2(override_color.u32[i], max); 160 } 161 } 162 } else if (util_format_is_pure_sint(format)) { 163 for (int i = 0; i < 4; i++) { 164 unsigned bits = util_format_get_component_bits( 165 format, UTIL_FORMAT_COLORSPACE_RGB, i); 166 if (bits < 32) { 167 int32_t max = (1 << (bits - 1)) - 1; 168 int32_t min = -(1 << (bits - 1)); 169 override_color.i32[i] = CLAMP(override_color.i32[i], min, max); 170 } 171 } 172 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT || 173 format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 174 /* these packed float formats only store unsigned values */ 175 for (int i = 0; i < 4; i++) 176 override_color.f32[i] = MAX2(override_color.f32[i], 0.0f); 177 } 178 179 if (!(colormask & 1 << 3)) { 180 if (util_format_is_pure_integer(format)) 181 override_color.u32[3] = 1; 182 else 183 override_color.f32[3] = 1.0f; 184 } 185 186 /* Handle linear to SRGB conversion */ 187 if (isl_format_is_srgb(render_format)) { 188 for (int i = 0; i < 3; i++) { 189 override_color.f32[i] = 190 util_format_linear_to_srgb_float(override_color.f32[i]); 191 } 192 } 193 194 return override_color; 195} 196 197static void 198fast_clear_color(struct iris_context *ice, 199 struct iris_resource *res, 200 unsigned level, 201 const struct pipe_box *box, 202 enum isl_format format, 203 union isl_color_value color, 204 enum blorp_batch_flags blorp_flags) 205{ 206 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 207 struct pipe_resource *p_res = (void *) res; 208 const enum isl_aux_state aux_state = 209 iris_resource_get_aux_state(res, level, box->z); 210 211 color = convert_fast_clear_color(ice, res, format, color); 212 213 bool color_changed = !!memcmp(&res->aux.clear_color, &color, 214 sizeof(color)); 215 216 if (color_changed) { 217 /* We decided that we are going to fast clear, and the color is 218 * changing. But if we have a predicate bit set, the predication 219 * affects whether we should clear or not, and if we shouldn't, we 220 * also shouldn't update the clear color. 221 * 222 * However, we can't simply predicate-update the clear color (the 223 * commands don't support that). And we would lose track of the 224 * color, preventing us from doing some optimizations later. 225 * 226 * Since changing the clear color when the predication bit is enabled 227 * is not something that should happen often, we stall on the CPU here 228 * to resolve the predication, and then proceed. 229 */ 230 iris_resolve_conditional_render(ice); 231 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER) 232 return; 233 } 234 235 iris_resource_set_clear_color(ice, res, color); 236 237 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't 238 * changed, the clear is redundant and can be skipped. 239 */ 240 if (!color_changed && aux_state == ISL_AUX_STATE_CLEAR) 241 return; 242 243 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": 244 * 245 * "Any transition from any value in {Clear, Render, Resolve} to a 246 * different value in {Clear, Render, Resolve} requires end of pipe 247 * synchronization." 248 * 249 * In other words, fast clear ops are not properly synchronized with 250 * other drawing. We need to use a PIPE_CONTROL to ensure that the 251 * contents of the previous draw hit the render target before we resolve 252 * and again afterwards to ensure that the resolve is complete before we 253 * do any more regular drawing. 254 */ 255 iris_emit_end_of_pipe_sync(batch, PIPE_CONTROL_RENDER_TARGET_FLUSH); 256 257 /* If we reach this point, we need to fast clear to change the state to 258 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both). 259 */ 260 blorp_flags |= color_changed ? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR; 261 262 struct blorp_batch blorp_batch; 263 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 264 265 struct blorp_surf surf; 266 iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, res->aux.usage, 267 level, true); 268 269 /* In newer gens (> 9), the hardware will do a linear -> sRGB conversion of 270 * the clear color during the fast clear, if the surface format is of sRGB 271 * type. We use the linear version of the surface format here to prevent 272 * that from happening, since we already do our own linear -> sRGB 273 * conversion in convert_fast_clear_color(). 274 */ 275 blorp_fast_clear(&blorp_batch, &surf, isl_format_srgb_to_linear(format), 276 level, box->z, box->depth, 277 box->x, box->y, box->x + box->width, 278 box->y + box->height); 279 blorp_batch_finish(&blorp_batch); 280 iris_emit_end_of_pipe_sync(batch, PIPE_CONTROL_RENDER_TARGET_FLUSH); 281 282 iris_resource_set_aux_state(ice, res, level, box->z, 283 box->depth, ISL_AUX_STATE_CLEAR); 284 ice->state.dirty |= IRIS_ALL_DIRTY_BINDINGS; 285 return; 286} 287 288static void 289clear_color(struct iris_context *ice, 290 struct pipe_resource *p_res, 291 unsigned level, 292 const struct pipe_box *box, 293 bool render_condition_enabled, 294 enum isl_format format, 295 struct isl_swizzle swizzle, 296 union isl_color_value color) 297{ 298 struct iris_resource *res = (void *) p_res; 299 300 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 301 const struct gen_device_info *devinfo = &batch->screen->devinfo; 302 enum blorp_batch_flags blorp_flags = 0; 303 304 if (render_condition_enabled) { 305 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER) 306 return; 307 308 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) 309 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE; 310 } 311 312 if (p_res->target == PIPE_BUFFER) 313 util_range_add(&res->valid_buffer_range, box->x, box->x + box->width); 314 315 iris_batch_maybe_flush(batch, 1500); 316 317 bool can_fast_clear = can_fast_clear_color(ice, p_res, level, box, 318 res->surf.format, format, color); 319 if (can_fast_clear) { 320 fast_clear_color(ice, res, level, box, format, color, 321 blorp_flags); 322 return; 323 } 324 325 bool color_write_disable[4] = { false, false, false, false }; 326 enum isl_aux_usage aux_usage = 327 iris_resource_render_aux_usage(ice, res, format, 328 false, false); 329 330 iris_resource_prepare_render(ice, batch, res, level, 331 box->z, box->depth, aux_usage); 332 333 struct blorp_surf surf; 334 iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, aux_usage, level, 335 true); 336 337 struct blorp_batch blorp_batch; 338 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 339 340 if (!isl_format_supports_rendering(devinfo, format) && 341 isl_format_is_rgbx(format)) 342 format = isl_format_rgbx_to_rgba(format); 343 344 blorp_clear(&blorp_batch, &surf, format, swizzle, 345 level, box->z, box->depth, box->x, box->y, 346 box->x + box->width, box->y + box->height, 347 color, color_write_disable); 348 349 blorp_batch_finish(&blorp_batch); 350 iris_flush_and_dirty_for_history(ice, batch, res); 351 352 iris_resource_finish_render(ice, res, level, 353 box->z, box->depth, aux_usage); 354} 355 356static bool 357can_fast_clear_depth(struct iris_context *ice, 358 struct iris_resource *res, 359 unsigned level, 360 const struct pipe_box *box, 361 float depth) 362{ 363 struct pipe_resource *p_res = (void *) res; 364 365 /* Check for partial clears */ 366 if (box->x > 0 || box->y > 0 || 367 box->width < u_minify(p_res->width0, level) || 368 box->height < u_minify(p_res->height0, level)) { 369 return false; 370 } 371 372 if (!(res->aux.has_hiz & (1 << level))) 373 return false; 374 375 return true; 376} 377 378static void 379fast_clear_depth(struct iris_context *ice, 380 struct iris_resource *res, 381 unsigned level, 382 const struct pipe_box *box, 383 float depth) 384{ 385 struct pipe_resource *p_res = (void *) res; 386 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 387 388 /* Quantize the clear value to what can be stored in the actual depth 389 * buffer. This makes the following check more accurate because it now 390 * checks if the actual depth bits will match. It also prevents us from 391 * getting a too-accurate depth value during depth testing or when sampling 392 * with HiZ enabled. 393 */ 394 const unsigned nbits = p_res->format == PIPE_FORMAT_Z16_UNORM ? 16 : 24; 395 const uint32_t depth_max = (1 << nbits) - 1; 396 depth = p_res->format == PIPE_FORMAT_Z32_FLOAT ? depth : 397 (unsigned)(depth * depth_max) / (float)depth_max; 398 399 bool update_clear_depth = false; 400 401 /* If we're clearing to a new clear value, then we need to resolve any clear 402 * flags out of the HiZ buffer into the real depth buffer. 403 */ 404 if (res->aux.clear_color.f32[0] != depth) { 405 /* We decided that we are going to fast clear, and the color is 406 * changing. But if we have a predicate bit set, the predication 407 * affects whether we should clear or not, and if we shouldn't, we 408 * also shouldn't update the clear color. 409 * 410 * However, we can't simply predicate-update the clear color (the 411 * commands don't support that). And we would lose track of the 412 * color, preventing us from doing some optimizations later. 413 * 414 * For depth clears, things are even more complicated, because here we 415 * resolve the other levels/layers if they have a different color than 416 * the current one. That resolve can be predicated, but we also set those 417 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated. 418 * Keeping track of the aux state when predication is involved is just 419 * even more complex, so the easiest thing to do when the fast clear 420 * depth is changing is to stall on the CPU and resolve the predication. 421 */ 422 iris_resolve_conditional_render(ice); 423 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER) 424 return; 425 426 for (unsigned res_level = 0; res_level < res->surf.levels; res_level++) { 427 if (!(res->aux.has_hiz & (1 << res_level))) 428 continue; 429 430 const unsigned level_layers = 431 iris_get_num_logical_layers(res, res_level); 432 for (unsigned layer = 0; layer < level_layers; layer++) { 433 if (res_level == level && 434 layer >= box->z && 435 layer < box->z + box->depth) { 436 /* We're going to clear this layer anyway. Leave it alone. */ 437 continue; 438 } 439 440 enum isl_aux_state aux_state = 441 iris_resource_get_aux_state(res, res_level, layer); 442 443 if (aux_state != ISL_AUX_STATE_CLEAR && 444 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) { 445 /* This slice doesn't have any fast-cleared bits. */ 446 continue; 447 } 448 449 /* If we got here, then the level may have fast-clear bits that 450 * use the old clear value. We need to do a depth resolve to get 451 * rid of their use of the clear value before we can change it. 452 * Fortunately, few applications ever change their depth clear 453 * value so this shouldn't happen often. 454 */ 455 iris_hiz_exec(ice, batch, res, res_level, layer, 1, 456 ISL_AUX_OP_FULL_RESOLVE, false); 457 iris_resource_set_aux_state(ice, res, res_level, layer, 1, 458 ISL_AUX_STATE_RESOLVED); 459 } 460 } 461 const union isl_color_value clear_value = { .f32 = {depth, } }; 462 iris_resource_set_clear_color(ice, res, clear_value); 463 update_clear_depth = true; 464 } 465 466 for (unsigned l = 0; l < box->depth; l++) { 467 enum isl_aux_state aux_state = 468 iris_resource_get_aux_state(res, level, box->z + l); 469 if (aux_state != ISL_AUX_STATE_CLEAR) { 470 iris_hiz_exec(ice, batch, res, level, 471 box->z + l, 1, ISL_AUX_OP_FAST_CLEAR, 472 update_clear_depth); 473 } 474 } 475 476 iris_resource_set_aux_state(ice, res, level, box->z, box->depth, 477 ISL_AUX_STATE_CLEAR); 478 ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER; 479} 480 481static void 482clear_depth_stencil(struct iris_context *ice, 483 struct pipe_resource *p_res, 484 unsigned level, 485 const struct pipe_box *box, 486 bool render_condition_enabled, 487 bool clear_depth, 488 bool clear_stencil, 489 float depth, 490 uint8_t stencil) 491{ 492 struct iris_resource *res = (void *) p_res; 493 494 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 495 enum blorp_batch_flags blorp_flags = 0; 496 497 if (render_condition_enabled) { 498 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER) 499 return; 500 501 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) 502 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE; 503 } 504 505 iris_batch_maybe_flush(batch, 1500); 506 507 struct iris_resource *z_res; 508 struct iris_resource *stencil_res; 509 struct blorp_surf z_surf; 510 struct blorp_surf stencil_surf; 511 512 iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res); 513 if (z_res && clear_depth && 514 can_fast_clear_depth(ice, z_res, level, box, depth)) { 515 fast_clear_depth(ice, z_res, level, box, depth); 516 iris_flush_and_dirty_for_history(ice, batch, res); 517 clear_depth = false; 518 z_res = false; 519 } 520 521 /* At this point, we might have fast cleared the depth buffer. So if there's 522 * no stencil clear pending, return early. 523 */ 524 if (!(clear_depth || clear_stencil)) { 525 return; 526 } 527 528 if (z_res) { 529 iris_resource_prepare_depth(ice, batch, z_res, level, box->z, box->depth); 530 iris_blorp_surf_for_resource(&ice->vtbl, &z_surf, &z_res->base, 531 z_res->aux.usage, level, true); 532 } 533 534 struct blorp_batch blorp_batch; 535 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 536 537 if (stencil_res) { 538 iris_blorp_surf_for_resource(&ice->vtbl, &stencil_surf, 539 &stencil_res->base, stencil_res->aux.usage, 540 level, true); 541 } 542 543 blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf, 544 level, box->z, box->depth, 545 box->x, box->y, 546 box->x + box->width, 547 box->y + box->height, 548 clear_depth && z_res, depth, 549 clear_stencil && stencil_res ? 0xff : 0, stencil); 550 551 blorp_batch_finish(&blorp_batch); 552 iris_flush_and_dirty_for_history(ice, batch, res); 553 554 if (z_res) { 555 iris_resource_finish_depth(ice, z_res, level, 556 box->z, box->depth, true); 557 } 558} 559 560/** 561 * The pipe->clear() driver hook. 562 * 563 * This clears buffers attached to the current draw framebuffer. 564 */ 565static void 566iris_clear(struct pipe_context *ctx, 567 unsigned buffers, 568 const union pipe_color_union *p_color, 569 double depth, 570 unsigned stencil) 571{ 572 struct iris_context *ice = (void *) ctx; 573 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer; 574 575 assert(buffers != 0); 576 577 if (buffers & PIPE_CLEAR_DEPTHSTENCIL) { 578 struct pipe_surface *psurf = cso_fb->zsbuf; 579 struct pipe_box box = { 580 .width = cso_fb->width, 581 .height = cso_fb->height, 582 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1, 583 .z = psurf->u.tex.first_layer, 584 }; 585 586 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true, 587 buffers & PIPE_CLEAR_DEPTH, 588 buffers & PIPE_CLEAR_STENCIL, 589 depth, stencil); 590 } 591 592 if (buffers & PIPE_CLEAR_COLOR) { 593 /* pipe_color_union and isl_color_value are interchangeable */ 594 union isl_color_value *color = (void *) p_color; 595 596 for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) { 597 if (buffers & (PIPE_CLEAR_COLOR0 << i)) { 598 struct pipe_surface *psurf = cso_fb->cbufs[i]; 599 struct iris_surface *isurf = (void *) psurf; 600 struct pipe_box box = { 601 .width = cso_fb->width, 602 .height = cso_fb->height, 603 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1, 604 .z = psurf->u.tex.first_layer, 605 }; 606 607 clear_color(ice, psurf->texture, psurf->u.tex.level, &box, 608 true, isurf->view.format, isurf->view.swizzle, 609 *color); 610 } 611 } 612 } 613} 614 615/** 616 * The pipe->clear_texture() driver hook. 617 * 618 * This clears the given texture resource. 619 */ 620static void 621iris_clear_texture(struct pipe_context *ctx, 622 struct pipe_resource *p_res, 623 unsigned level, 624 const struct pipe_box *box, 625 const void *data) 626{ 627 struct iris_context *ice = (void *) ctx; 628 struct iris_screen *screen = (void *) ctx->screen; 629 const struct gen_device_info *devinfo = &screen->devinfo; 630 631 if (util_format_is_depth_or_stencil(p_res->format)) { 632 const struct util_format_description *fmt_desc = 633 util_format_description(p_res->format); 634 635 float depth = 0.0; 636 uint8_t stencil = 0; 637 638 if (fmt_desc->unpack_z_float) 639 fmt_desc->unpack_z_float(&depth, 0, data, 0, 1, 1); 640 641 if (fmt_desc->unpack_s_8uint) 642 fmt_desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1); 643 644 clear_depth_stencil(ice, p_res, level, box, true, true, true, 645 depth, stencil); 646 } else { 647 union isl_color_value color; 648 struct iris_resource *res = (void *) p_res; 649 enum isl_format format = res->surf.format; 650 651 if (!isl_format_supports_rendering(devinfo, format)) { 652 const struct isl_format_layout *fmtl = isl_format_get_layout(format); 653 // XXX: actually just get_copy_format_for_bpb from BLORP 654 // XXX: don't cut and paste this 655 switch (fmtl->bpb) { 656 case 8: format = ISL_FORMAT_R8_UINT; break; 657 case 16: format = ISL_FORMAT_R8G8_UINT; break; 658 case 24: format = ISL_FORMAT_R8G8B8_UINT; break; 659 case 32: format = ISL_FORMAT_R8G8B8A8_UINT; break; 660 case 48: format = ISL_FORMAT_R16G16B16_UINT; break; 661 case 64: format = ISL_FORMAT_R16G16B16A16_UINT; break; 662 case 96: format = ISL_FORMAT_R32G32B32_UINT; break; 663 case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break; 664 default: 665 unreachable("Unknown format bpb"); 666 } 667 668 /* No aux surfaces for non-renderable surfaces */ 669 assert(res->aux.usage == ISL_AUX_USAGE_NONE); 670 } 671 672 isl_color_value_unpack(&color, format, data); 673 674 clear_color(ice, p_res, level, box, true, format, 675 ISL_SWIZZLE_IDENTITY, color); 676 } 677} 678 679/** 680 * The pipe->clear_render_target() driver hook. 681 * 682 * This clears the given render target surface. 683 */ 684static void 685iris_clear_render_target(struct pipe_context *ctx, 686 struct pipe_surface *psurf, 687 const union pipe_color_union *p_color, 688 unsigned dst_x, unsigned dst_y, 689 unsigned width, unsigned height, 690 bool render_condition_enabled) 691{ 692 struct iris_context *ice = (void *) ctx; 693 struct iris_surface *isurf = (void *) psurf; 694 struct pipe_box box = { 695 .x = dst_x, 696 .y = dst_y, 697 .z = psurf->u.tex.first_layer, 698 .width = width, 699 .height = height, 700 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1 701 }; 702 703 /* pipe_color_union and isl_color_value are interchangeable */ 704 union isl_color_value *color = (void *) p_color; 705 706 clear_color(ice, psurf->texture, psurf->u.tex.level, &box, 707 render_condition_enabled, 708 isurf->view.format, isurf->view.swizzle, *color); 709} 710 711/** 712 * The pipe->clear_depth_stencil() driver hook. 713 * 714 * This clears the given depth/stencil surface. 715 */ 716static void 717iris_clear_depth_stencil(struct pipe_context *ctx, 718 struct pipe_surface *psurf, 719 unsigned flags, 720 double depth, 721 unsigned stencil, 722 unsigned dst_x, unsigned dst_y, 723 unsigned width, unsigned height, 724 bool render_condition_enabled) 725{ 726 struct iris_context *ice = (void *) ctx; 727 struct pipe_box box = { 728 .x = dst_x, 729 .y = dst_y, 730 .z = psurf->u.tex.first_layer, 731 .width = width, 732 .height = height, 733 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1 734 }; 735 736 assert(util_format_is_depth_or_stencil(psurf->texture->format)); 737 738 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, 739 render_condition_enabled, 740 flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL, 741 depth, stencil); 742} 743 744void 745iris_init_clear_functions(struct pipe_context *ctx) 746{ 747 ctx->clear = iris_clear; 748 ctx->clear_texture = iris_clear_texture; 749 ctx->clear_render_target = iris_clear_render_target; 750 ctx->clear_depth_stencil = iris_clear_depth_stencil; 751} 752