1/* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef IRIS_CONTEXT_H 24#define IRIS_CONTEXT_H 25 26#include "pipe/p_context.h" 27#include "pipe/p_state.h" 28#include "util/u_debug.h" 29#include "intel/blorp/blorp.h" 30#include "intel/dev/gen_debug.h" 31#include "intel/compiler/brw_compiler.h" 32#include "iris_batch.h" 33#include "iris_binder.h" 34#include "iris_fence.h" 35#include "iris_resource.h" 36#include "iris_screen.h" 37 38struct iris_bo; 39struct iris_context; 40struct blorp_batch; 41struct blorp_params; 42 43#define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27) 44#define IRIS_MAX_TEXTURE_SAMPLERS 32 45/* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */ 46#define IRIS_MAX_ABOS 16 47#define IRIS_MAX_SSBOS 16 48#define IRIS_MAX_VIEWPORTS 16 49#define IRIS_MAX_CLIP_PLANES 8 50 51enum iris_param_domain { 52 BRW_PARAM_DOMAIN_BUILTIN = 0, 53 BRW_PARAM_DOMAIN_IMAGE, 54}; 55 56#define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val)) 57#define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24) 58#define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff) 59#define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset)) 60#define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8) 61#define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf) 62 63/** 64 * Dirty flags. When state changes, we flag some combination of these 65 * to indicate that particular GPU commands need to be re-emitted. 66 * 67 * Each bit typically corresponds to a single 3DSTATE_* command packet, but 68 * in rare cases they map to a group of related packets that need to be 69 * emitted together. 70 * 71 * See iris_upload_render_state(). 72 */ 73#define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0) 74#define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1) 75#define IRIS_DIRTY_SCISSOR_RECT (1ull << 2) 76#define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3) 77#define IRIS_DIRTY_CC_VIEWPORT (1ull << 4) 78#define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5) 79#define IRIS_DIRTY_PS_BLEND (1ull << 6) 80#define IRIS_DIRTY_BLEND_STATE (1ull << 7) 81#define IRIS_DIRTY_RASTER (1ull << 8) 82#define IRIS_DIRTY_CLIP (1ull << 9) 83#define IRIS_DIRTY_SBE (1ull << 10) 84#define IRIS_DIRTY_LINE_STIPPLE (1ull << 11) 85#define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12) 86#define IRIS_DIRTY_MULTISAMPLE (1ull << 13) 87#define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14) 88#define IRIS_DIRTY_SAMPLE_MASK (1ull << 15) 89#define IRIS_DIRTY_SAMPLER_STATES_VS (1ull << 16) 90#define IRIS_DIRTY_SAMPLER_STATES_TCS (1ull << 17) 91#define IRIS_DIRTY_SAMPLER_STATES_TES (1ull << 18) 92#define IRIS_DIRTY_SAMPLER_STATES_GS (1ull << 19) 93#define IRIS_DIRTY_SAMPLER_STATES_PS (1ull << 20) 94#define IRIS_DIRTY_SAMPLER_STATES_CS (1ull << 21) 95#define IRIS_DIRTY_UNCOMPILED_VS (1ull << 22) 96#define IRIS_DIRTY_UNCOMPILED_TCS (1ull << 23) 97#define IRIS_DIRTY_UNCOMPILED_TES (1ull << 24) 98#define IRIS_DIRTY_UNCOMPILED_GS (1ull << 25) 99#define IRIS_DIRTY_UNCOMPILED_FS (1ull << 26) 100#define IRIS_DIRTY_UNCOMPILED_CS (1ull << 27) 101#define IRIS_DIRTY_VS (1ull << 28) 102#define IRIS_DIRTY_TCS (1ull << 29) 103#define IRIS_DIRTY_TES (1ull << 30) 104#define IRIS_DIRTY_GS (1ull << 31) 105#define IRIS_DIRTY_FS (1ull << 32) 106#define IRIS_DIRTY_CS (1ull << 33) 107#define IRIS_DIRTY_URB (1ull << 34) 108#define IRIS_DIRTY_CONSTANTS_VS (1ull << 35) 109#define IRIS_DIRTY_CONSTANTS_TCS (1ull << 36) 110#define IRIS_DIRTY_CONSTANTS_TES (1ull << 37) 111#define IRIS_DIRTY_CONSTANTS_GS (1ull << 38) 112#define IRIS_DIRTY_CONSTANTS_FS (1ull << 39) 113#define IRIS_DIRTY_CONSTANTS_CS (1ull << 40) 114#define IRIS_DIRTY_DEPTH_BUFFER (1ull << 41) 115#define IRIS_DIRTY_WM (1ull << 42) 116#define IRIS_DIRTY_BINDINGS_VS (1ull << 43) 117#define IRIS_DIRTY_BINDINGS_TCS (1ull << 44) 118#define IRIS_DIRTY_BINDINGS_TES (1ull << 45) 119#define IRIS_DIRTY_BINDINGS_GS (1ull << 46) 120#define IRIS_DIRTY_BINDINGS_FS (1ull << 47) 121#define IRIS_DIRTY_BINDINGS_CS (1ull << 48) 122#define IRIS_DIRTY_SO_BUFFERS (1ull << 49) 123#define IRIS_DIRTY_SO_DECL_LIST (1ull << 50) 124#define IRIS_DIRTY_STREAMOUT (1ull << 51) 125#define IRIS_DIRTY_VF_SGVS (1ull << 52) 126#define IRIS_DIRTY_VF (1ull << 53) 127#define IRIS_DIRTY_VF_TOPOLOGY (1ull << 54) 128#define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 55) 129#define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56) 130#define IRIS_DIRTY_VF_STATISTICS (1ull << 57) 131 132#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \ 133 IRIS_DIRTY_SAMPLER_STATES_CS | \ 134 IRIS_DIRTY_UNCOMPILED_CS | \ 135 IRIS_DIRTY_CONSTANTS_CS | \ 136 IRIS_DIRTY_BINDINGS_CS | \ 137 IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES) 138 139#define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE 140 141#define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS | \ 142 IRIS_DIRTY_BINDINGS_TCS | \ 143 IRIS_DIRTY_BINDINGS_TES | \ 144 IRIS_DIRTY_BINDINGS_GS | \ 145 IRIS_DIRTY_BINDINGS_FS | \ 146 IRIS_DIRTY_BINDINGS_CS) 147 148/** 149 * Non-orthogonal state (NOS) dependency flags. 150 * 151 * Shader programs may depend on non-orthogonal state. These flags are 152 * used to indicate that a shader's key depends on the state provided by 153 * a certain Gallium CSO. Changing any CSOs marked as a dependency will 154 * cause the driver to re-compute the shader key, possibly triggering a 155 * shader recompile. 156 */ 157enum iris_nos_dep { 158 IRIS_NOS_FRAMEBUFFER, 159 IRIS_NOS_DEPTH_STENCIL_ALPHA, 160 IRIS_NOS_RASTERIZER, 161 IRIS_NOS_BLEND, 162 IRIS_NOS_LAST_VUE_MAP, 163 164 IRIS_NOS_COUNT, 165}; 166 167struct iris_depth_stencil_alpha_state; 168 169/** 170 * Cache IDs for the in-memory program cache (ice->shaders.cache). 171 */ 172enum iris_program_cache_id { 173 IRIS_CACHE_VS = MESA_SHADER_VERTEX, 174 IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL, 175 IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL, 176 IRIS_CACHE_GS = MESA_SHADER_GEOMETRY, 177 IRIS_CACHE_FS = MESA_SHADER_FRAGMENT, 178 IRIS_CACHE_CS = MESA_SHADER_COMPUTE, 179 IRIS_CACHE_BLORP, 180}; 181 182/** @{ 183 * 184 * Defines for PIPE_CONTROL operations, which trigger cache flushes, 185 * synchronization, pipelined memory writes, and so on. 186 * 187 * The bits here are not the actual hardware values. The actual fields 188 * move between various generations, so we just have flags for each 189 * potential operation, and use genxml to encode the actual packet. 190 */ 191enum pipe_control_flags 192{ 193 PIPE_CONTROL_FLUSH_LLC = (1 << 1), 194 PIPE_CONTROL_LRI_POST_SYNC_OP = (1 << 2), 195 PIPE_CONTROL_STORE_DATA_INDEX = (1 << 3), 196 PIPE_CONTROL_CS_STALL = (1 << 4), 197 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET = (1 << 5), 198 PIPE_CONTROL_SYNC_GFDT = (1 << 6), 199 PIPE_CONTROL_TLB_INVALIDATE = (1 << 7), 200 PIPE_CONTROL_MEDIA_STATE_CLEAR = (1 << 8), 201 PIPE_CONTROL_WRITE_IMMEDIATE = (1 << 9), 202 PIPE_CONTROL_WRITE_DEPTH_COUNT = (1 << 10), 203 PIPE_CONTROL_WRITE_TIMESTAMP = (1 << 11), 204 PIPE_CONTROL_DEPTH_STALL = (1 << 12), 205 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13), 206 PIPE_CONTROL_INSTRUCTION_INVALIDATE = (1 << 14), 207 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15), 208 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16), 209 PIPE_CONTROL_NOTIFY_ENABLE = (1 << 17), 210 PIPE_CONTROL_FLUSH_ENABLE = (1 << 18), 211 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19), 212 PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20), 213 PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21), 214 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), 215 PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23), 216 PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24), 217}; 218 219#define PIPE_CONTROL_CACHE_FLUSH_BITS \ 220 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ 221 PIPE_CONTROL_DATA_CACHE_FLUSH | \ 222 PIPE_CONTROL_RENDER_TARGET_FLUSH) 223 224#define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ 225 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \ 226 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \ 227 PIPE_CONTROL_VF_CACHE_INVALIDATE | \ 228 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ 229 PIPE_CONTROL_INSTRUCTION_INVALIDATE) 230 231enum iris_predicate_state { 232 /* The first two states are used if we can determine whether to draw 233 * without having to look at the values in the query object buffer. This 234 * will happen if there is no conditional render in progress, if the query 235 * object is already completed or if something else has already added 236 * samples to the preliminary result. 237 */ 238 IRIS_PREDICATE_STATE_RENDER, 239 IRIS_PREDICATE_STATE_DONT_RENDER, 240 241 /* In this case whether to draw or not depends on the result of an 242 * MI_PREDICATE command so the predicate enable bit needs to be checked. 243 */ 244 IRIS_PREDICATE_STATE_USE_BIT, 245}; 246 247/** @} */ 248 249/** 250 * A compiled shader variant, containing a pointer to the GPU assembly, 251 * as well as program data and other packets needed by state upload. 252 * 253 * There can be several iris_compiled_shader variants per API-level shader 254 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key). 255 */ 256struct iris_compiled_shader { 257 /** Reference to the uploaded assembly. */ 258 struct iris_state_ref assembly; 259 260 /** Pointer to the assembly in the BO's map. */ 261 void *map; 262 263 /** The program data (owned by the program cache hash table) */ 264 struct brw_stage_prog_data *prog_data; 265 266 /** A list of system values to be uploaded as uniforms. */ 267 enum brw_param_builtin *system_values; 268 unsigned num_system_values; 269 270 /** Number of constbufs expected by the shader. */ 271 unsigned num_cbufs; 272 273 /** 274 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets 275 * (the VUE-based information for transform feedback outputs). 276 */ 277 uint32_t *streamout; 278 279 /** 280 * Shader packets and other data derived from prog_data. These must be 281 * completely determined from prog_data. 282 */ 283 uint8_t derived_data[0]; 284}; 285 286/** 287 * API context state that is replicated per shader stage. 288 */ 289struct iris_shader_state { 290 /** Uniform Buffers */ 291 struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS]; 292 struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS]; 293 294 struct pipe_constant_buffer cbuf0; 295 bool cbuf0_needs_upload; 296 297 /** Shader Storage Buffers */ 298 struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS]; 299 struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS]; 300 301 /** Shader Storage Images (image load store) */ 302 struct iris_image_view image[PIPE_MAX_SHADER_IMAGES]; 303 304 struct iris_state_ref sampler_table; 305 struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS]; 306 struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS]; 307 308 /** Bitfield of which constant buffers are bound (non-null). */ 309 uint32_t bound_cbufs; 310 311 /** Bitfield of which image views are bound (non-null). */ 312 uint32_t bound_image_views; 313 314 /** Bitfield of which sampler views are bound (non-null). */ 315 uint32_t bound_sampler_views; 316 317 /** Bitfield of which shader storage buffers are bound (non-null). */ 318 uint32_t bound_ssbos; 319 320 /** Bitfield of which shader storage buffers are writable. */ 321 uint32_t writable_ssbos; 322}; 323 324/** 325 * Gallium CSO for stream output (transform feedback) targets. 326 */ 327struct iris_stream_output_target { 328 struct pipe_stream_output_target base; 329 330 /** Storage holding the offset where we're writing in the buffer */ 331 struct iris_state_ref offset; 332 333 /** Stride (dwords-per-vertex) during this transform feedback operation */ 334 uint16_t stride; 335 336 /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */ 337 bool zeroed; 338}; 339 340/** 341 * Virtual table for generation-specific (genxml) function calls. 342 */ 343struct iris_vtable { 344 void (*destroy_state)(struct iris_context *ice); 345 void (*init_render_context)(struct iris_screen *screen, 346 struct iris_batch *batch, 347 struct iris_vtable *vtbl, 348 struct pipe_debug_callback *dbg); 349 void (*init_compute_context)(struct iris_screen *screen, 350 struct iris_batch *batch, 351 struct iris_vtable *vtbl, 352 struct pipe_debug_callback *dbg); 353 void (*upload_render_state)(struct iris_context *ice, 354 struct iris_batch *batch, 355 const struct pipe_draw_info *draw); 356 void (*update_surface_base_address)(struct iris_batch *batch, 357 struct iris_binder *binder); 358 void (*upload_compute_state)(struct iris_context *ice, 359 struct iris_batch *batch, 360 const struct pipe_grid_info *grid); 361 void (*rebind_buffer)(struct iris_context *ice, 362 struct iris_resource *res, 363 uint64_t old_address); 364 void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst, 365 uint32_t src); 366 void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst, 367 uint32_t src); 368 void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg, 369 uint32_t val); 370 void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg, 371 uint64_t val); 372 void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg, 373 struct iris_bo *bo, uint32_t offset); 374 void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg, 375 struct iris_bo *bo, uint32_t offset); 376 void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg, 377 struct iris_bo *bo, uint32_t offset, 378 bool predicated); 379 void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg, 380 struct iris_bo *bo, uint32_t offset, 381 bool predicated); 382 void (*store_data_imm32)(struct iris_batch *batch, 383 struct iris_bo *bo, uint32_t offset, 384 uint32_t value); 385 void (*store_data_imm64)(struct iris_batch *batch, 386 struct iris_bo *bo, uint32_t offset, 387 uint64_t value); 388 void (*copy_mem_mem)(struct iris_batch *batch, 389 struct iris_bo *dst_bo, uint32_t dst_offset, 390 struct iris_bo *src_bo, uint32_t src_offset, 391 unsigned bytes); 392 void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags, 393 struct iris_bo *bo, uint32_t offset, 394 uint64_t imm); 395 396 unsigned (*derived_program_state_size)(enum iris_program_cache_id id); 397 void (*store_derived_program_state)(struct iris_context *ice, 398 enum iris_program_cache_id cache_id, 399 struct iris_compiled_shader *shader); 400 uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol, 401 const struct brw_vue_map *vue_map); 402 void (*populate_vs_key)(const struct iris_context *ice, 403 const struct shader_info *info, 404 struct brw_vs_prog_key *key); 405 void (*populate_tcs_key)(const struct iris_context *ice, 406 struct brw_tcs_prog_key *key); 407 void (*populate_tes_key)(const struct iris_context *ice, 408 struct brw_tes_prog_key *key); 409 void (*populate_gs_key)(const struct iris_context *ice, 410 struct brw_gs_prog_key *key); 411 void (*populate_fs_key)(const struct iris_context *ice, 412 struct brw_wm_prog_key *key); 413 void (*populate_cs_key)(const struct iris_context *ice, 414 struct brw_cs_prog_key *key); 415 uint32_t (*mocs)(const struct iris_bo *bo); 416}; 417 418/** 419 * A pool containing SAMPLER_BORDER_COLOR_STATE entries. 420 * 421 * See iris_border_color.c for more information. 422 */ 423struct iris_border_color_pool { 424 struct iris_bo *bo; 425 void *map; 426 unsigned insert_point; 427 428 /** Map from border colors to offsets in the buffer. */ 429 struct hash_table *ht; 430}; 431 432/** 433 * The API context (derived from pipe_context). 434 * 435 * Most driver state is tracked here. 436 */ 437struct iris_context { 438 struct pipe_context ctx; 439 440 /** A debug callback for KHR_debug output. */ 441 struct pipe_debug_callback dbg; 442 443 /** Slab allocator for iris_transfer_map objects. */ 444 struct slab_child_pool transfer_pool; 445 446 struct iris_vtable vtbl; 447 448 struct blorp_context blorp; 449 450 struct iris_batch batches[IRIS_BATCH_COUNT]; 451 452 struct u_upload_mgr *query_buffer_uploader; 453 454 struct { 455 struct { 456 /** 457 * Either the value of BaseVertex for indexed draw calls or the value 458 * of the argument <first> for non-indexed draw calls. 459 */ 460 int firstvertex; 461 int baseinstance; 462 } params; 463 464 /** 465 * Resource and offset that stores draw_parameters from the indirect 466 * buffer or to the buffer that stures the previous values for non 467 * indirect draws. 468 */ 469 struct pipe_resource *draw_params_res; 470 uint32_t draw_params_offset; 471 472 struct { 473 /** 474 * The value of DrawID. This always comes in from it's own vertex 475 * buffer since it's not part of the indirect draw parameters. 476 */ 477 int drawid; 478 479 /** 480 * Stores if an indexed or non-indexed draw (~0/0). Useful to 481 * calculate BaseVertex as an AND of firstvertex and is_indexed_draw. 482 */ 483 int is_indexed_draw; 484 } derived_params; 485 486 /** 487 * Resource and offset used for GL_ARB_shader_draw_parameters which 488 * contains parameters that are not present in the indirect buffer as 489 * drawid and is_indexed_draw. They will go in their own vertex element. 490 */ 491 struct pipe_resource *derived_draw_params_res; 492 uint32_t derived_draw_params_offset; 493 494 bool is_indirect; 495 } draw; 496 497 struct { 498 struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES]; 499 struct iris_compiled_shader *prog[MESA_SHADER_STAGES]; 500 struct brw_vue_map *last_vue_map; 501 502 struct u_upload_mgr *uploader; 503 struct hash_table *cache; 504 505 unsigned urb_size; 506 507 /** Is a GS or TES outputting points or lines? */ 508 bool output_topology_is_points_or_lines; 509 510 /* Track last VS URB entry size */ 511 unsigned last_vs_entry_size; 512 513 /** 514 * Scratch buffers for various sizes and stages. 515 * 516 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding, 517 * and shader stage. 518 */ 519 struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES]; 520 } shaders; 521 522 struct { 523 struct iris_query *query; 524 bool condition; 525 } condition; 526 527 struct { 528 uint64_t dirty; 529 uint64_t dirty_for_nos[IRIS_NOS_COUNT]; 530 531 unsigned num_viewports; 532 unsigned sample_mask; 533 struct iris_blend_state *cso_blend; 534 struct iris_rasterizer_state *cso_rast; 535 struct iris_depth_stencil_alpha_state *cso_zsa; 536 struct iris_vertex_element_state *cso_vertex_elements; 537 struct pipe_blend_color blend_color; 538 struct pipe_poly_stipple poly_stipple; 539 struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS]; 540 struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS]; 541 struct pipe_stencil_ref stencil_ref; 542 struct pipe_framebuffer_state framebuffer; 543 struct pipe_clip_state clip_planes; 544 545 float default_outer_level[4]; 546 float default_inner_level[2]; 547 548 /** Bitfield of which vertex buffers are bound (non-null). */ 549 uint64_t bound_vertex_buffers; 550 551 bool primitive_restart; 552 unsigned cut_index; 553 enum pipe_prim_type prim_mode:8; 554 bool prim_is_points_or_lines; 555 uint8_t vertices_per_patch; 556 557 /** The last compute grid size */ 558 uint32_t last_grid[3]; 559 /** Reference to the BO containing the compute grid size */ 560 struct iris_state_ref grid_size; 561 /** Reference to the SURFACE_STATE for the compute grid resource */ 562 struct iris_state_ref grid_surf_state; 563 564 /** 565 * Array of aux usages for drawing, altered to account for any 566 * self-dependencies from resources bound for sampling and rendering. 567 */ 568 enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS]; 569 570 /** Bitfield of whether color blending is enabled for RT[i] */ 571 uint8_t blend_enables; 572 573 /** Are depth writes enabled? (Depth buffer may or may not exist.) */ 574 bool depth_writes_enabled; 575 576 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */ 577 bool stencil_writes_enabled; 578 579 /** GenX-specific current state */ 580 struct iris_genx_state *genx; 581 582 struct iris_shader_state shaders[MESA_SHADER_STAGES]; 583 584 /** Do vertex shader uses shader draw parameters ? */ 585 bool vs_uses_draw_params; 586 bool vs_uses_derived_draw_params; 587 bool vs_needs_sgvs_element; 588 589 /** Do vertex shader uses edge flag ? */ 590 bool vs_needs_edge_flag; 591 592 /** Do any samplers need border color? One bit per shader stage. */ 593 uint8_t need_border_colors; 594 595 struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS]; 596 bool streamout_active; 597 598 bool statistics_counters_enabled; 599 600 /** Current conditional rendering mode */ 601 enum iris_predicate_state predicate; 602 603 /** 604 * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the 605 * render context that needs to be uploaded to the compute context. 606 */ 607 struct iris_bo *compute_predicate; 608 609 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */ 610 bool prims_generated_query_active; 611 612 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */ 613 uint32_t *streamout; 614 615 /** Current strides for each streamout buffer */ 616 uint16_t *streamout_strides; 617 618 /** The SURFACE_STATE for a 1x1x1 null surface. */ 619 struct iris_state_ref unbound_tex; 620 621 /** The SURFACE_STATE for a framebuffer-sized null surface. */ 622 struct iris_state_ref null_fb; 623 624 struct u_upload_mgr *surface_uploader; 625 // XXX: may want a separate uploader for "hey I made a CSO!" vs 626 // "I'm streaming this out at draw time and never want it again!" 627 struct u_upload_mgr *dynamic_uploader; 628 629 struct iris_binder binder; 630 631 struct iris_border_color_pool border_color_pool; 632 633 /** The high 16-bits of the last VBO/index buffer addresses */ 634 uint16_t last_vbo_high_bits[33]; 635 uint16_t last_index_bo_high_bits; 636 637 /** 638 * Resources containing streamed state which our render context 639 * currently points to. Used to re-add these to the validation 640 * list when we start a new batch and haven't resubmitted commands. 641 */ 642 struct { 643 struct pipe_resource *cc_vp; 644 struct pipe_resource *sf_cl_vp; 645 struct pipe_resource *color_calc; 646 struct pipe_resource *scissor; 647 struct pipe_resource *blend; 648 struct pipe_resource *index_buffer; 649 } last_res; 650 } state; 651}; 652 653#define perf_debug(dbg, ...) do { \ 654 if (INTEL_DEBUG & DEBUG_PERF) \ 655 dbg_printf(__VA_ARGS__); \ 656 if (unlikely(dbg)) \ 657 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \ 658} while(0) 659 660double get_time(void); 661 662struct pipe_context * 663iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags); 664 665void iris_init_blit_functions(struct pipe_context *ctx); 666void iris_init_clear_functions(struct pipe_context *ctx); 667void iris_init_program_functions(struct pipe_context *ctx); 668void iris_init_resource_functions(struct pipe_context *ctx); 669void iris_init_query_functions(struct pipe_context *ctx); 670void iris_update_compiled_shaders(struct iris_context *ice); 671void iris_update_compiled_compute_shader(struct iris_context *ice); 672void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data, 673 uint32_t *dst); 674 675 676/* iris_blit.c */ 677void iris_blorp_surf_for_resource(struct iris_vtable *vtbl, 678 struct blorp_surf *surf, 679 struct pipe_resource *p_res, 680 enum isl_aux_usage aux_usage, 681 unsigned level, 682 bool is_render_target); 683void iris_copy_region(struct blorp_context *blorp, 684 struct iris_batch *batch, 685 struct pipe_resource *dst, 686 unsigned dst_level, 687 unsigned dstx, unsigned dsty, unsigned dstz, 688 struct pipe_resource *src, 689 unsigned src_level, 690 const struct pipe_box *src_box); 691 692/* iris_draw.c */ 693 694void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 695void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *); 696 697/* iris_pipe_control.c */ 698 699void iris_emit_pipe_control_flush(struct iris_batch *batch, 700 uint32_t flags); 701void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags, 702 struct iris_bo *bo, uint32_t offset, 703 uint64_t imm); 704void iris_emit_end_of_pipe_sync(struct iris_batch *batch, 705 uint32_t flags); 706 707void iris_init_flush_functions(struct pipe_context *ctx); 708 709/* iris_blorp.c */ 710void gen8_init_blorp(struct iris_context *ice); 711void gen9_init_blorp(struct iris_context *ice); 712void gen10_init_blorp(struct iris_context *ice); 713void gen11_init_blorp(struct iris_context *ice); 714 715/* iris_border_color.c */ 716 717void iris_init_border_color_pool(struct iris_context *ice); 718void iris_destroy_border_color_pool(struct iris_context *ice); 719void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count); 720uint32_t iris_upload_border_color(struct iris_context *ice, 721 union pipe_color_union *color); 722 723/* iris_state.c */ 724void gen8_init_state(struct iris_context *ice); 725void gen9_init_state(struct iris_context *ice); 726void gen10_init_state(struct iris_context *ice); 727void gen11_init_state(struct iris_context *ice); 728void gen8_emit_urb_setup(struct iris_context *ice, 729 struct iris_batch *batch, 730 const unsigned size[4], 731 bool tess_present, bool gs_present); 732void gen9_emit_urb_setup(struct iris_context *ice, 733 struct iris_batch *batch, 734 const unsigned size[4], 735 bool tess_present, bool gs_present); 736void gen10_emit_urb_setup(struct iris_context *ice, 737 struct iris_batch *batch, 738 const unsigned size[4], 739 bool tess_present, bool gs_present); 740void gen11_emit_urb_setup(struct iris_context *ice, 741 struct iris_batch *batch, 742 const unsigned size[4], 743 bool tess_present, bool gs_present); 744 745/* iris_program.c */ 746const struct shader_info *iris_get_shader_info(const struct iris_context *ice, 747 gl_shader_stage stage); 748struct iris_bo *iris_get_scratch_space(struct iris_context *ice, 749 unsigned per_thread_scratch, 750 gl_shader_stage stage); 751 752/* iris_program_cache.c */ 753 754void iris_init_program_cache(struct iris_context *ice); 755void iris_destroy_program_cache(struct iris_context *ice); 756void iris_print_program_cache(struct iris_context *ice); 757struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice, 758 enum iris_program_cache_id, 759 uint32_t key_size, 760 const void *key); 761struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice, 762 enum iris_program_cache_id, 763 uint32_t key_size, 764 const void *key, 765 const void *assembly, 766 struct brw_stage_prog_data *, 767 uint32_t *streamout, 768 enum brw_param_builtin *sysv, 769 unsigned num_system_values, 770 unsigned num_cbufs); 771const void *iris_find_previous_compile(const struct iris_context *ice, 772 enum iris_program_cache_id cache_id, 773 unsigned program_string_id); 774bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch, 775 const void *key, 776 uint32_t key_size, 777 uint32_t *kernel_out, 778 void *prog_data_out); 779bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, 780 const void *key, uint32_t key_size, 781 const void *kernel, uint32_t kernel_size, 782 const struct brw_stage_prog_data *prog_data, 783 uint32_t prog_data_size, 784 uint32_t *kernel_out, 785 void *prog_data_out); 786 787/* iris_query.c */ 788 789void iris_math_div32_gpr0(struct iris_context *ice, 790 struct iris_batch *batch, 791 uint32_t D); 792void iris_math_add32_gpr0(struct iris_context *ice, 793 struct iris_batch *batch, 794 uint32_t x); 795 796uint64_t iris_timebase_scale(const struct gen_device_info *devinfo, 797 uint64_t gpu_timestamp); 798void iris_resolve_conditional_render(struct iris_context *ice); 799 800/* iris_resolve.c */ 801 802void iris_predraw_resolve_inputs(struct iris_context *ice, 803 struct iris_batch *batch, 804 bool *draw_aux_buffer_disabled, 805 gl_shader_stage stage, 806 bool consider_framebuffer); 807void iris_predraw_resolve_framebuffer(struct iris_context *ice, 808 struct iris_batch *batch, 809 bool *draw_aux_buffer_disabled); 810void iris_postdraw_update_resolve_tracking(struct iris_context *ice, 811 struct iris_batch *batch); 812void iris_cache_sets_clear(struct iris_batch *batch); 813void iris_flush_depth_and_render_caches(struct iris_batch *batch); 814void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo); 815void iris_cache_flush_for_render(struct iris_batch *batch, 816 struct iris_bo *bo, 817 enum isl_format format, 818 enum isl_aux_usage aux_usage); 819void iris_render_cache_add_bo(struct iris_batch *batch, 820 struct iris_bo *bo, 821 enum isl_format format, 822 enum isl_aux_usage aux_usage); 823void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo); 824void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo); 825 826/* iris_state.c */ 827void gen9_toggle_preemption(struct iris_context *ice, 828 struct iris_batch *batch, 829 const struct pipe_draw_info *draw); 830#endif 831