1b8e80941Smrg/* 2b8e80941Smrg * Copyright © 2018 Intel Corporation 3b8e80941Smrg * 4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5b8e80941Smrg * copy of this software and associated documentation files (the "Software"), 6b8e80941Smrg * to deal in the Software without restriction, including without limitation 7b8e80941Smrg * on the rights to use, copy, modify, merge, publish, distribute, sub 8b8e80941Smrg * license, and/or sell copies of the Software, and to permit persons to whom 9b8e80941Smrg * the Software is furnished to do so, subject to the following conditions: 10b8e80941Smrg * 11b8e80941Smrg * The above copyright notice and this permission notice (including the next 12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the 13b8e80941Smrg * Software. 14b8e80941Smrg * 15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18b8e80941Smrg * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19b8e80941Smrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20b8e80941Smrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21b8e80941Smrg * USE OR OTHER DEALINGS IN THE SOFTWARE. 22b8e80941Smrg */ 23b8e80941Smrg#ifndef IRIS_DEFINES_H 24b8e80941Smrg#define IRIS_DEFINES_H 25b8e80941Smrg 26b8e80941Smrg/** 27b8e80941Smrg * @file iris_defines.h 28b8e80941Smrg * 29b8e80941Smrg * Random hardware #defines that we're not using GENXML for. 30b8e80941Smrg */ 31b8e80941Smrg 32b8e80941Smrg#define MI_PREDICATE (0xC << 23) 33b8e80941Smrg# define MI_PREDICATE_LOADOP_KEEP (0 << 6) 34b8e80941Smrg# define MI_PREDICATE_LOADOP_LOAD (2 << 6) 35b8e80941Smrg# define MI_PREDICATE_LOADOP_LOADINV (3 << 6) 36b8e80941Smrg# define MI_PREDICATE_COMBINEOP_SET (0 << 3) 37b8e80941Smrg# define MI_PREDICATE_COMBINEOP_AND (1 << 3) 38b8e80941Smrg# define MI_PREDICATE_COMBINEOP_OR (2 << 3) 39b8e80941Smrg# define MI_PREDICATE_COMBINEOP_XOR (3 << 3) 40b8e80941Smrg# define MI_PREDICATE_COMPAREOP_TRUE (0 << 0) 41b8e80941Smrg# define MI_PREDICATE_COMPAREOP_FALSE (1 << 0) 42b8e80941Smrg# define MI_PREDICATE_COMPAREOP_SRCS_EQUAL (2 << 0) 43b8e80941Smrg# define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL (3 << 0) 44b8e80941Smrg 45b8e80941Smrg/* Predicate registers */ 46b8e80941Smrg#define MI_PREDICATE_SRC0 0x2400 47b8e80941Smrg#define MI_PREDICATE_SRC1 0x2408 48b8e80941Smrg#define MI_PREDICATE_DATA 0x2410 49b8e80941Smrg#define MI_PREDICATE_RESULT 0x2418 50b8e80941Smrg#define MI_PREDICATE_RESULT_1 0x241C 51b8e80941Smrg#define MI_PREDICATE_RESULT_2 0x2214 52b8e80941Smrg 53b8e80941Smrg#define CS_GPR(n) (0x2600 + (n) * 8) 54b8e80941Smrg 55b8e80941Smrg/* The number of bits in our TIMESTAMP queries. */ 56b8e80941Smrg#define TIMESTAMP_BITS 36 57b8e80941Smrg 58b8e80941Smrg#endif 59